AllSpiceMirrors/jellyfish-powersupply
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21a3dedb0c
jellyfish-powersupply/hw/mcu.kicad_sch
Igor Brkic 21a3dedb0c routing done 90%, board layout defined
2024-06-22 18:39:47 +02:00

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1 2 3 4 5 6 1 2 3 4 5 6 D C B A D C B A Date: 2024-04-10 Size: A4 Id: / File: blob_658d39ce47ca79d8f97d108a2adc9e992773bd53_1508028890.kicad_sch Sheet: / KiCad E.D.A. eeschema 8.0 SPDX-FileCopyrightText: 2024 Igor Brkic <igor@hyperglitch.com> SPDX-License-Identifier: CERN-OHL-S-2.0 Title: JellyfishOPP Rev: 1 HYPERGLITCH Ltd C249 15pF C225 100nF VTref 1 nRESET 10 SWDIO/TMS 2 GND 3 SWCLK/TCK 4 5V 5 SWO/TDO 6 RTCK 7 TDI 8 TRST 9 J10 C251 2.2uF C232 15pF C230 330pF Tri-State 1 GND 2 OUT 3 VDD 4 X1 24MHz C250 1uF R197 12k C233 100nF 1 2 J11 1 2 3 4 Y2 24MHz C231 1uF 1 2 3 4 Y3 24MHz C248 4.7uF C234 100nF R203 0R R250 10k R195 1M C239 100nF C224 100nF R202 0R C222 4.7uF C253 2.2uF C223 100nF C244 100nF C229 100nF R206 5.1k C227 100nF R204 10k C243 100nF C246 15pF GND 1 EXTVBUS 10 NXT 11 DIR 12 STP 13 CLKOUT 14 VDD1.8 15 VDD3.3 16 DATA7 17 DATA6 18 DATA5 19 GND 2 DATA4 20 DATA3 21 DATA2 22 DATA1 23 DATA0 24 VDD3.3 25 VDD1.8 26 XO 27 XI 28 VDDA1.8 29 CPEN 3 VDD3.3 30 REG_EN 31 RBIAS 32 GND 33 VBUS 4 ID 5 VDD3.3 6 DP 7 DM 8 RESET 9 U46 USB3300-EZK C226 15pF R200 33R C252 100nF R196 470R C242 4.7uF R201 33R R205 5.1k R199 0R C228 4.7uF C241 100nF R244 10k TP9 R198 0R C247 4.7uF C245 100nF TP8 C238 100nF TP7 TP6 C237 100nF C236 100nF PE2 1 VSS 10 VDD 100 VDD 11 PH0 12 PH1 13 NRST 14 PC0 15 PC1 16 PC2 17 PC3 18 VDD 19 PE3 2 VSSA 20 VREF+ 21 VDDA 22 PA0 23 PA1 24 PA2 25 PA3 26 VDD 28 PA4 29 PE4 3 PA5 30 PA6 31 PA7 32 PC4 33 PC5 34 PB0 35 PB1 36 PB2 37 PE7 38 PE8 39 PE5 4 PE9 40 PE10 41 PE11 42 PE12 43 PE13 44 PE14 45 PE15 46 PB10 47 VCAP_1 48 PE6 5 VDD 50 PB12 51 PB13 52 PB14 53 PB15 54 PD8 55 PD9 56 PD10 57 PD11 58 PD12 59 VBAT 6 PD13 60 PD14 61 PD15 62 PC6 63 PC7 64 PC8 65 PC9 66 PA8 67 PA9 68 PA10 69 PC13 7 PA11 70 PA12 71 PA13 72 VCAP_2 73 VDD 75 PA14 76 PA15 77 PC10 78 PC11 79 PC14 8 PC12 80 PD0 81 PD1 82 PD2 83 PD3 84 PD4 85 PD5 86 PD6 87 PD7 88 PB3 89 PC15 9 PB4 90 PB5 91 PB6 92 PB7 93 BOOT0 94 PB8 95 PB9 96 PE0 97 PE1 98 U47 STM32F446VETx +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V +3.3V SCL DISP_DC LED_B SPI1_SCK{slash}SWO USB_ULPI_D2 SPI2_MISO ENC_B QSPI_NCS 24MHz_CLK DISP_NCS USB_ULPI_D1 LED_R DISP_SCL EN_USB1 VSENSE_USB0 nRST EN_DC USB_ULPI_D5 ENC_B SPI1_MISO DISP_SCL QSPI_BK1_IO1 QSPI_BK1_IO0 USB_ULPI_CK D- SPI1_MOSI VSENSE_DC QSPI_BK2_IO1 ENC_SW LED_R EN_USB1 QSPI_BK2_IO0 DISP_RES VBUS DISP_BLK DISP_MOSI USB_ULPI_DIR QSPI_BK2_IO3 D+ USART1_TX EN_ISO USB_ULPI_D6 DISP_MOSI USB_ULPI_D0 QSPI_BK2_IO1 SWDIO SWCLK EN_ISO USB_ULPI_D5 {NTC[1..2]} USB_ULPI_D4 QSPI_BK1_IO3 USB_ULPI_DIR SDA USB_ULPI_STP ENC_A QSPI_BK1_IO2 SDA VSENSE_USB1 QSPI_BK2_IO2 USB_ULPI_D3 24MHz_CLK USB_ULPI_D7 SCL USB_ULPI_NXT QSPI_CLK DISP_NCS QSPI_NCS NTC1 USB_ULPI_D3 QSPI_BK2_IO3 USB_ULPI_D0 USB_ULPI_D2 LED_B QSPI_BK1_IO3 USB_ULPI_D6 USB_ULPI_STP QSPI_BK1_IO2 DISP_DC SWDIO USB_ULPI_NXT DISP_BLK DISP_RES SWCLK NTC2 USB_ULPI_D7 QSPI_BK1_IO0 EN_DC ENC_A LED_G USB_ULPI_D1 SPI1_NSS SPI1_SCK{slash}SWO LED_G QSPI_BK2_IO0 nRST USB_ULPI_CK QSPI_BK2_IO2 QSPI_BK1_IO1 USART1_RX ENC_SW USB_ULPI_D4 QSPI_CLK AUX_ENABLE EXT_IN_ENABLE {I2C} {ENCODER} {NTC[1..2]} EN_PREREG AUX_ISENSE {USB} {CTRL_PWRIN} {VSENSE_PWRIN} 24MHz_CLK {QSPI} {DISP} OUTPUT_ENABLE BUTTON AUX_VSENSE {RGB_LED} USB3300-EZK symbol from the Interface_USB library has pins 15 and 26 defined as "Power Output". Those two pins need to be connected together according to the datasheet which causes ERC error (flexible) (flexible) Vdda decoupling Oscillator is used to clock the whole system and provide the stable clock. The crystal is left as a backup option for testing. (flexible) (flexible) Vdd decoupling (flexible) (flexible) (flexible) CL1 = CL2 = 2*(Cl - Cs) = 2*(12 - 5) = 14pF ~= 15pF (flexible) (flexible) (flexible)
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