AllSpiceMirrors/kicad
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Must check for implicit min separately from opt/max.

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Fixes https://gitlab.com/kicad/code/kicad/-/issues/19012
This commit is contained in:
Jeff Young 2024-10-29 16:30:32 +00:00
parent f1abdfa1aa
commit 7074c31374
6 changed files with 12 additions and 5 deletions

5
pcbnew/drc/drc_engine.cpp
View File

@ -722,7 +722,12 @@ DRC_CONSTRAINT DRC_ENGINE::EvalRules( DRC_CONSTRAINT_T aConstraintType, const BO
[&]( const DRC_ENGINE_CONSTRAINT* c )
{
if( c->constraint.m_Value.HasMin() )
{
if( c->parentRule && c->parentRule->m_Implicit )
constraint.m_ImplicitMin = true;
constraint.m_Value.SetMin( c->constraint.m_Value.Min() );
}
if( c->constraint.m_Value.HasOpt() )
constraint.m_Value.SetOpt( c->constraint.m_Value.Opt() );

4
pcbnew/drc/drc_rule.h
View File

@ -125,7 +125,7 @@ public:
class DRC_CONSTRAINT
{
public:
public:
DRC_CONSTRAINT( DRC_CONSTRAINT_T aType = NULL_CONSTRAINT,
const wxString& aName = wxEmptyString ) :
m_Type( aType ),
@ -133,6 +133,7 @@ class DRC_CONSTRAINT
m_DisallowFlags( 0 ),
m_ZoneConnection( ZONE_CONNECTION::INHERITED ),
m_Test( nullptr ),
m_ImplicitMin( false ),
m_name( aName ),
m_parentRule( nullptr )
{
@ -190,6 +191,7 @@ public:
int m_DisallowFlags;
ZONE_CONNECTION m_ZoneConnection;
DRC_RULE_CONDITION* m_Test;
bool m_ImplicitMin;
private:
wxString m_name; // For just-in-time constraints

2
pcbnew/drc/drc_test_provider_hole_size.cpp
View File

@ -229,7 +229,7 @@ void DRC_TEST_PROVIDER_HOLE_SIZE::checkViaHole( PCB_VIA* via, bool aExceedMicro,
if( fail_min )
{
if( constraint.GetParentRule() && constraint.GetParentRule()->m_Implicit )
if( constraint.m_ImplicitMin )
constraintName = _( "board setup constraints" );
msg = formatMsg( _( "(%s min hole %s; actual %s)" ),

2
pcbnew/drc/drc_test_provider_track_segment_length.cpp
View File

@ -132,7 +132,7 @@ bool DRC_TEST_PROVIDER_TRACK_SEGMENT_LENGTH::Run()
if( fail_min )
{
if( constraint.GetParentRule() && constraint.GetParentRule()->m_Implicit )
if( constraint.m_ImplicitMin )
constraintName = _( "board setup constraints" );
msg = formatMsg( _( "(%s min length %s; actual %s)" ),

2
pcbnew/drc/drc_test_provider_track_width.cpp
View File

@ -131,7 +131,7 @@ bool DRC_TEST_PROVIDER_TRACK_WIDTH::Run()
if( fail_min )
{
if( constraint.GetParentRule() && constraint.GetParentRule()->m_Implicit )
if( constraint.m_ImplicitMin )
constraintName = _( "board setup constraints" );
msg = formatMsg( _( "(%s min width %s; actual %s)" ),

2
pcbnew/drc/drc_test_provider_via_diameter.cpp
View File

@ -117,7 +117,7 @@ bool DRC_TEST_PROVIDER_VIA_DIAMETER::Run()
if( fail_min )
{
if( constraint.GetParentRule() && constraint.GetParentRule()->m_Implicit )
if( constraint.m_ImplicitMin )
constraintName = _( "board setup constraints" );
msg = formatMsg( _( "(%s min diameter %s; actual %s)" ),