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mirror of https://gitlab.com/kicad/code/kicad.git synced 2024-11-22 17:55:01 +00:00
kicad/qa/data/pcbnew/unconnected-netnames/unconnected-netnames.kicad_pcb
Seth Hillbrand f61d400d88 Allow non-identical schematic/pcb nets
The schematic net names are fully unique but if we have multiple pads
that are mapped to a NC pin, they need to have unique net names so that
they do not get connected to each other in the ratsnest.  This breaks
the schematic parity check as we have modified the netname for some
pads.  To work around this, we first maintain the zero-th net without
suffix and then add an additional check in DRC to ensure that we allow
unconnected nets as long as the share a common prefix with the schematic
netname.
2024-04-15 17:54:44 -07:00

313 lines
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(generator_version "8.0")
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(legacy_teardrops no)
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(paper "A4")
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(31 "B.Cu" signal)
(32 "B.Adhes" user "B.Adhesive")
(33 "F.Adhes" user "F.Adhesive")
(34 "B.Paste" user)
(35 "F.Paste" user)
(36 "B.SilkS" user "B.Silkscreen")
(37 "F.SilkS" user "F.Silkscreen")
(38 "B.Mask" user)
(39 "F.Mask" user)
(40 "Dwgs.User" user "User.Drawings")
(41 "Cmts.User" user "User.Comments")
(42 "Eco1.User" user "User.Eco1")
(43 "Eco2.User" user "User.Eco2")
(44 "Edge.Cuts" user)
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(46 "B.CrtYd" user "B.Courtyard")
(47 "F.CrtYd" user "F.Courtyard")
(48 "B.Fab" user)
(49 "F.Fab" user)
(50 "User.1" user)
(51 "User.2" user)
(52 "User.3" user)
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(54 "User.5" user)
(55 "User.6" user)
(56 "User.7" user)
(57 "User.8" user)
(58 "User.9" user)
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(setup
(pad_to_mask_clearance 0)
(allow_soldermask_bridges_in_footprints no)
(pcbplotparams
(layerselection 0x00010fc_ffffffff)
(plot_on_all_layers_selection 0x0000000_00000000)
(disableapertmacros no)
(usegerberextensions no)
(usegerberattributes yes)
(usegerberadvancedattributes yes)
(creategerberjobfile yes)
(dashed_line_dash_ratio 12.000000)
(dashed_line_gap_ratio 3.000000)
(svgprecision 4)
(plotframeref no)
(viasonmask no)
(mode 1)
(useauxorigin no)
(hpglpennumber 1)
(hpglpenspeed 20)
(hpglpendiameter 15.000000)
(pdf_front_fp_property_popups yes)
(pdf_back_fp_property_popups yes)
(dxfpolygonmode yes)
(dxfimperialunits yes)
(dxfusepcbnewfont yes)
(psnegative no)
(psa4output no)
(plotreference yes)
(plotvalue yes)
(plotfptext yes)
(plotinvisibletext no)
(sketchpadsonfab no)
(subtractmaskfromsilk no)
(outputformat 1)
(mirror no)
(drillshape 1)
(scaleselection 1)
(outputdirectory "")
)
)
(net 0 "")
(net 1 "unconnected-(TP1-Pad1)")
(net 2 "unconnected-(TP1-Pad1)_0")
(footprint "TestPoint:TestPoint_Bridge_Pitch2.0mm_Drill0.7mm"
(layer "F.Cu")
(uuid "5680b68d-7137-4930-9dd5-5f4fafc5da8a")
(at 138.030698 95.032002)
(descr "wire loop as test point, pitch 2.0mm, hole diameter 0.7mm, wire diameter 0.5mm")
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(property ki_fp_filters "Pin* Test*")
(path "/b198df71-7d13-4632-9ab4-7f217c917f8e")
(sheetname "Root")
(sheetfile "unconnected-netnames.kicad_sch")
(attr through_hole)
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(pad "1" thru_hole circle
(at 0 0)
(size 1.4 1.4)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(net 2 "unconnected-(TP1-Pad1)_0")
(pinfunction "1")
(pintype "passive+no_connect")
(uuid "891be13e-e841-49df-9fe9-aa0803a01c48")
)
(pad "1" thru_hole circle
(at 2 0)
(size 1.4 1.4)
(drill 0.7)
(layers "*.Cu" "*.Mask")
(remove_unused_layers no)
(net 1 "unconnected-(TP1-Pad1)")
(pinfunction "1")
(pintype "passive+no_connect")
(uuid "7f73b514-d3e4-4e9b-aa32-6a472854c04b")
)
(model "${KICAD6_3DMODEL_DIR}/TestPoint.3dshapes/TestPoint_Bridge_Pitch2.0mm_Drill0.7mm.wrl"
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(gr_rect
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(fill none)
(layer "Edge.Cuts")
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)
(gr_text "There should be no schematic parity errors\nhere because NC pads share a common \nprefix with the test point"
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(layer "F.Fab")
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