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#!/bin/bash
# Interrupts Connected System - This project uses interrupts to test
# communication between multiple parallella boards
#=====================================================================
# June 2016
#
#
# Designed in the Parallel Programming Laboratory,
# The Faculty of Electrical Engineering,
# Technion Instittute of Technology.
#
# Student (author) : Aviv Burshtein
# Instructor : Oz Shmueli
# Academic Supervisor : Prof. Tsahi Birk
# http://psl.eelabs.technion.ac.il/
#
#=======================================================================
# File name : edit_hdf.bash
# Function : sets EPIPHANY_HDF file to match location in the cluster
# Usage : sudo ./edit_hdf [master/slave/restore] [number of slave boards/ slave board number/ - ]
#
#
if [ "$#" -ne 2 ]&&[ "$#" -ne 1 ]; then
echo "
use : sudo ./edit_hdf.sh [master] [number of slaves: 1-4]
or: ./edit_hdf.sh [slave] [slave_number: 1-4]
"
exit 1
fi
if [ "$1" == "master" ]; then
echo "Setting up master HDF"
case $2 in
1)
echo "// Platform description for the
// Parallella/1GB/E16G3
PLATFORM_VERSION PARALLELLA1601
ESYS_REGS_BASE 0x70000000
NUM_CHIPS 2
CHIP E16G301
CHIP_ROW 32
CHIP_COL 8
CHIP E16G301
CHIP_ROW 36
CHIP_COL 8
NUM_EXT_MEMS 1
EMEM ext-DRAM
EMEM_BASE_ADDRESS 0x3e000000
EMEM_EPI_BASE 0x8e000000
EMEM_SIZE 0x02000000
EMEM_TYPE RDWR
" > /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf
echo ""
echo ""
echo "hdf file is now :"
cat /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf;;
2)
echo "// Platform description for the
// Parallella/1GB/E16G3
PLATFORM_VERSION PARALLELLA1601
ESYS_REGS_BASE 0x70000000
NUM_CHIPS 3
CHIP E16G301
CHIP_ROW 32
CHIP_COL 8
CHIP E16G301
CHIP_ROW 36
CHIP_COL 8
CHIP E16G301
CHIP_ROW 40
CHIP_COL 8
NUM_EXT_MEMS 1
EMEM ext-DRAM
EMEM_BASE_ADDRESS 0x3e000000
EMEM_EPI_BASE 0x8e000000
EMEM_SIZE 0x02000000
EMEM_TYPE RDWR
" > /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf
echo ""
echo ""
echo "hdf file is now :"
cat /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf;;
3)
echo "// Platform description for the
// Parallella/1GB/E16G3
PLATFORM_VERSION PARALLELLA1601
ESYS_REGS_BASE 0x70000000
NUM_CHIPS 4
CHIP E16G301
CHIP_ROW 32
CHIP_COL 8
CHIP E16G301
CHIP_ROW 36
CHIP_COL 8
CHIP E16G301
CHIP_ROW 40
CHIP_COL 8
CHIP E16G301
CHIP_ROW 44
CHIP_COL 8
NUM_EXT_MEMS 1
EMEM ext-DRAM
EMEM_BASE_ADDRESS 0x3e000000
EMEM_EPI_BASE 0x8e000000
EMEM_SIZE 0x02000000
EMEM_TYPE RDWR
" > /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf
echo ""
echo ""
echo "hdf file is now :"
cat /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf;;
4)
echo "// Platform description for the
// Parallella/1GB/E16G3
PLATFORM_VERSION PARALLELLA1601
ESYS_REGS_BASE 0x70000000
NUM_CHIPS 5
CHIP E16G301
CHIP_ROW 32
CHIP_COL 8
CHIP E16G301
CHIP_ROW 36
CHIP_COL 8
CHIP E16G301
CHIP_ROW 40
CHIP_COL 8
CHIP E16G301
CHIP_ROW 44
CHIP_COL 8
CHIP E16G301
CHIP_ROW 48
CHIP_COL 8
NUM_EXT_MEMS 1
EMEM ext-DRAM
EMEM_BASE_ADDRESS 0x3e000000
EMEM_EPI_BASE 0x8e000000
EMEM_SIZE 0x02000000
EMEM_TYPE RDWR
" > /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf
echo ""
echo ""
echo "hdf file is now :"
cat /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf;;
*)
echo "Number of slaves not supported :-(";;
esac
elif [ "$1" == "slave" ]; then
echo "Setting up slave HDF"
case $2 in
1)
echo "// Platform description for the
// Parallella/1GB/E16G3
PLATFORM_VERSION PARALLELLA1601
ESYS_REGS_BASE 0x70000000
NUM_CHIPS 1
CHIP E16G301
CHIP_ROW 36
CHIP_COL 8
NUM_EXT_MEMS 1
EMEM ext-DRAM
EMEM_BASE_ADDRESS 0x3e000000
EMEM_EPI_BASE 0x8e000000
EMEM_SIZE 0x02000000
EMEM_TYPE RDWR
" > /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf
echo ""
echo ""
echo "hdf file is now :"
cat /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf;;
2)
echo "// Platform description for the
// Parallella/1GB/E16G3
PLATFORM_VERSION PARALLELLA1601
ESYS_REGS_BASE 0x70000000
NUM_CHIPS 1
CHIP E16G301
CHIP_ROW 40
CHIP_COL 8
NUM_EXT_MEMS 1
EMEM ext-DRAM
EMEM_BASE_ADDRESS 0x3e000000
EMEM_EPI_BASE 0x8e000000
EMEM_SIZE 0x02000000
EMEM_TYPE RDWR
" > /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf
echo ""
echo ""
echo "hdf file is now :"
cat /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf;;
3)
echo "// Platform description for the
// Parallella/1GB/E16G3
PLATFORM_VERSION PARALLELLA1601
ESYS_REGS_BASE 0x70000000
NUM_CHIPS 1
CHIP E16G301
CHIP_ROW 44
CHIP_COL 8
NUM_EXT_MEMS 1
EMEM ext-DRAM
EMEM_BASE_ADDRESS 0x3e000000
EMEM_EPI_BASE 0x8e000000
EMEM_SIZE 0x02000000
EMEM_TYPE RDWR
" > /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf
echo ""
echo ""
echo "hdf file is now :"
cat /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf;;
4)
echo "// Platform description for the
// Parallella/1GB/E16G3
PLATFORM_VERSION PARALLELLA1601
ESYS_REGS_BASE 0x70000000
NUM_CHIPS 1
CHIP E16G301
CHIP_ROW 48
CHIP_COL 8
NUM_EXT_MEMS 1
EMEM ext-DRAM
EMEM_BASE_ADDRESS 0x3e000000
EMEM_EPI_BASE 0x8e000000
EMEM_SIZE 0x02000000
EMEM_TYPE RDWR
" > /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf
echo ""
echo ""
echo "hdf file is now :"
cat /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf;;
*)
echo "Number of slaves not supported :-(";;
esac
elif [ "$1" == "restore" ]; then
echo "Restoring hdf to default..."
echo "// Platform description for the
// Parallella/1GB/E16G3
PLATFORM_VERSION PARALLELLA1601
ESYS_REGS_BASE 0x70000000
NUM_CHIPS 1
CHIP E16G301
CHIP_ROW 32
CHIP_COL 8
NUM_EXT_MEMS 1
EMEM ext-DRAM
EMEM_BASE_ADDRESS 0x3e000000
EMEM_EPI_BASE 0x8e000000
EMEM_SIZE 0x02000000
EMEM_TYPE RDWR
" > /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf
echo ""
echo ""
echo "hdf file is now :"
cat /opt/adapteva/esdk/bsps/parallella_E16G3_1GB/parallella_E16G3_1GB.hdf
else
echo "First input arguments not matched :-("
fi
exit 1

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#!/bin/bash
set -e
rm -f ./Debug/*
ESDK=${EPIPHANY_HOME}
ELIBS=${ESDK}/tools/host/lib
EINCS=${ESDK}/tools/host/include
ELDF=${ESDK}/bsps/current/fast.ldf
SRC_LIB=./src/
DEBUG_LIB=./Debug/
CROSS_PREFIX=
case $(uname -p) in
arm*)
# Use native arm compiler (no cross prefix)
CROSS_PREFIX=
;;
*)
# Use cross compiler
CROSS_PREFIX="arm-linux-gnueabihf-"
;;
esac
mkdir -p ./Debug
# Build HOST side application
${CROSS_PREFIX} gcc ${SRC_LIB}int-test.c ${SRC_LIB}my_h.c -o ./Debug/int-test.elf -I ${EINCS} -L ${ELIBS} -le-hal -le-loader
# Build DEVICE side program
e-gcc -O0 -T ${ELDF} ${SRC_LIB}e-int-test.master.c -o ${DEBUG_LIB}e-int-test.master.elf -le-lib
# Convert ebinary to SREC file
e-objcopy --srec-forceS3 --output-target srec ${DEBUG_LIB}e-int-test.master.elf ${DEBUG_LIB}e-int-test.master.srec

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#!/bin/bash
cd Debug
set -e
ESDK=${EPIPHANY_HOME}
ELIBS=${ESDK}/tools/host/lib:${LD_LIBRARY_PATH}
EHDF=${EPIPHANY_HDF}
sudo -E LD_LIBRARY_PATH=${ELIBS} EPIPHANY_HDF=${EHDF} ./int-test.elf

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/* Copyright (C) 2012 Adapteva, Inc.
Interrupts Connected System - This project uses interrupts to test
communication between multiple parallella boards
=====================================================================
June 2016
Designed in the Parallel Programming Laboratory,
The Faculty of Electrical Engineering,
Technion Instittute of Technology.
Student (author) : Aviv Burshtein
Instructor : Oz Shmueli
Academic Supervisor : Prof. Tsahi Birk
http://psl.eelabs.technion.ac.il/
=======================================================================
File name : e-int-test.master.c
Function : Epiphany side of master board. Waits for timer interrupt, sends messasges to all boards, gets message interrupt, and writes to (0,0) mailbox
Usage : ../run.sh
Code is based on system interrupts code by Yaniv Sapir <yaniv@adapteva.com>
========================================================================
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program, see the file COPYING. If not, see
<http://www.gnu.org/licenses/>.
*/
#include "e_lib.h"
#define Fhz (600e6) // Clock frequency (Hz)
#define Td (2) // Delay time (sec)
#define Delay (Td * Fhz)
#define TIMER0_VECTOR 0x0000000c // address of TIMER0 entry in IVT
#define B_OPCODE 0x000000e8 // OpCode of the B<*> instruction
#define maxcorenum 40
#define BASE_ROW 32
#define MB_size 40
void SW_EXCEPTION_isr(int signum);
void E_MEM_FAULT_isr(int signum);
void E_TIMER0_INT_isr(int signum);
void E_TIMER1_INT_isr(int signum);
void E_MESSAGE_INT_isr(int signum);
void E_DMA0_INT_isr(int signum);
void E_DMA1_INT_isr(int signum);
void E_USER_INT_isr(int signum);
unsigned name_irq[8] = {E_SW_EXCEPTION, E_MEM_FAULT, E_TIMER0_INT, E_TIMER1_INT, E_MESSAGE_INT, E_DMA0_INT, E_DMA1_INT, E_USER_INT};//@where are these from?
char event [8][20];
char volatile mailbox[maxcorenum][MB_size];//@why volatile?
// Define macro for indirect interrupt dispathcer method.
// Undef for the direct and faster, but more explicit, method.
int main(void)
{
strcpy (event[0], "E_SW_EXCEPTION");
strcpy (event[1], "E_MEM_FAULT");
strcpy (event[2], "E_TIMER0_INT");
strcpy (event[3], "E_TIMER1_INT");
strcpy (event[4], "E_MESSAGE_INT");
strcpy (event[5], "E_DMA0_INT");
strcpy (event[6], "E_DMA1_INT");
strcpy (event[7], "E_USER_INT");
e_irq_attach(name_irq[0],SW_EXCEPTION_isr);//@defines handlers for each type of interrupt
e_irq_attach(name_irq[1],E_MEM_FAULT_isr);
e_irq_attach(name_irq[2],E_TIMER0_INT_isr);
e_irq_attach(name_irq[3],E_TIMER1_INT_isr);
e_irq_attach(name_irq[4],E_MESSAGE_INT_isr);
e_irq_attach(name_irq[5],E_DMA0_INT_isr);
e_irq_attach(name_irq[6],E_DMA1_INT_isr);
e_irq_attach(name_irq[7],E_USER_INT_isr);
// Enable the TIMER0 interrupt
e_ctimer_start(E_CTIMER_0, E_CTIMER_OFF);
e_irq_mask(name_irq[0], E_FALSE);
e_irq_mask(name_irq[1], E_FALSE);
e_irq_mask(name_irq[2], E_FALSE);
e_irq_mask(name_irq[3], E_FALSE);
e_irq_mask(name_irq[4], E_FALSE);
e_irq_mask(name_irq[5], E_FALSE);
e_irq_mask(name_irq[6], E_FALSE);
e_irq_mask(name_irq[7], E_FALSE);
e_irq_global_mask(E_FALSE);
// Start the timer, counting for ~1 sec, and wait for
// it to finish.
e_ctimer_set(E_CTIMER_0, Delay);
e_ctimer_start(E_CTIMER_0, E_CTIMER_CLK);
while (e_ctimer_get(E_CTIMER_0));
return 0;
}
void __attribute__((interrupt)) SW_EXCEPTION_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[0]);
return;
}
void __attribute__((interrupt)) E_MEM_FAULT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[1]);
return;
}
void __attribute__((interrupt)) E_TIMER0_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
char* p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[2]);
if (i == 0)
{
e_irq_set(0, 1, E_MESSAGE_INT);
e_irq_set(0, 2, E_MESSAGE_INT);
e_irq_set(0, 3, E_MESSAGE_INT);
e_irq_set(1, 0, E_MESSAGE_INT);
e_irq_set(1, 1, E_MESSAGE_INT);
e_irq_set(1, 2, E_MESSAGE_INT);
e_irq_set(1, 3, E_MESSAGE_INT);
e_irq_set(2, 0, E_MESSAGE_INT);
e_irq_set(2, 1, E_MESSAGE_INT);
e_irq_set(2, 2, E_MESSAGE_INT);
e_irq_set(2, 3, E_MESSAGE_INT);
e_irq_set(3, 0, E_MESSAGE_INT);
e_irq_set(3, 1, E_MESSAGE_INT);
e_irq_set(3, 2, E_MESSAGE_INT);
e_irq_set(3, 3, E_MESSAGE_INT);
e_irq_set(4, 1, E_MESSAGE_INT);
e_irq_set(4, 2, E_MESSAGE_INT);
e_irq_set(4, 3, E_MESSAGE_INT);
e_irq_set(4, 0, E_MESSAGE_INT);
e_irq_set(5, 1, E_MESSAGE_INT);
e_irq_set(5, 2, E_MESSAGE_INT);
e_irq_set(5, 3, E_MESSAGE_INT);
e_irq_set(5, 0, E_MESSAGE_INT);
e_irq_set(6, 1, E_MESSAGE_INT);
e_irq_set(6, 2, E_MESSAGE_INT);
e_irq_set(6, 3, E_MESSAGE_INT);
e_irq_set(7, 0, E_MESSAGE_INT);
e_irq_set(7, 1, E_MESSAGE_INT);
e_irq_set(7, 2, E_MESSAGE_INT);
e_irq_set(7, 3, E_MESSAGE_INT);
}
return;
}
void __attribute__((interrupt))E_TIMER1_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[3]);
return;
}
void __attribute__((interrupt)) E_MESSAGE_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
char* p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[4]);
return;
}
void __attribute__((interrupt)) E_DMA0_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[5]);
return;
}
void __attribute__((interrupt)) E_DMA1_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[6]);
return;
}
void __attribute__((interrupt)) E_USER_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[7]);
return;
}

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/* Copyright (C) 2012 Adapteva, Inc.
Interrupts Connected System - This project uses interrupts to test
communication between multiple parallella boards
=====================================================================
June 2016
Designed in the Parallel Programming Laboratory,
The Faculty of Electrical Engineering,
Technion Instittute of Technology.
Student (author) : Aviv Burshtein
Instructor : Oz Shmueli
Academic Supervisor : Prof. Tsahi Birk
http://psl.eelabs.technion.ac.il/
=======================================================================
File name :int-test.master.c
Function : ARM side of master board. loads code to local Epiphany and reads mailboxs.
Usage : ../run.sh
Code is based on system interrupts code by Yaniv Sapir <yaniv@adapteva.com>
Note that upon any change in code the mailbox location changes and the value in line 146 must be adjusted.
To find the correct value (after initial compilation) : e-objdump -x ./Debug/e-int-test.master.elf | grep mailbox
========================================================================
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program, see the file COPYING. If not, see
<http://www.gnu.org/licenses/>.
*/
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <e-hal.h>
#include "my_h.h"
void print_mbox(e_epiphany_t *dev, e_mem_t *emem, char *msg);
#define _BufOffset (0x01000000)
#define maxcorenum 32
unsigned corenum=32;
char M[maxcorenum][40];
unsigned IVT[10];
int main(int argc, char *argv[])
{
int i,j;
unsigned row, col, coreid;
unsigned di, ci, go, go_all;
e_platform_t platform;
e_epiphany_t dev;
e_mem_t emem;
// Initialize progress state in mailbox
for(i=0;i<corenum;i++)
for(j=0;j<40;j++)
M[i][j] ='\0';
// initialize system, read platform params from
// default HDF. Then, reset the platform.
e_init(NULL);
fprintf(stderr, "finished init\n");
e_reset_connected_system();
fprintf(stderr, "finished reset\n");
e_get_platform_info(&platform);
fprintf(stderr, "platform info: num_chips =0x%x ,emems = 0x%x\n",platform.num_chips,platform.num_emems);
fprintf(stderr, "hdf_ platform info: core (0,0) id =%x\n ", (0 + platform.row) * 64 + 0 + platform.col );
fprintf(stderr, "platform info: rows =0x%x ,cols = 0x%x\n",platform.rows,platform.cols );
corenum=platform.rows*platform.cols;
// Open the first and second cores for master and slave programs, resp.
fprintf(stderr, "starting e_open\n");
usleep(1e6);
e_open(&dev, 0, 0, platform.rows, platform.cols);
fprintf(stderr, "finished e_open\n");
// Allocate the ext. mem. mailbox
e_alloc(&emem, _BufOffset, sizeof(M));
// Load programs on cores.
fprintf(stderr, "starting e_load\n");
e_load_group("e-int-test.master.srec", &dev, 0, 0, platform.rows, platform.cols, E_FALSE);
fprintf(stderr, "starting e_load\n");
//e_load("e-int-test.slave.srec", &dev, 0, 1, E_FALSE);
// clear mailbox.
e_write(&emem, 0, 0, (off_t) (0x0000), (void *) &(M[0]), sizeof(M));
usleep(500e3);
// Print mbox status.
print_mbox(&dev, &emem, "1. Clearing mbox:");
// start the master program
e_start_group(&dev);
printf("started :\n");
usleep(2e6);
print_mbox(&dev, &emem, "2. started:");
//usleep(4e6);
usleep(3e6);
print_mbox(&dev, &emem, "3. started:");
// At this point, the mailbox should contain all of the progress
// indicators, and look like the following:
//
// 0x808 0x809 0x22222222 0x33333333 0x44444444
//
// If there is a "0xdeadbeef" state in one of the slots, it means
// that something went wrong.
// Finalize
e_close(&dev);
e_free(&emem);
e_finalize();
return 0;
}
void print_mbox(e_epiphany_t *dev, e_mem_t *emem, char *msg)
{
//e_read(emem, 0, 0, (off_t) (0x0000), (void *) &(M[0]), sizeof(M));
printf("\n%s\n" ,msg);
e_read(dev, 0, 0, (off_t) (0x00002114), (void *) &(M[0]), sizeof(M));
int i,j=0;
for(i=0;i<corenum;i++)
{
printf("\nmsgs from(%d) :\n",i);
for(j=0;j<40;j++) printf("%c",M[i][j]) ;
}
return;
}

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/* Copyright (C) 2012 Adapteva, Inc.
Interrupts Connected System - This project uses interrupts to test
communication between multiple parallella boards
=====================================================================
June 2016
Designed in the Parallel Programming Laboratory,
The Faculty of Electrical Engineering,
Technion Instittute of Technology.
Student (author) : Aviv Burshtein
Instructor : Oz Shmueli
Academic Supervisor : Prof. Tsahi Birk
http://psl.eelabs.technion.ac.il/
=======================================================================
File name :my_h.h
Function : Header file for my_h.c. Helper functions for setting up a parallella cluster.
Note the function reset_connected_systems().
========================================================================
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program, see the file COPYING. If not, see
<http://www.gnu.org/licenses/>.
*/
#ifndef __MY_H_H__
#define __MY_H_H__
#include<e_hal.h>
/*
#ifdef __cplusplus
extern "C"
typedef enum {
E_FALSE = false,
E_TRUE = true,
} e_bool_t;
#else
typedef enum {
E_FALSE = 0,
E_TRUE = 1,
} e_bool_t;
#endif
//from e-hal-data-local.h
typedef enum {
E_SYNC = 0,
E_USER_INT = 9,
} e_signal_t;
typedef enum {
E_RD = 1,
E_WR = 2,
E_RDWR = 3,
} e_memtype_t;
typedef enum {
E_NULL = 0,
E_EPI_PLATFORM = 1,
E_EPI_CHIP = 2,
E_EPI_GROUP = 3,
E_EPI_CORE = 4,
E_EXT_MEM = 5,
E_MAPPING = 6,
E_SHARED_MEM = 7
} e_objtype_t;
typedef enum {
E_E16G301 = 0,
E_E64G401 = 1,
} e_chiptype_t;
typedef enum {
E_GENERIC = 0,
E_EMEK301 = 1,
E_EMEK401 = 2,
E_ZEDBOARD1601 = 3,
E_ZEDBOARD6401 = 4,
E_PARALLELLA1601 = 5,
E_PARALLELLA6401 = 6,
} e_platformtype_t;
typedef struct {
e_objtype_t objtype; // object type identifier
off_t phy_base; // physical global base address of memory region
off_t page_base; // physical base address of memory page
off_t page_offset; // offset of memory region base to memory page base
size_t map_size; // size of mapped region
void *mapped_base; // for mmap
void *base; // application space base address of memory region
} e_mmap_t;
typedef struct {
e_objtype_t objtype; // object type identifier
unsigned int id; // core ID
unsigned int row; // core absolute row number
unsigned int col; // core absolute col number
e_mmap_t mems; // core's SRAM data structure
e_mmap_t regs; // core's e-regs data structure
} e_core_t;
// Platform data structures
typedef struct {
e_objtype_t objtype; // object type identifier
e_chiptype_t type; // Epiphany chip part number
char version[32]; // version number of Epiphany chip
unsigned int arch; // architecture generation
unsigned int base_coreid; // chip base core ID
unsigned int row; // chip absolute row number
unsigned int col; // chip absolute col number
unsigned int rows; // number of rows in chip
unsigned int cols; // number of cols in chip
unsigned int num_cores; // number of cores in chip
unsigned int sram_base; // base offset of core SRAM
unsigned int sram_size; // size of core SRAM
unsigned int regs_base; // base offset of core registers
unsigned int regs_size; // size of core registers segment
off_t ioregs_n; // base address of north IO register
off_t ioregs_e; // base address of east IO register
off_t ioregs_s; // base address of south IO register
off_t ioregs_w; // base address of west IO register
} e_chip_t;
typedef struct {
e_objtype_t objtype; // object type identifier
off_t phy_base; // physical global base address of external memory segment as seen by host
off_t ephy_base; // physical global base address of external memory segment as seen by devic
size_t size; // size of eDRAM allocated buffer for host side
e_memtype_t type; // type of memory RD/WR/RW
} e_memseg_t;
typedef struct {
e_objtype_t objtype; // object type identifier
e_platformtype_t type; // platform part number
char version[32]; // version number of platform
unsigned int hal_ver; // version number of the E-HAL
int initialized; // platform initialized?
unsigned int regs_base; // base address of platform registers
int num_chips; // number of Epiphany chips in platform
e_chip_t *chip; // array of Epiphany chip objects
unsigned int row; // platform absolute minimum row number
unsigned int col; // platform absolute minimum col number
unsigned int rows; // number of rows in platform
unsigned int cols; // number of cols in platform
int num_emems; // number of external memory segments in platform
e_memseg_t *emem; // array of external memory segments
} e_platform_t;
// Definitions for device workgroup communication object
typedef unsigned int e_coreid_t;
#define SIZEOF_IVT (0x28)
typedef struct {
e_objtype_t objtype; // 0x28
e_chiptype_t chiptype; // 0x2c
e_coreid_t group_id; // 0x30
unsigned group_row; // 0x34
unsigned group_col; // 0x38
unsigned group_rows; // 0x3c
unsigned group_cols; // 0x40
unsigned core_row; // 0x44
unsigned core_col; // 0x48
unsigned alignment_padding; // 0x4c
} e_group_config_t;
typedef struct {
e_objtype_t objtype; // 0x50
unsigned base; // 0x54
} e_emem_config_t;
// fromepiphany-hal-api.h
typedef enum {
H_D0 = 0,
H_D1 = 1,
H_D2 = 2,
H_D3 = 3,
H_D4 = 4,
} e_hal_diag_t;
typedef enum {
E_OK = 0,
E_ERR = -1,
E_WARN = -2,
} e_return_stat_t;
// eCore General Purpose Registers
typedef enum {
E_REG_R0 = 0xf0000,
E_REG_R1 = 0xf0004,
E_REG_R2 = 0xf0008,
E_REG_R3 = 0xf000c,
E_REG_R4 = 0xf0010,
E_REG_R5 = 0xf0014,
E_REG_R6 = 0xf0018,
E_REG_R7 = 0xf001c,
E_REG_R8 = 0xf0020,
E_REG_R9 = 0xf0024,
E_REG_R10 = 0xf0028,
E_REG_R11 = 0xf002c,
E_REG_R12 = 0xf0030,
E_REG_R13 = 0xf0034,
E_REG_R14 = 0xf0038,
E_REG_R15 = 0xf003c,
E_REG_R16 = 0xf0040,
E_REG_R17 = 0xf0044,
E_REG_R18 = 0xf0048,
E_REG_R19 = 0xf004c,
E_REG_R20 = 0xf0050,
E_REG_R21 = 0xf0054,
E_REG_R22 = 0xf0058,
E_REG_R23 = 0xf005c,
E_REG_R24 = 0xf0060,
E_REG_R25 = 0xf0064,
E_REG_R26 = 0xf0068,
E_REG_R27 = 0xf006c,
E_REG_R28 = 0xf0070,
E_REG_R29 = 0xf0074,
E_REG_R30 = 0xf0078,
E_REG_R31 = 0xf007c,
E_REG_R32 = 0xf0080,
E_REG_R33 = 0xf0084,
E_REG_R34 = 0xf0088,
E_REG_R35 = 0xf008c,
E_REG_R36 = 0xf0090,
E_REG_R37 = 0xf0094,
E_REG_R38 = 0xf0098,
E_REG_R39 = 0xf009c,
E_REG_R40 = 0xf00a0,
E_REG_R41 = 0xf00a4,
E_REG_R42 = 0xf00a8,
E_REG_R43 = 0xf00ac,
E_REG_R44 = 0xf00b0,
E_REG_R45 = 0xf00b4,
E_REG_R46 = 0xf00b8,
E_REG_R47 = 0xf00bc,
E_REG_R48 = 0xf00c0,
E_REG_R49 = 0xf00c4,
E_REG_R50 = 0xf00c8,
E_REG_R51 = 0xf00cc,
E_REG_R52 = 0xf00d0,
E_REG_R53 = 0xf00d4,
E_REG_R54 = 0xf00d8,
E_REG_R55 = 0xf00dc,
E_REG_R56 = 0xf00e0,
E_REG_R57 = 0xf00e4,
E_REG_R58 = 0xf00e8,
E_REG_R59 = 0xf00ec,
E_REG_R60 = 0xf00f0,
E_REG_R61 = 0xf00f4,
E_REG_R62 = 0xf00f8,
E_REG_R63 = 0xf00fc
} e_gp_reg_id_t;
// eCore Special Registers
typedef enum {
// Control registers
E_REG_CONFIG = 0xf0400,
E_REG_STATUS = 0xf0404,
E_REG_PC = 0xf0408,
E_REG_DEBUGSTATUS = 0xf040c,
E_REG_LC = 0xf0414,
E_REG_LS = 0xf0418,
E_REG_LE = 0xf041c,
E_REG_IRET = 0xf0420,
E_REG_IMASK = 0xf0424,
E_REG_ILAT = 0xf0428,
E_REG_ILATST = 0xf042C,
E_REG_ILATCL = 0xf0430,
E_REG_IPEND = 0xf0434,
E_REG_CTIMER0 = 0xf0438,
E_REG_CTIMER1 = 0xf043C,
E_REG_FSTATUS = 0xf0440,
E_REG_DEBUGCMD = 0xf0448,
// DMA Registers
E_REG_DMA0CONFIG = 0xf0500,
E_REG_DMA0STRIDE = 0xf0504,
E_REG_DMA0COUNT = 0xf0508,
E_REG_DMA0SRCADDR = 0xf050c,
E_REG_DMA0DSTADDR = 0xf0510,
E_REG_DMA0AUTODMA0 = 0xf0514,
E_REG_DMA0AUTODMA1 = 0xf0518,
E_REG_DMA0STATUS = 0xf051c,
E_REG_DMA1CONFIG = 0xf0520,
E_REG_DMA1STRIDE = 0xf0524,
E_REG_DMA1COUNT = 0xf0528,
E_REG_DMA1SRCADDR = 0xf052c,
E_REG_DMA1DSTADDR = 0xf0530,
E_REG_DMA1AUTODMA0 = 0xf0534,
E_REG_DMA1AUTODMA1 = 0xf0538,
E_REG_DMA1STATUS = 0xf053c,
// Memory Protection Registers
E_REG_MEMSTATUS = 0xf0604,
E_REG_MEMPROTECT = 0xf0608,
// Node Registers
E_REG_MESHCONFIG = 0xf0700,
E_REG_COREID = 0xf0704,
E_REG_MULTICAST = 0xf0708,
E_REG_RESETCORE = 0xf070c,
E_REG_CMESHROUTE = 0xf0710,
E_REG_XMESHROUTE = 0xf0714,
E_REG_RMESHROUTE = 0xf0718
} e_core_reg_id_t;
// Chip registers
typedef enum {
E_REG_LINKCFG = 0xf0300,
E_REG_LINKTXCFG = 0xf0304,
E_REG_LINKRXCFG = 0xf0308,
E_REG_GPIOCFG = 0xf030c,
E_REG_FLAGCFG = 0xf0318,
E_REG_SYNC = 0xf031c,
E_REG_HALT = 0xf0320,
E_REG_RESET = 0xf0324,
E_REG_LINKDEBUG = 0xf0328
} e_chip_regs_t;
// Epiphany system registers
typedef enum {
E_SYS_RESET = 0x0040,
E_SYS_CFGTX = 0x0044,
E_SYS_CFGRX = 0x0048,
E_SYS_CFGCLK = 0x004c,
E_SYS_COREID = 0x0050,
E_SYS_VERSION = 0x0054,
E_SYS_GPIOIN = 0x0058,
E_SYS_GPIOOUT = 0x005c
} e_sys_reg_id_t;
typedef union {
unsigned int reg;
struct {
unsigned int enable:1;
unsigned int mmu:1;
unsigned int mode:2; // 0=Normal, 1=GPIO
unsigned int ctrlmode:4;
unsigned int clkmode:4; // 0=Full speed, 1=1/2 speed
unsigned int resvd:20;
} fields;
} e_syscfg_tx_t;
typedef union {
unsigned int reg;
struct {
unsigned int enable:1;
unsigned int mmu:1;
unsigned int path:2; // 0=Normal, 1=GPIO, 2=Loopback
unsigned int monitor:1;
unsigned int resvd:27;
} fields;
} e_syscfg_rx_t;
typedef union {
unsigned int reg;
struct {
unsigned int divider:4; // 0=off, 1=F/64 ... 7=F/1
unsigned int pll:4; // TBD
unsigned int resvd:24;
} fields;
} e_syscfg_clk_t;
typedef union {
unsigned int reg;
struct {
unsigned int col:6;
unsigned int row:6;
unsigned int resvd:20;
} fields;
} e_syscfg_coreid_t;
typedef union {
unsigned int reg;
struct {
unsigned int revision:8;
unsigned int type:8;
unsigned int platform:8;
unsigned int generation:8;
} fields;
} e_syscfg_version_t;
// The following is for E_SYS_GPIOIN and E_SYS_GPIOOUT
typedef union {
unsigned int reg;
struct {
unsigned int data:8;
unsigned int frame:1;
unsigned int wait_rd:1;
unsigned int wait_wr:1;
unsigned int resvd:21;
} fields;
} e_syscfg_gpio_t;
// Core group data structures
typedef struct {
e_objtype_t objtype; // object type identifier
e_chiptype_t type; // Epiphany chip part number
unsigned int num_cores; // number of cores group
unsigned int base_coreid; // group base core ID
unsigned int row; // group absolute row number
unsigned int col; // group absolute col number
unsigned int rows; // number of rows group
unsigned int cols; // number of cols group
e_core_t **core; // e-cores data structures array
int memfd; // for mmap
} e_epiphany_t;
typedef struct {
e_objtype_t objtype; // object type identifier
off_t phy_base; // physical global base address of external memory buffer as seen by host side
off_t page_base; // physical base address of memory page
off_t page_offset; // offset of memory region base to memory page base
size_t map_size; // size of eDRAM allocated buffer for host side
off_t ephy_base; // physical global base address of external memory buffer as seen by device side
size_t emap_size; // size of eDRAM allocated buffer for device side
void *mapped_base; // for mmap
void *base; // application (virtual) space base address of external memory buffer
int memfd; // for mmap
} e_mem_t;
#define ALIGN(x) __attribute__ ((aligned (x)))
#define MAX_SHM_REGIONS 64
#pragma pack(push, 1)
// Shared memory segment
typedef struct ALIGN(8) e_shmseg {
void *addr; // Virtual address
char name[256]; // Region name
size_t size; // Region size in bytes
void *paddr; // Physical Address accessible from Epiphany cores
off_t offset; // Offset from shm base address
} e_shmseg_t;
typedef struct ALIGN(8) e_shmseg_pvt {
e_shmseg_t shm_seg; // The shared memory segment
unsigned refcnt; // host app reference count
unsigned valid; // 1 if the region is in use, 0 otherwise
} e_shmseg_pvt_t;
typedef struct ALIGN(8) e_shmtable {
unsigned int magic;
unsigned int initialized;
e_shmseg_pvt_t regions[MAX_SHM_REGIONS];
unsigned long paddr_epi; // Physical address of the shm region as seen by epiphany
unsigned long paddr_cpu; // Physical address of the shm region as seen by the host cpu
} e_shmtable_t;
#pragma pack(pop)
*/
//api declarations:
int e_reset_connected_system(void);
#endif // __MY_H_H__

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B_OPCODE e-int-test.master.c 27
Delay e-int-test.master.c 24
E_DMA0_INT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_DMA0_INT_isr(int/
E_DMA1_INT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_DMA1_INT_isr(int/
E_MEM_FAULT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_MEM_FAULT_isr(in/
E_MESSAGE_INT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_MESSAGE_INT_isr(/
E_TIMER0_INT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_TIMER0_INT_isr(i/
E_TIMER1_INT_isr e-int-test.master.c /^void __attribute__((interrupt))E_TIMER1_INT_isr(in/
E_USER_INT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_USER_INT_isr(int/
Fhz e-int-test.master.c 22
IVT int-test.c 32
M int-test.c 31
Me-int-test.master e-int-test.master.c /^int main(void)$/
Mint-test int-test.c /^int main(int argc, char *argv[])$/
SW_EXCEPTION_isr e-int-test.master.c /^void __attribute__((interrupt)) SW_EXCEPTION_isr(i/
TIMER0_VECTOR e-int-test.master.c 26
Td e-int-test.master.c 23
_BufOffset int-test.c 28
corenum int-test.c 30
event e-int-test.master.c 41
mailbox e-int-test.master.c 43
maxcorenum e-int-test.master.c 28
maxcorenum int-test.c 29
name_irq e-int-test.master.c 40
print_mbox int-test.c /^void print_mbox(e_epiphany_t *dev, e_mem_t *emem, /

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#!/bin/bash
set -e
rm -f ./Debug/*
ESDK=${EPIPHANY_HOME}
ELIBS=${ESDK}/tools/host/lib
EINCS=${ESDK}/tools/host/include
ELDF=${ESDK}/bsps/current/fast.ldf
SRC_LIB=./src/
DEBUG_LIB=./Debug/
CROSS_PREFIX=
case $(uname -p) in
arm*)
# Use native arm compiler (no cross prefix)
CROSS_PREFIX=
;;
*)
# Use cross compiler
CROSS_PREFIX="arm-linux-gnueabihf-"
;;
esac
mkdir -p ./Debug
# Build HOST side application
#${CROSS_PREFIX} gcc ${SRC_LIB}my_h.c -o ./Debug/my_h.elf -I ${EINCS} -L ${ELIBS} -le-hal -le-loader
${CROSS_PREFIX} gcc ${SRC_LIB}int-test.c ${SRC_LIB}my_h.c -o ./Debug/int-test.elf -I ${EINCS} -L ${ELIBS} -le-hal -le-loader
# Build DEVICE side program
e-gcc -O0 -T ${ELDF} ${SRC_LIB}e-int-test.master.c -o ${DEBUG_LIB}e-int-test.master.elf -le-lib
# Convert ebinary to SREC file
e-objcopy --srec-forceS3 --output-target srec ${DEBUG_LIB}e-int-test.master.elf ${DEBUG_LIB}e-int-test.master.srec

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#!/bin/bash
cd Debug
set -e
ESDK=${EPIPHANY_HOME}
ELIBS=${ESDK}/tools/host/lib:${LD_LIBRARY_PATH}
EHDF=${EPIPHANY_HDF}
sudo -E LD_LIBRARY_PATH=${ELIBS} EPIPHANY_HDF=${EHDF} ./int-test.elf

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/* Copyright (C) 2012 Adapteva, Inc.
Interrupts Connected System - This project uses interrupts to test
communication between multiple parallella boards
=====================================================================
June 2016
Designed in the Parallel Programming Laboratory,
The Faculty of Electrical Engineering,
Technion Instittute of Technology.
Student (author) : Aviv Burshtein
Instructor : Oz Shmueli
Academic Supervisor : Prof. Tsahi Birk
http://psl.eelabs.technion.ac.il/
=======================================================================
File name : e-int-test.master.c
Function : Epiphany side of slave board. Each core gets message interrupt, and writes to (0,0) mailbox
Usage : ../run.sh
Code is based on system interrupts code by Yaniv Sapir <yaniv@adapteva.com>
========================================================================
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program, see the file COPYING. If not, see
<http://www.gnu.org/licenses/>.
*/
#include "e_lib.h"
#define Fhz (600e6) // Clock frequency (Hz)
#define Td (2) // Delay time (sec)
#define Delay (Td * Fhz)
#define TIMER0_VECTOR 0x0000000c // address of TIMER0 entry in IVT
#define B_OPCODE 0x000000e8 // OpCode of the B<*> instruction
#define maxcorenum 32
#define BASE_ROW 32
#define MB_size 40
void SW_EXCEPTION_isr(int signum);
void E_MEM_FAULT_isr(int signum);
void E_TIMER0_INT_isr(int signum);
void E_TIMER1_INT_isr(int signum);
void E_MESSAGE_INT_isr(int signum);
void E_DMA0_INT_isr(int signum);
void E_DMA1_INT_isr(int signum);
void E_USER_INT_isr(int signum);
unsigned name_irq[8] = {E_SW_EXCEPTION, E_MEM_FAULT, E_TIMER0_INT, E_TIMER1_INT, E_MESSAGE_INT, E_DMA0_INT, E_DMA1_INT, E_USER_INT};//@where are these from?
char event [8][20];
char volatile mailbox[maxcorenum][MB_size];//@why volatile?
// Define macro for indirect interrupt dispathcer method.
// Undef for the direct and faster, but more explicit, method.
int main(void)
{
strcpy (event[0], "E_SW_EXCEPTION");
strcpy (event[1], "E_MEM_FAULT");
strcpy (event[2], "E_TIMER0_INT");
strcpy (event[3], "E_TIMER1_INT");
strcpy (event[4], "E_MESSAGE_INT");
strcpy (event[5], "E_DMA0_INT");
strcpy (event[6], "E_DMA1_INT");
strcpy (event[7], "E_USER_INT");
e_irq_attach(name_irq[0],SW_EXCEPTION_isr);//@defines handlers for each type of interrupt
e_irq_attach(name_irq[1],E_MEM_FAULT_isr);
e_irq_attach(name_irq[2],E_TIMER0_INT_isr);
e_irq_attach(name_irq[3],E_TIMER1_INT_isr);
e_irq_attach(name_irq[4],E_MESSAGE_INT_isr);
e_irq_attach(name_irq[5],E_DMA0_INT_isr);
e_irq_attach(name_irq[6],E_DMA1_INT_isr);
e_irq_attach(name_irq[7],E_USER_INT_isr);
// Enable the TIMER0 interrupt
e_ctimer_start(E_CTIMER_0, E_CTIMER_OFF);
e_irq_mask(name_irq[0], E_FALSE);
e_irq_mask(name_irq[1], E_FALSE);
e_irq_mask(name_irq[2], E_FALSE);
e_irq_mask(name_irq[3], E_FALSE);
e_irq_mask(name_irq[4], E_FALSE);
e_irq_mask(name_irq[5], E_FALSE);
e_irq_mask(name_irq[6], E_FALSE);
e_irq_mask(name_irq[7], E_FALSE);
e_irq_global_mask(E_FALSE);
// Start the timer, counting for ~1 sec, and wait for
// it to finish.
e_ctimer_set(E_CTIMER_0, Delay);
e_ctimer_start(E_CTIMER_0, E_CTIMER_CLK);
while (e_ctimer_get(E_CTIMER_0));
return 0;
}
void __attribute__((interrupt)) SW_EXCEPTION_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[0]);
return;
}
void __attribute__((interrupt)) E_MEM_FAULT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[1]);
return;
}
void __attribute__((interrupt)) E_TIMER0_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
char* p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[2]);
if (i == 0)
{
e_irq_set(0, 1, E_MESSAGE_INT);
e_irq_set(0, 2, E_MESSAGE_INT);
e_irq_set(0, 3, E_MESSAGE_INT);
e_irq_set(1, 0, E_MESSAGE_INT);
e_irq_set(1, 1, E_MESSAGE_INT);
e_irq_set(1, 2, E_MESSAGE_INT);
e_irq_set(1, 3, E_MESSAGE_INT);
e_irq_set(2, 0, E_MESSAGE_INT);
e_irq_set(2, 1, E_MESSAGE_INT);
e_irq_set(2, 2, E_MESSAGE_INT);
e_irq_set(2, 3, E_MESSAGE_INT);
e_irq_set(3, 0, E_MESSAGE_INT);
e_irq_set(3, 1, E_MESSAGE_INT);
e_irq_set(3, 2, E_MESSAGE_INT);
e_irq_set(3, 3, E_MESSAGE_INT);
e_irq_set(4, 1, E_MESSAGE_INT);
e_irq_set(4, 2, E_MESSAGE_INT);
e_irq_set(4, 3, E_MESSAGE_INT);
e_irq_set(4, 0, E_MESSAGE_INT);
e_irq_set(5, 1, E_MESSAGE_INT);
e_irq_set(5, 2, E_MESSAGE_INT);
e_irq_set(5, 3, E_MESSAGE_INT);
e_irq_set(5, 0, E_MESSAGE_INT);
e_irq_set(6, 1, E_MESSAGE_INT);
e_irq_set(6, 2, E_MESSAGE_INT);
e_irq_set(6, 3, E_MESSAGE_INT);
e_irq_set(7, 0, E_MESSAGE_INT);
e_irq_set(7, 1, E_MESSAGE_INT);
e_irq_set(7, 2, E_MESSAGE_INT);
e_irq_set(7, 3, E_MESSAGE_INT);
}
return;
}
void __attribute__((interrupt))E_TIMER1_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[3]);
return;
}
void __attribute__((interrupt)) E_MESSAGE_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
char* p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[4]);
return;
}
void __attribute__((interrupt)) E_DMA0_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[5]);
return;
}
void __attribute__((interrupt)) E_DMA1_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[6]);
return;
}
void __attribute__((interrupt)) E_USER_INT_isr(int signum)
{
int x=e_get_coreid()%64 -8;
int y=e_get_coreid()/64 -BASE_ROW;
int i=y*4+x;
unsigned*p=NULL;
p=e_get_global_address(0,0,mailbox)+i*MB_size;
sprintf(p,"%x says:%s\n",e_get_coreid(),event[7]);
return;
}

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/* Copyright (C) 2012 Adapteva, Inc.
Interrupts Connected System - This project uses interrupts to test
communication between multiple parallella boards
=====================================================================
June 2016
Designed in the Parallel Programming Laboratory,
The Faculty of Electrical Engineering,
Technion Instittute of Technology.
Student (author) : Aviv Burshtein
Instructor : Oz Shmueli
Academic Supervisor : Prof. Tsahi Birk
http://psl.eelabs.technion.ac.il/
=======================================================================
File name :int-test.master.c
Function : ARM side of slave board. loads code to local Epiphany and waits for the master board.
Usage : ../run.sh
Code is based on system interrupts code by Yaniv Sapir <yaniv@adapteva.com>
========================================================================
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program, see the file COPYING. If not, see
<http://www.gnu.org/licenses/>.
*/
#include <stdlib.h>
#include <stdio.h>
#include <unistd.h>
#include <e-hal.h>
#include "my_h.h"
void print_mbox(e_epiphany_t *dev, e_mem_t *emem, char *msg);
#define _BufOffset (0x01000000)
#define maxcorenum 32
unsigned corenum=32;
char M[maxcorenum][40];
unsigned IVT[10];
int main(int argc, char *argv[])
{
int i,j;
unsigned row, col, coreid;
unsigned di, ci, go, go_all;
e_platform_t platform;
e_epiphany_t dev;
e_mem_t emem;
// Initialize progress state in mailbox
for(i=0;i<corenum;i++)
for(j=0;j<40;j++)
M[i][j] ='\0';
// initialize system, read platform params from
// default HDF. Then, reset the platform.
e_init(NULL);
e_reset_connected_system();
e_get_platform_info(&platform);
fprintf(stderr, "platform info: num_chips =0x%x ,emems = 0x%x\n",platform.num_chips,platform.num_emems);
fprintf(stderr, "hdf_ platform info: core (0,0) id =%x\n ", (0 + platform.row) * 64 + 0 + platform.col );
fprintf(stderr, "platform info: rows =0x%x ,cols = 0x%x\n",platform.rows,platform.cols );
corenum=platform.rows*platform.cols;
//Open the first and second cores for master and slave programs, resp.
e_open(&dev, 0, 0, platform.rows, platform.cols);
// Allocate the ext. mem. mailbox
////e_alloc(&emem, _BufOffset, sizeof(M));
// Load programs on cores.
printf("loading :\n");
e_load_group("e-int-test.master.srec", &dev, 0, 0, platform.rows, platform.cols, E_FALSE);
printf("loaded :rows = %d, cols = %d\n", platform.rows, platform.cols );
//e_load("e-int-test.slave.srec", &dev, 0, 1, E_FALSE);
// clear mailbox.
///////e_write(&emem, 0, 0, (off_t) (0x0000), (void *) &(M[0]), sizeof(M));
// usleep(5e6);
// e_close(&dev);
// e_free(&emem);
// e_finalize();
// e_init(NULL);
// e_reset_connected_system();
// Print mbox status.
// print_mbox(&dev, &emem, "1. Clearing mbox:");
// start the master program
////e_start_group(&dev);
////printf("started :\n");
////usleep(4e6);
//print_mbox(&dev, &emem, "2. started:");
//usleep(4e6);
//print_mbox(&dev, &emem, "3. started:");
// At this point, the mailbox should contain all of the progress
// indicators, and look like the following:
//
// 0x808 0x809 0x22222222 0x33333333 0x44444444
//
// If there is a "0xdeadbeef" state in one of the slots, it means
// that something went wrong.
// Finalize
fprintf(stderr, "Waiting for my Master!\n\n");
usleep(30e6);
fprintf(stderr, "Done waiting for my master board! Im not his slave!\n");
e_close(&dev);
e_free(&emem);
e_finalize();
return 0;
}
void print_mbox(e_epiphany_t *dev, e_mem_t *emem, char *msg)
{
//e_read(emem, 0, 0, (off_t) (0x0000), (void *) &(M[0]), sizeof(M));
printf("\n%s\n" ,msg);
e_read(dev, 0, 0, (off_t) (0x00002124), (void *) &(M[0]), sizeof(M));
int i,j=0;
for(i=0;i<corenum;i++)
{
printf("\nmsgs from(%d) :\n",i);
for(j=0;j<40;j++) printf("%c",M[i][j]) ;
}
return;
}

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/* Copyright (C) 2012 Adapteva, Inc.
Interrupts Connected System - This project uses interrupts to test
communication between multiple parallella boards
=====================================================================
June 2016
Designed in the Parallel Programming Laboratory,
The Faculty of Electrical Engineering,
Technion Instittute of Technology.
Student (author) : Aviv Burshtein
Instructor : Oz Shmueli
Academic Supervisor : Prof. Tsahi Birk
http://psl.eelabs.technion.ac.il/
=======================================================================
File name :my_h.h
Function : Header file for my_h.c. Helper functions for setting up a parallella cluster.
Note the function reset_connected_systems().
========================================================================
This program is free software: you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation, either version 3 of the License, or
(at your option) any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License
along with this program, see the file COPYING. If not, see
<http://www.gnu.org/licenses/>.
*/
#ifndef __MY_H_H__
#define __MY_H_H__
#include<e_hal.h>
/*
#ifdef __cplusplus
extern "C"
typedef enum {
E_FALSE = false,
E_TRUE = true,
} e_bool_t;
#else
typedef enum {
E_FALSE = 0,
E_TRUE = 1,
} e_bool_t;
#endif
//from e-hal-data-local.h
typedef enum {
E_SYNC = 0,
E_USER_INT = 9,
} e_signal_t;
typedef enum {
E_RD = 1,
E_WR = 2,
E_RDWR = 3,
} e_memtype_t;
typedef enum {
E_NULL = 0,
E_EPI_PLATFORM = 1,
E_EPI_CHIP = 2,
E_EPI_GROUP = 3,
E_EPI_CORE = 4,
E_EXT_MEM = 5,
E_MAPPING = 6,
E_SHARED_MEM = 7
} e_objtype_t;
typedef enum {
E_E16G301 = 0,
E_E64G401 = 1,
} e_chiptype_t;
typedef enum {
E_GENERIC = 0,
E_EMEK301 = 1,
E_EMEK401 = 2,
E_ZEDBOARD1601 = 3,
E_ZEDBOARD6401 = 4,
E_PARALLELLA1601 = 5,
E_PARALLELLA6401 = 6,
} e_platformtype_t;
typedef struct {
e_objtype_t objtype; // object type identifier
off_t phy_base; // physical global base address of memory region
off_t page_base; // physical base address of memory page
off_t page_offset; // offset of memory region base to memory page base
size_t map_size; // size of mapped region
void *mapped_base; // for mmap
void *base; // application space base address of memory region
} e_mmap_t;
typedef struct {
e_objtype_t objtype; // object type identifier
unsigned int id; // core ID
unsigned int row; // core absolute row number
unsigned int col; // core absolute col number
e_mmap_t mems; // core's SRAM data structure
e_mmap_t regs; // core's e-regs data structure
} e_core_t;
// Platform data structures
typedef struct {
e_objtype_t objtype; // object type identifier
e_chiptype_t type; // Epiphany chip part number
char version[32]; // version number of Epiphany chip
unsigned int arch; // architecture generation
unsigned int base_coreid; // chip base core ID
unsigned int row; // chip absolute row number
unsigned int col; // chip absolute col number
unsigned int rows; // number of rows in chip
unsigned int cols; // number of cols in chip
unsigned int num_cores; // number of cores in chip
unsigned int sram_base; // base offset of core SRAM
unsigned int sram_size; // size of core SRAM
unsigned int regs_base; // base offset of core registers
unsigned int regs_size; // size of core registers segment
off_t ioregs_n; // base address of north IO register
off_t ioregs_e; // base address of east IO register
off_t ioregs_s; // base address of south IO register
off_t ioregs_w; // base address of west IO register
} e_chip_t;
typedef struct {
e_objtype_t objtype; // object type identifier
off_t phy_base; // physical global base address of external memory segment as seen by host
off_t ephy_base; // physical global base address of external memory segment as seen by devic
size_t size; // size of eDRAM allocated buffer for host side
e_memtype_t type; // type of memory RD/WR/RW
} e_memseg_t;
typedef struct {
e_objtype_t objtype; // object type identifier
e_platformtype_t type; // platform part number
char version[32]; // version number of platform
unsigned int hal_ver; // version number of the E-HAL
int initialized; // platform initialized?
unsigned int regs_base; // base address of platform registers
int num_chips; // number of Epiphany chips in platform
e_chip_t *chip; // array of Epiphany chip objects
unsigned int row; // platform absolute minimum row number
unsigned int col; // platform absolute minimum col number
unsigned int rows; // number of rows in platform
unsigned int cols; // number of cols in platform
int num_emems; // number of external memory segments in platform
e_memseg_t *emem; // array of external memory segments
} e_platform_t;
// Definitions for device workgroup communication object
typedef unsigned int e_coreid_t;
#define SIZEOF_IVT (0x28)
typedef struct {
e_objtype_t objtype; // 0x28
e_chiptype_t chiptype; // 0x2c
e_coreid_t group_id; // 0x30
unsigned group_row; // 0x34
unsigned group_col; // 0x38
unsigned group_rows; // 0x3c
unsigned group_cols; // 0x40
unsigned core_row; // 0x44
unsigned core_col; // 0x48
unsigned alignment_padding; // 0x4c
} e_group_config_t;
typedef struct {
e_objtype_t objtype; // 0x50
unsigned base; // 0x54
} e_emem_config_t;
// fromepiphany-hal-api.h
typedef enum {
H_D0 = 0,
H_D1 = 1,
H_D2 = 2,
H_D3 = 3,
H_D4 = 4,
} e_hal_diag_t;
typedef enum {
E_OK = 0,
E_ERR = -1,
E_WARN = -2,
} e_return_stat_t;
// eCore General Purpose Registers
typedef enum {
E_REG_R0 = 0xf0000,
E_REG_R1 = 0xf0004,
E_REG_R2 = 0xf0008,
E_REG_R3 = 0xf000c,
E_REG_R4 = 0xf0010,
E_REG_R5 = 0xf0014,
E_REG_R6 = 0xf0018,
E_REG_R7 = 0xf001c,
E_REG_R8 = 0xf0020,
E_REG_R9 = 0xf0024,
E_REG_R10 = 0xf0028,
E_REG_R11 = 0xf002c,
E_REG_R12 = 0xf0030,
E_REG_R13 = 0xf0034,
E_REG_R14 = 0xf0038,
E_REG_R15 = 0xf003c,
E_REG_R16 = 0xf0040,
E_REG_R17 = 0xf0044,
E_REG_R18 = 0xf0048,
E_REG_R19 = 0xf004c,
E_REG_R20 = 0xf0050,
E_REG_R21 = 0xf0054,
E_REG_R22 = 0xf0058,
E_REG_R23 = 0xf005c,
E_REG_R24 = 0xf0060,
E_REG_R25 = 0xf0064,
E_REG_R26 = 0xf0068,
E_REG_R27 = 0xf006c,
E_REG_R28 = 0xf0070,
E_REG_R29 = 0xf0074,
E_REG_R30 = 0xf0078,
E_REG_R31 = 0xf007c,
E_REG_R32 = 0xf0080,
E_REG_R33 = 0xf0084,
E_REG_R34 = 0xf0088,
E_REG_R35 = 0xf008c,
E_REG_R36 = 0xf0090,
E_REG_R37 = 0xf0094,
E_REG_R38 = 0xf0098,
E_REG_R39 = 0xf009c,
E_REG_R40 = 0xf00a0,
E_REG_R41 = 0xf00a4,
E_REG_R42 = 0xf00a8,
E_REG_R43 = 0xf00ac,
E_REG_R44 = 0xf00b0,
E_REG_R45 = 0xf00b4,
E_REG_R46 = 0xf00b8,
E_REG_R47 = 0xf00bc,
E_REG_R48 = 0xf00c0,
E_REG_R49 = 0xf00c4,
E_REG_R50 = 0xf00c8,
E_REG_R51 = 0xf00cc,
E_REG_R52 = 0xf00d0,
E_REG_R53 = 0xf00d4,
E_REG_R54 = 0xf00d8,
E_REG_R55 = 0xf00dc,
E_REG_R56 = 0xf00e0,
E_REG_R57 = 0xf00e4,
E_REG_R58 = 0xf00e8,
E_REG_R59 = 0xf00ec,
E_REG_R60 = 0xf00f0,
E_REG_R61 = 0xf00f4,
E_REG_R62 = 0xf00f8,
E_REG_R63 = 0xf00fc
} e_gp_reg_id_t;
// eCore Special Registers
typedef enum {
// Control registers
E_REG_CONFIG = 0xf0400,
E_REG_STATUS = 0xf0404,
E_REG_PC = 0xf0408,
E_REG_DEBUGSTATUS = 0xf040c,
E_REG_LC = 0xf0414,
E_REG_LS = 0xf0418,
E_REG_LE = 0xf041c,
E_REG_IRET = 0xf0420,
E_REG_IMASK = 0xf0424,
E_REG_ILAT = 0xf0428,
E_REG_ILATST = 0xf042C,
E_REG_ILATCL = 0xf0430,
E_REG_IPEND = 0xf0434,
E_REG_CTIMER0 = 0xf0438,
E_REG_CTIMER1 = 0xf043C,
E_REG_FSTATUS = 0xf0440,
E_REG_DEBUGCMD = 0xf0448,
// DMA Registers
E_REG_DMA0CONFIG = 0xf0500,
E_REG_DMA0STRIDE = 0xf0504,
E_REG_DMA0COUNT = 0xf0508,
E_REG_DMA0SRCADDR = 0xf050c,
E_REG_DMA0DSTADDR = 0xf0510,
E_REG_DMA0AUTODMA0 = 0xf0514,
E_REG_DMA0AUTODMA1 = 0xf0518,
E_REG_DMA0STATUS = 0xf051c,
E_REG_DMA1CONFIG = 0xf0520,
E_REG_DMA1STRIDE = 0xf0524,
E_REG_DMA1COUNT = 0xf0528,
E_REG_DMA1SRCADDR = 0xf052c,
E_REG_DMA1DSTADDR = 0xf0530,
E_REG_DMA1AUTODMA0 = 0xf0534,
E_REG_DMA1AUTODMA1 = 0xf0538,
E_REG_DMA1STATUS = 0xf053c,
// Memory Protection Registers
E_REG_MEMSTATUS = 0xf0604,
E_REG_MEMPROTECT = 0xf0608,
// Node Registers
E_REG_MESHCONFIG = 0xf0700,
E_REG_COREID = 0xf0704,
E_REG_MULTICAST = 0xf0708,
E_REG_RESETCORE = 0xf070c,
E_REG_CMESHROUTE = 0xf0710,
E_REG_XMESHROUTE = 0xf0714,
E_REG_RMESHROUTE = 0xf0718
} e_core_reg_id_t;
// Chip registers
typedef enum {
E_REG_LINKCFG = 0xf0300,
E_REG_LINKTXCFG = 0xf0304,
E_REG_LINKRXCFG = 0xf0308,
E_REG_GPIOCFG = 0xf030c,
E_REG_FLAGCFG = 0xf0318,
E_REG_SYNC = 0xf031c,
E_REG_HALT = 0xf0320,
E_REG_RESET = 0xf0324,
E_REG_LINKDEBUG = 0xf0328
} e_chip_regs_t;
// Epiphany system registers
typedef enum {
E_SYS_RESET = 0x0040,
E_SYS_CFGTX = 0x0044,
E_SYS_CFGRX = 0x0048,
E_SYS_CFGCLK = 0x004c,
E_SYS_COREID = 0x0050,
E_SYS_VERSION = 0x0054,
E_SYS_GPIOIN = 0x0058,
E_SYS_GPIOOUT = 0x005c
} e_sys_reg_id_t;
typedef union {
unsigned int reg;
struct {
unsigned int enable:1;
unsigned int mmu:1;
unsigned int mode:2; // 0=Normal, 1=GPIO
unsigned int ctrlmode:4;
unsigned int clkmode:4; // 0=Full speed, 1=1/2 speed
unsigned int resvd:20;
} fields;
} e_syscfg_tx_t;
typedef union {
unsigned int reg;
struct {
unsigned int enable:1;
unsigned int mmu:1;
unsigned int path:2; // 0=Normal, 1=GPIO, 2=Loopback
unsigned int monitor:1;
unsigned int resvd:27;
} fields;
} e_syscfg_rx_t;
typedef union {
unsigned int reg;
struct {
unsigned int divider:4; // 0=off, 1=F/64 ... 7=F/1
unsigned int pll:4; // TBD
unsigned int resvd:24;
} fields;
} e_syscfg_clk_t;
typedef union {
unsigned int reg;
struct {
unsigned int col:6;
unsigned int row:6;
unsigned int resvd:20;
} fields;
} e_syscfg_coreid_t;
typedef union {
unsigned int reg;
struct {
unsigned int revision:8;
unsigned int type:8;
unsigned int platform:8;
unsigned int generation:8;
} fields;
} e_syscfg_version_t;
// The following is for E_SYS_GPIOIN and E_SYS_GPIOOUT
typedef union {
unsigned int reg;
struct {
unsigned int data:8;
unsigned int frame:1;
unsigned int wait_rd:1;
unsigned int wait_wr:1;
unsigned int resvd:21;
} fields;
} e_syscfg_gpio_t;
// Core group data structures
typedef struct {
e_objtype_t objtype; // object type identifier
e_chiptype_t type; // Epiphany chip part number
unsigned int num_cores; // number of cores group
unsigned int base_coreid; // group base core ID
unsigned int row; // group absolute row number
unsigned int col; // group absolute col number
unsigned int rows; // number of rows group
unsigned int cols; // number of cols group
e_core_t **core; // e-cores data structures array
int memfd; // for mmap
} e_epiphany_t;
typedef struct {
e_objtype_t objtype; // object type identifier
off_t phy_base; // physical global base address of external memory buffer as seen by host side
off_t page_base; // physical base address of memory page
off_t page_offset; // offset of memory region base to memory page base
size_t map_size; // size of eDRAM allocated buffer for host side
off_t ephy_base; // physical global base address of external memory buffer as seen by device side
size_t emap_size; // size of eDRAM allocated buffer for device side
void *mapped_base; // for mmap
void *base; // application (virtual) space base address of external memory buffer
int memfd; // for mmap
} e_mem_t;
#define ALIGN(x) __attribute__ ((aligned (x)))
#define MAX_SHM_REGIONS 64
#pragma pack(push, 1)
// Shared memory segment
typedef struct ALIGN(8) e_shmseg {
void *addr; // Virtual address
char name[256]; // Region name
size_t size; // Region size in bytes
void *paddr; // Physical Address accessible from Epiphany cores
off_t offset; // Offset from shm base address
} e_shmseg_t;
typedef struct ALIGN(8) e_shmseg_pvt {
e_shmseg_t shm_seg; // The shared memory segment
unsigned refcnt; // host app reference count
unsigned valid; // 1 if the region is in use, 0 otherwise
} e_shmseg_pvt_t;
typedef struct ALIGN(8) e_shmtable {
unsigned int magic;
unsigned int initialized;
e_shmseg_pvt_t regions[MAX_SHM_REGIONS];
unsigned long paddr_epi; // Physical address of the shm region as seen by epiphany
unsigned long paddr_cpu; // Physical address of the shm region as seen by the host cpu
} e_shmtable_t;
#pragma pack(pop)
*/
//api declarations:
int e_reset_connected_system(void);
#endif // __MY_H_H__

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interrupts_connected/slave/src/tags Normal file
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B_OPCODE e-int-test.master.c 27
Delay e-int-test.master.c 24
E_DMA0_INT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_DMA0_INT_isr(int/
E_DMA1_INT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_DMA1_INT_isr(int/
E_MEM_FAULT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_MEM_FAULT_isr(in/
E_MESSAGE_INT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_MESSAGE_INT_isr(/
E_TIMER0_INT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_TIMER0_INT_isr(i/
E_TIMER1_INT_isr e-int-test.master.c /^void __attribute__((interrupt))E_TIMER1_INT_isr(in/
E_USER_INT_isr e-int-test.master.c /^void __attribute__((interrupt)) E_USER_INT_isr(int/
Fhz e-int-test.master.c 22
IVT int-test.c 32
M int-test.c 31
Me-int-test.master e-int-test.master.c /^int main(void)$/
Mint-test int-test.c /^int main(int argc, char *argv[])$/
SW_EXCEPTION_isr e-int-test.master.c /^void __attribute__((interrupt)) SW_EXCEPTION_isr(i/
TIMER0_VECTOR e-int-test.master.c 26
Td e-int-test.master.c 23
_BufOffset int-test.c 28
corenum int-test.c 30
event e-int-test.master.c 41
mailbox e-int-test.master.c 43
maxcorenum e-int-test.master.c 28
maxcorenum int-test.c 29
name_irq e-int-test.master.c 40
print_mbox int-test.c /^void print_mbox(e_epiphany_t *dev, e_mem_t *emem, /