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Reorg, cleanup

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This commit is contained in:
Andreas Olofsson 2015-04-09 09:02:20 -04:00
parent 31e2ee7be5
commit b3525e3fee
133 changed files with 114015 additions and 1 deletions
fpga
externals
fpgahdl_xilinx
ip/altera
README
old
bitstreams
README.mdelink2_e16_headless_gpiose_7010.bit.binelink2_e16_headless_gpiose_7020.bit.binparallella_e16_hdmi_7010.bit.binparallella_e16_hdmi_7020.bit.binparallella_e16_headless_7010.bit.binparallella_e16_headless_7020.bit.binparallella_e64_hdmi_7020.bit.binparallella_e64_headless_7020.bit.bin
edk-vivado/parallella_7020_headless
.gitignoreprocessing_system7_0.xci
edk
parallella_7010_hdmi
.gitignore
data
ps7_system_prj.xml
system.mhssystem.xmp
parallella_7010_headless
.gitignore
data
ps7_system_prj.xml
system.mhssystem.xmp
parallella_7020_hdmi
.gitignore
data
ps7_system_prj.xml
system.mhssystem.xmp
parallella_7020_headless
.gitignore
data
ps7_system_prj.xml
system.mhssystem.xmp
externals
README.mdfpgahdl_xilinx.scoget_fpgahdl_xilinx
vivado
archives
parallella_7020_headless.xpr.zip
obsolete
elink2new_testbench
.gitignoreconfig.wcfgelink2_tb_behav.wcfg
elink2new_testbench.sim
.gitignoreraddrraddr_ecfgwaddrwaddr_ecfgwdatawdata_ecfg
elink2new_testbench.srcs/sources_1/bd/elink_testbench
elink_testbench.bdelink_testbench.bxml
ip
elink_testbench_axi_bram_ctrl_0_0
elink_testbench_axi_bram_ctrl_0_0.upgrade_logelink_testbench_axi_bram_ctrl_0_0.xcielink_testbench_axi_bram_ctrl_0_0.xml
elink_testbench_axi_bram_ctrl_0_1
elink_testbench_axi_bram_ctrl_0_1.xcielink_testbench_axi_bram_ctrl_0_1.xml
elink_testbench_axi_bram_ctrl_2_2
elink_testbench_axi_bram_ctrl_2_2.xcielink_testbench_axi_bram_ctrl_2_2.xml
elink_testbench_axi_protocol_converter_0_0
elink_testbench_axi_protocol_converter_0_0.xcielink_testbench_axi_protocol_converter_0_0.xml
elink_testbench_axi_protocol_converter_0_1
elink_testbench_axi_protocol_converter_0_1.xcielink_testbench_axi_protocol_converter_0_1.xml
elink_testbench_axi_protocol_converter_0_2
elink_testbench_axi_protocol_converter_0_2.xcielink_testbench_axi_protocol_converter_0_2.xml
elink_testbench_axi_traffic_controller_0_0
elink_testbench_axi_traffic_controller_0_0.xcielink_testbench_axi_traffic_controller_0_0.xml
elink_testbench_axi_traffic_controller_0_1
elink_testbench_axi_traffic_controller_0_1.xcielink_testbench_axi_traffic_controller_0_1.xml
elink_testbench_axi_traffic_controller_1_0
elink_testbench_axi_traffic_controller_1_0.xcielink_testbench_axi_traffic_controller_1_0.xml
elink_testbench_blk_mem_gen_0_0
elink_testbench_blk_mem_gen_0_0.upgrade_logelink_testbench_blk_mem_gen_0_0.xcielink_testbench_blk_mem_gen_0_0.xml
elink_testbench_blk_mem_gen_0_1
elink_testbench_blk_mem_gen_0_1.xcielink_testbench_blk_mem_gen_0_1.xml
elink_testbench_eCfg_0_0
elink_testbench_eCfg_0_0.upgrade_logelink_testbench_eCfg_0_0.xcielink_testbench_eCfg_0_0.xml
elink_testbench_earb_0_0
elink_testbench_earb_0_0.upgrade_logelink_testbench_earb_0_0.xcielink_testbench_earb_0_0.xml
elink_testbench_ecfg_split_0_0
elink_testbench_ecfg_split_0_0.upgrade_logelink_testbench_ecfg_split_0_0.xcielink_testbench_ecfg_split_0_0.xml
elink_testbench_eclock_0_2
elink_testbench_eclock_0_2.upgrade_logelink_testbench_eclock_0_2.xcielink_testbench_eclock_0_2.xml
elink_testbench_edistrib_0_0
elink_testbench_edistrib_0_0.upgrade_logelink_testbench_edistrib_0_0.xcielink_testbench_edistrib_0_0.xml
elink_testbench_eio_rx_0_2
elink_testbench_eio_rx_0_2.upgrade_logelink_testbench_eio_rx_0_2.xcielink_testbench_eio_rx_0_2.xml
elink_testbench_eio_tx_0_2
elink_testbench_eio_tx_0_2.upgrade_logelink_testbench_eio_tx_0_2.xcielink_testbench_eio_tx_0_2.xml
elink_testbench_elink_gold_0_0
elink_testbench_elink_gold_0_0.upgrade_logelink_testbench_elink_gold_0_0.xcielink_testbench_elink_gold_0_0.xml
elink_testbench_emaxi_0_0
elink_testbench_emaxi_0_0.upgrade_logelink_testbench_emaxi_0_0.xcielink_testbench_emaxi_0_0.xml
elink_testbench_emesh_split_0_0
elink_testbench_emesh_split_0_0.upgrade_logelink_testbench_emesh_split_0_0.xcielink_testbench_emesh_split_0_0.xml
elink_testbench_eproto_rx_0_0
elink_testbench_eproto_rx_0_0.upgrade_logelink_testbench_eproto_rx_0_0.xcielink_testbench_eproto_rx_0_0.xml
elink_testbench_eproto_tx_0_0
elink_testbench_eproto_tx_0_0.upgrade_logelink_testbench_eproto_tx_0_0.xcielink_testbench_eproto_tx_0_0.xml
elink_testbench_esaxi_0_0
elink_testbench_esaxi_0_0.upgrade_logelink_testbench_esaxi_0_0.xcielink_testbench_esaxi_0_0.xml
elink_testbench_fifo_103x16_0_0
elink_testbench_fifo_103x16_0_0.xcielink_testbench_fifo_103x16_0_0.xml
elink_testbench_fifo_103x16_0_1
elink_testbench_fifo_103x16_0_1.xcielink_testbench_fifo_103x16_0_1.xml
elink_testbench_fifo_103x32_0_0
elink_testbench_fifo_103x32_0_0.xcielink_testbench_fifo_103x32_0_0.xml
elink_testbench_fifo_103x32_0_1
elink_testbench_fifo_103x32_0_1.xcielink_testbench_fifo_103x32_0_1.xml
elink_testbench_fifo_103x32_0_2
elink_testbench_fifo_103x32_0_2.xcielink_testbench_fifo_103x32_0_2.xml
elink_testbench_fifo_generator_0_0
elink_testbench_fifo_generator_0_0.xcielink_testbench_fifo_generator_0_0.xml
ui
bd_583888d1.uibd_625c958a.uibd_f348d452.uibd_fb70713e.ui
elink2new_testbench.xprelink_tb_behav.wcfgnew_rx.wcfgserdestest.wcfg
parallella_7020_headless
.gitignoreREADME.mdcreate_project.shparallella_7020_headless.tclversion.v

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fpga/externals/fpgahdl_xilinx vendored

Submodule fpga/externals/fpgahdl_xilinx deleted from 9ba3ed9df6

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fpga/bitstreams/parallella_e16_hdmi_7010.bit.bin → fpga/old/bitstreams/parallella_e16_hdmi_7010.bit.bin
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fpga/edk-vivado/parallella_7020_headless/.gitignore → fpga/old/edk-vivado/parallella_7020_headless/.gitignore vendored
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fpga/edk/parallella_7010_hdmi/system.mhs → fpga/old/edk/parallella_7010_hdmi/system.mhs
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fpga/edk/parallella_7010_hdmi/system.xmp → fpga/old/edk/parallella_7010_hdmi/system.xmp
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fpga/edk/parallella_7010_headless/system.mhs → fpga/old/edk/parallella_7010_headless/system.mhs
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fpga/edk/parallella_7010_headless/system.xmp → fpga/old/edk/parallella_7010_headless/system.xmp
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