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  • f158afe257 Fixing typo Andreas Olofsson 2015-03-23 15:46:56 -0400
  • bc9a58b48b Merge remote-tracking branch 'origin/elink_redesign_fred' march23 Andreas Olofsson 2015-03-23 15:29:55 -0400
  • 862ce4485e Merge remote-tracking branch 'origin/elink_redesign' Andreas Olofsson 2015-03-23 15:24:38 -0400
  • 89a0a78cbf Adding the latest Vivado design archive for Parallella Andreas Olofsson 2015-03-21 10:14:13 -0400
  • 572e1f5bc2 Shortening names (reorg) Andreas Olofsson 2015-03-21 10:04:55 -0400
  • 7f9d1fc4c2 Reorg Andreas Olofsson 2015-03-21 10:01:08 -0400
  • 400b3e0d2b Merge pull request from Fred3/master Andreas Olofsson 2015-02-22 23:12:07 -0500
  • 97bd47e18b Porcupine Version 2. Fred Huettig 2015-02-19 01:07:24 -0500
  • 9dfa677aaf Merge branch 'master' of https://github.com/Parallella/parallella-hw Fred Huettig 2015-02-18 03:07:55 -0500
  • 22f0370088 Revert "Fixing port declarations (thanks Verilator!)" elink_redesign Fred Huettig 2015-01-28 14:15:13 -0500
  • ac3a5ffa54 Partial integration of new elink elink_redesign_fred Fred Huettig 2015-01-28 13:53:09 -0500
  • f5193374b7 Added XDC constraints files. Added REMAP function to non-MMU eDistrib. Fixed EMAXI operation when eLink is very busy. Added streaming support for eproto_rx. Fixed handling of bursts on ESAXI, added support for memcpy() unaligned reads. Added testbench code. Fred Huettig 2014-12-19 16:15:26 -0500
  • 7531044740 Fixing port declarations (thanks Verilator!) aolofsson 2014-12-15 16:39:28 -0500
  • dc7225fddd Fixed renaming bug in e_tx_ack signal. (thanks verilator) aolofsson 2014-12-15 15:28:33 -0500
  • 1b24a912b3 Wrong bus width (just cleanup..) aolofsson 2014-12-15 15:26:07 -0500
  • 5bc1fff358 Verilator inspired bug fixes -address width in elink -bus widths in ecfg -command file more generic aolofsson 2014-12-15 15:25:09 -0500
  • 14cbe0ebef Verious silly compilation fixes, nothing to see here.. aolofsson 2014-12-14 22:24:16 -0500
  • 1d66006464 Consolidating all axi interface in one directory Adding interface for axi lite slave, needs content aolofsson 2014-12-14 22:22:49 -0500
  • 3d31e6dea9 Adding stubs files for xilinx IP Goal is to create models for all of these aolofsson 2014-12-14 22:21:01 -0500
  • 65afbb89c0 Adding new elink top level file written in verilog. Compiles and runs (needs work) aolofsson 2014-12-14 22:19:02 -0500
  • cfcfc80593 Adding fofo environment for elink to check for broken signals. Too many stub modules to be practical..next need sim models aolofsson 2014-12-14 22:17:23 -0500
  • 082a1c57a1 Moving file to elink (makes more sense): Each directory should be a self contained "object" aolofsson 2014-12-14 17:41:07 -0500
  • 21b640003a Adding README file describing design structure of the elink aolofsson 2014-12-14 17:40:23 -0500
  • c1031421d3 An unverified clean top level elink design module aolofsson 2014-12-14 17:25:46 -0500
  • 8e0a6e1345 Adding new verilog modules for receiver and transmitter -moving away from Vivado block editor -creating a "clean" split between RX and TX aolofsson 2014-12-14 17:18:53 -0500
  • dd54ea4eeb Adding axi lite interface to be used by various registers aolofsson 2014-12-14 17:17:04 -0500
  • 3c6920571e Incremental renaming aolofsson 2014-12-14 09:14:25 -0500
  • f7c6155d54 Created a verilog wrapper for the elink transmitter (moving away from the Vivado block editor) aolofsson 2014-12-12 20:36:15 -0500
  • ffc2dda821 Changed module name for new structure aolofsson 2014-12-12 16:35:59 -0500
  • b1c6c0b651 Renamed file Converted all signals to lower case aolofsson 2014-12-12 16:34:52 -0500
  • a49875299e Removing old files not needed by new design aolofsson 2014-12-12 12:27:22 -0500
  • 9d466a6f1b Add register definition for ESYSDEBUG... aolofsson 2014-12-12 12:20:18 -0500
  • f4be5e7237 Adding a read only debug register for monitor important elink signals. Useful for debugging new hardware. aolofsson 2014-12-11 14:51:09 -0500
  • 24ae857f9d Minor fixes for implementation. Fred Huettig 2014-11-24 01:57:57 -0500
  • 4aed853348 eCfg: Renamed reset input to hw_reset, OR'd into ecfg_reset output. eCfg IP updated to match. Fred Huettig 2014-11-19 16:59:04 -0500
  • 8d34b3ca8c Added elink-gold -> elink2 test project. Fred Huettig 2014-11-19 14:56:33 -0500
  • 41b14f77f8 Merge branch 'elink_redesign' of https://github.com/Parallella/parallella-hw into elink_redesign Fred Huettig 2014-11-19 12:29:35 -0500
  • 635227356a New Vivado-friendly modules, testbench for elink gold-vs-new. Fred Huettig 2014-11-19 12:02:18 -0500
  • da805cf66f Deleting old files (moved to src) aolofsson 2014-11-06 15:41:28 -0500
  • e2267a3919 Cleaning up old files.. aolofsson 2014-11-06 15:40:40 -0500
  • ec4d87939f More file organization Adding some more utility functions aolofsson 2014-11-06 12:19:39 -0500
  • 840ccb59b5 A "complete" elink top level block with all new features added. Still need to work on the axi side. aolofsson 2014-11-06 12:18:16 -0500
  • be8b1cf19e Adding place holders for hard macros aolofsson 2014-11-06 12:17:56 -0500
  • 6cee5d6ddb Fixing interface as 20 bits, fits with Epiphany architecture. Very unlikely to EVER change, so hard coding. aolofsson 2014-11-06 12:17:09 -0500
  • 4842ed7b48 Basic interfaces..still need to add the axi signals and fill in the content aolofsson 2014-11-06 12:16:09 -0500
  • 2fffe9944c Adding readback indicator for slave axi mux aolofsson 2014-11-06 12:15:19 -0500
  • a045ce3fa5 Adding readback indicator for AXI slave mux aolofsson 2014-11-06 12:14:49 -0500
  • 09f15054b9 Create combined reset (hw+sw) Added data select output for axi_slave mux Signal cleanup (gpio_data) aolofsson 2014-11-06 11:52:38 -0500
  • 250a9e28ca Adding run.sh files for simulation aolofsson 2014-11-05 20:00:57 -0500
  • 728bba33b9 Changing to 20 bit address interface aolofsson 2014-11-05 19:59:15 -0500
  • ea73ffcf8f Changed to 20 bit addressing for clarity in FPGA aolofsson 2014-11-05 19:49:18 -0500
  • 83eef9749b Changed to 20 bit address width for clarity in FPGA block aolofsson 2014-11-05 19:37:25 -0500
  • f51207db6c Run script for embox aolofsson 2014-11-05 19:36:58 -0500
  • f72aa81f7d Reorganizing structure to be IP centric -Each directory contains one sub block -Each directory contains a dv/docs/hdl directory, self contained. -May need to add constraints directory as well at some point. -This is the right thing to do, make each block modular and self contained. aolofsson 2014-11-05 14:31:05 -0500
  • e6033c1a8e Lint fix (matching bit widths) aolofsson 2014-11-05 09:50:37 -0500
  • a3ea326e75 Lint fixes aolofsson 2014-11-05 09:47:56 -0500
  • 6a33cb836a Adding generic memory modules -insert tecnology specific macros insides (BRAM etc) aolofsson 2014-11-05 09:29:51 -0500
  • 460e6ff839 Ading a memory management unit for Epiphany -32 and 64 bit support -this is going to be very nice.... aolofsson 2014-11-05 09:29:02 -0500
  • 1fbb5460c2 Adding module for testing the monitor circuit aolofsson 2014-11-04 21:52:54 -0500
  • a96fe511ea Fixing various connection bugs based on dv unit testing.. aolofsson 2014-11-04 21:11:02 -0500
  • ee08afd112 Adding dv module for mailbox aolofsson 2014-11-04 21:10:38 -0500
  • 7263652794 Removing interrupt signal aolofsson 2014-11-04 17:15:32 -0500
  • ccc61378c8 Lots of stupid little bug fixes..too many to mention. -ecfg Block now verified with simple verilog unit test aolofsson 2014-11-04 17:10:28 -0500
  • 0a64e13895 Adding a simple dv unit test for configuration file aolofsson 2014-11-04 17:09:59 -0500
  • 546d0b5f92 Adding a register file config block -this block drivers the controls for the elink -(not verified) aolofsson 2014-11-03 16:45:59 -0500
  • 49b98d5781 Adding a monitor block for elink -tracks wait signals -tracks access signals (not verified) aolofsson 2014-11-03 16:32:45 -0500
  • eb7f245125 Adding generic axi memory interface -this would instantiate a bram controller interface (or other IP) aolofsson 2014-11-03 16:31:39 -0500
  • ce0c7bc49a Adding some memory wrappers (not yet tested) aolofsson 2014-11-03 12:54:44 -0500
  • 59a9e12252 Adding mailbox block -fifo full and empty output flags -can be polled for status -output can be connected to interrupt block of Zynq -intent is for one entry per core aolofsson 2014-11-03 10:13:35 -0500
  • edf973c0e0 First version of new elink register file Significantly expanded feature spec: -cclk power down/divider -gpio mod -loopback support -start of irq/mmu feature -traffic monitor aolofsson 2014-10-11 12:56:14 -0400
  • c721f127e6 Added missing write channel ready signal on m_axi aolofsson 2014-10-09 15:37:16 -0400
  • 173bc61d45 First version of new elink interface aolofsson 2014-10-07 18:02:32 -0400
  • a0a3f5be2e dummy change aolofsson 2014-10-07 13:07:27 -0400
  • ce97134bc0 Step clarification Andreas Olofsson 2014-09-02 09:16:24 -0400
  • 8491f34a77 And finally, add xdc files, don't import them. Fred Huettig 2014-07-29 16:14:44 -0400
  • fa33a17f5b Add create_project script, don't import PS files into project. Fred Huettig 2014-07-29 15:41:24 -0400
  • 4a77390147 Prevent tcl script from importing files, they should be referenced from the original locations. Fred Huettig 2014-07-29 15:10:35 -0400
  • 1239be823d Cleanup for Vivado project. Fred Huettig 2014-07-28 19:48:17 -0400
  • 86afb5906b Migrate to Vivado Fred Huettig 2014-07-28 15:56:23 -0400
  • 7a815f7e89 Updated flash images & readme instructions. Fred Huettig 2014-07-22 12:36:47 -0400
  • dfb0708be8 Added PDF schematic for those without KiCad. Fred Huettig 2014-06-24 03:27:05 -0400
  • 7f2bf2104c As released for fab., Rev. A. Fred Huettig 2014-06-20 20:48:04 -0400
  • a273d90451 Updated top-level readme. Fred Huettig 2014-06-19 05:00:29 -0400
  • 7b0de4b46c Ready for full review. Fred Huettig 2014-06-19 04:45:38 -0400
  • 4e0d8ab797 Changed to a single header for all the PEC_POWER/misc. stuff. Added 3D models for shrouded & right-angle connectors. Fred Huettig 2014-06-18 03:45:09 -0400
  • 1cda51adde Completed design w/3-row XID/YID and various 4-pin IO connectors. Fixed page ordering, changed "Mfr" field to "Manufacturer" Will now re-do to combine all misc. functions onto a single 2xN connector. Fred Huettig 2014-06-17 18:38:32 -0400
  • a0704fed17 Fully routed design, needs checks, drill dwg. Removed elink-north/south as these are now the same. Fred Huettig 2014-06-16 11:48:35 -0400
  • f94ced8afa Schematic is stable, PCB mostly routed. Fred Huettig 2014-06-13 03:41:20 -0400
  • 55696ad7d9 First commit of porcupine board, not complete, not routed, don't use! Fred Huettig 2014-06-05 21:16:55 -0400
  • c292324f4a Markdown updates. Now I will use http://tmpvar.com/markdown.html Fred Huettig 2014-06-04 13:15:40 -0400
  • 374a5a12a0 Readme updates. Fred Huettig 2014-06-04 13:02:04 -0400
  • 0cf275ffdd Added E64 project with HDMI. Some cleanup to paracard template. Fred Huettig 2014-06-03 19:20:33 -0400
  • bfb0513381 The parallella-daughtercard (paracard) template. Fred Huettig 2014-06-02 03:25:41 -0400
  • 20b9239ce6 Yeah, can't have blockquotes within an ordered list without restarting the count. Fred Huettig 2014-05-23 16:18:44 -0400
  • 49f3a0d8e3 Can't put a block quote within a list? Fred Huettig 2014-05-23 16:09:59 -0400
  • 1f9fc65187 Fixed nested lists. Fred Huettig 2014-05-23 16:06:56 -0400
  • 90a4871286 Top-level README update. Fred Huettig 2014-05-23 14:55:04 -0400
  • 41c39add2a README updates. Fred Huettig 2014-05-23 14:36:35 -0400
  • d56c522dcc Added HDMI versions of 7010 and 7020 projects for E16. Requires pulling the external repo "fpgahdl_xilinx," see fpga/externals. Fred Huettig 2014-05-23 12:25:46 -0400
  • cf954a9169 Added external repo fpgahdl_xilinx from analog devices. Added helper scripts for external repo fetch & sparse checkout. Fred Huettig 2014-05-16 14:54:00 -0400