mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-24 11:35:00 +00:00
188 lines
8.3 KiB
Plaintext
188 lines
8.3 KiB
Plaintext
#######################
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# HDMI constraints
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#######################
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NET HDMI_D8 LOC = Y18 | IOSTANDARD = LVCMOS25;
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NET HDMI_D9 LOC = W18 | IOSTANDARD = LVCMOS25;
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NET HDMI_D10 LOC = V18 | IOSTANDARD = LVCMOS25;
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NET HDMI_D11 LOC = U18 | IOSTANDARD = LVCMOS25;
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NET HDMI_D12 LOC = R18 | IOSTANDARD = LVCMOS25;
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NET HDMI_D13 LOC = P18 | IOSTANDARD = LVCMOS25;
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NET HDMI_D14 LOC = Y19 | IOSTANDARD = LVCMOS25;
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NET HDMI_D15 LOC = W19 | IOSTANDARD = LVCMOS25;
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NET HDMI_D16 LOC = U19 | IOSTANDARD = LVCMOS25;
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NET HDMI_D17 LOC = T19 | IOSTANDARD = LVCMOS25;
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NET HDMI_D18 LOC = R19 | IOSTANDARD = LVCMOS25;
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NET HDMI_D19 LOC = P19 | IOSTANDARD = LVCMOS25;
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NET HDMI_D20 LOC = W20 | IOSTANDARD = LVCMOS25;
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NET HDMI_D21 LOC = V20 | IOSTANDARD = LVCMOS25;
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NET HDMI_D22 LOC = U20 | IOSTANDARD = LVCMOS25;
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NET HDMI_D23 LOC = T20 | IOSTANDARD = LVCMOS25;
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NET HDMI_CLK LOC = R17 | IOSTANDARD = LVCMOS25;
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NET HDMI_VSYNC LOC = V17 | IOSTANDARD = LVCMOS25;
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NET HDMI_HSYNC LOC = T17 | IOSTANDARD = LVCMOS25;
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NET HDMI_DE LOC = Y17 | IOSTANDARD = LVCMOS25;
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#NET HDMI_SPDIF LOC = Y16 | IOSTANDARD = LVCMOS25;
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#NET TURBO_MODE LOC = R16 | IOSTANDARD = LVCMOS25;
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NET PS_I2C_SCL LOC = N18 | IOSTANDARD = LVCMOS25;
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NET PS_I2C_SDA LOC = N17 | IOSTANDARD = LVCMOS25;
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#####################
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# Epiphany Interface
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#####################
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# cclk
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NET "RXI_CCLK_P" LOC = "N20" | IOSTANDARD = LVDS_25;
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NET "RXI_CCLK_N" LOC = "P20" | IOSTANDARD = LVDS_25;
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# reset
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NET "DSP_RESET_N" LOC = "G14" | IOSTANDARD = LVCMOS25;
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# flag
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NET "DSP_FLAG" LOC = "J15" | IOSTANDARD = LVCMOS25;
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# rxi lclk
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NET "RXI_LCLK_P" LOC = "F16" | IOSTANDARD = LVDS_25;
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NET "RXI_LCLK_N" LOC = "F17" | IOSTANDARD = LVDS_25;
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# rxi data
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NET "RXI_DATA0_P" LOC = "B19" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA0_N" LOC = "A20" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA1_P" LOC = "C20" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA1_N" LOC = "B20" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA2_P" LOC = "D19" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA2_N" LOC = "D20" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA3_P" LOC = "E18" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA3_N" LOC = "E19" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA4_P" LOC = "E17" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA4_N" LOC = "D18" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA5_P" LOC = "F19" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA5_N" LOC = "F20" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA6_P" LOC = "G17" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA6_N" LOC = "G18" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA7_P" LOC = "G19" | IOSTANDARD = LVDS_25;
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NET "RXI_DATA7_N" LOC = "G20" | IOSTANDARD = LVDS_25;
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#rxi frame
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NET "RXI_FRAME_P" LOC = "H15" | IOSTANDARD = LVDS_25;
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NET "RXI_FRAME_N" LOC = "G15" | IOSTANDARD = LVDS_25;
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#rxo waits
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NET "RXO_RD_WAIT_P" LOC = "H16" | IOSTANDARD = LVDS_25;
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NET "RXO_RD_WAIT_N" LOC = "H17" | IOSTANDARD = LVDS_25;
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NET "RXO_WR_WAIT_P" LOC = "J18" | IOSTANDARD = LVDS_25;
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NET "RXO_WR_WAIT_N" LOC = "H18" | IOSTANDARD = LVDS_25;
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# txo lclk
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#NET "TXO_LCLK_P" LOC = "L14" | IOSTANDARD = LVDS_25; switch with data1
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#NET "TXO_LCLK_N" LOC = "L15" | IOSTANDARD = LVDS_25;
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NET "TXO_LCLK_P" LOC = "K17" | IOSTANDARD = LVDS_25;
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NET "TXO_LCLK_N" LOC = "K18" | IOSTANDARD = LVDS_25;
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# txo data
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NET "TXO_DATA0_P" LOC = "K19" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA0_N" LOC = "J19" | IOSTANDARD = LVDS_25;
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#NET "TXO_DATA1_P" LOC = "K17" | IOSTANDARD = LVDS_25; switch with lclk
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#NET "TXO_DATA1_N" LOC = "K18" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA1_P" LOC = "L14" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA1_N" LOC = "L15" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA2_P" LOC = "L16" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA2_N" LOC = "L17" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA3_P" LOC = "M14" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA3_N" LOC = "M15" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA4_P" LOC = "L19" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA4_N" LOC = "L20" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA5_P" LOC = "M19" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA5_N" LOC = "M20" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA6_P" LOC = "M17" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA6_N" LOC = "M18" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA7_P" LOC = "N15" | IOSTANDARD = LVDS_25;
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NET "TXO_DATA7_N" LOC = "N16" | IOSTANDARD = LVDS_25;
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#txo frame
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NET "TXO_FRAME_P" LOC = "J20" | IOSTANDARD = LVDS_25;
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NET "TXO_FRAME_N" LOC = "H20" | IOSTANDARD = LVDS_25;
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#txi waits
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NET "TXI_RD_WAIT_P" LOC = "K14" | IOSTANDARD = LVDS_25;
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NET "TXI_RD_WAIT_N" LOC = "J14" | IOSTANDARD = LVDS_25;
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NET "TXI_WR_WAIT_P" LOC = "K16" | IOSTANDARD = LVDS_25;
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NET "TXI_WR_WAIT_N" LOC = "J16" | IOSTANDARD = LVDS_25;
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#######################
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# GPIO
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#######################
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NET "GPIO0_P" LOC = "T16" | IOSTANDARD = LVDS_25;
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NET "GPIO0_N" LOC = "U17" | IOSTANDARD = LVDS_25;
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NET "GPIO1_P" LOC = "V16" | IOSTANDARD = LVDS_25;
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NET "GPIO1_N" LOC = "W16" | IOSTANDARD = LVDS_25;
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NET "GPIO2_P" LOC = "P15" | IOSTANDARD = LVDS_25;
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NET "GPIO2_N" LOC = "P16" | IOSTANDARD = LVDS_25;
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NET "GPIO3_P" LOC = "V15" | IOSTANDARD = LVDS_25;
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NET "GPIO3_N" LOC = "W15" | IOSTANDARD = LVDS_25;
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NET "GPIO4_P" LOC = "P14" | IOSTANDARD = LVDS_25;
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NET "GPIO4_N" LOC = "R14" | IOSTANDARD = LVDS_25;
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NET "GPIO5_P" LOC = "T14" | IOSTANDARD = LVDS_25;
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NET "GPIO5_N" LOC = "T15" | IOSTANDARD = LVDS_25;
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NET "GPIO6_P" LOC = "U14" | IOSTANDARD = LVDS_25;
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NET "GPIO6_N" LOC = "U15" | IOSTANDARD = LVDS_25;
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NET "GPIO7_P" LOC = "W14" | IOSTANDARD = LVDS_25;
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NET "GPIO7_N" LOC = "Y14" | IOSTANDARD = LVDS_25;
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NET "GPIO8_P" LOC = "U13" | IOSTANDARD = LVDS_25;
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NET "GPIO8_N" LOC = "V13" | IOSTANDARD = LVDS_25;
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NET "GPIO9_P" LOC = "V12" | IOSTANDARD = LVDS_25;
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NET "GPIO9_N" LOC = "W13" | IOSTANDARD = LVDS_25;
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NET "GPIO10_P" LOC = "T12" | IOSTANDARD = LVDS_25;
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NET "GPIO10_N" LOC = "U12" | IOSTANDARD = LVDS_25;
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NET "GPIO11_P" LOC = "T11" | IOSTANDARD = LVDS_25;
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NET "GPIO11_N" LOC = "T10" | IOSTANDARD = LVDS_25;
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##################################
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# IOs to be used with zc7020 ONLY
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##################################
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NET "GPIO12_P" LOC = "Y12" | IOSTANDARD = LVDS_25;
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NET "GPIO12_N" LOC = "Y13" | IOSTANDARD = LVDS_25;
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NET "GPIO13_P" LOC = "W11" | IOSTANDARD = LVDS_25;
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NET "GPIO13_N" LOC = "Y11" | IOSTANDARD = LVDS_25;
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NET "GPIO14_P" LOC = "V11" | IOSTANDARD = LVDS_25;
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NET "GPIO14_N" LOC = "V10" | IOSTANDARD = LVDS_25;
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NET "GPIO15_P" LOC = "T9" | IOSTANDARD = LVDS_25;
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NET "GPIO15_N" LOC = "U10" | IOSTANDARD = LVDS_25;
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NET "GPIO16_P" LOC = "W10" | IOSTANDARD = LVDS_25;
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NET "GPIO16_N" LOC = "W9" | IOSTANDARD = LVDS_25;
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NET "GPIO17_P" LOC = "U9" | IOSTANDARD = LVDS_25;
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NET "GPIO17_N" LOC = "U8" | IOSTANDARD = LVDS_25;
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NET "GPIO18_P" LOC = "V8" | IOSTANDARD = LVDS_25;
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NET "GPIO18_N" LOC = "W8" | IOSTANDARD = LVDS_25;
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NET "GPIO19_P" LOC = "Y9" | IOSTANDARD = LVDS_25;
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NET "GPIO19_N" LOC = "Y8" | IOSTANDARD = LVDS_25;
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NET "GPIO20_P" LOC = "Y7" | IOSTANDARD = LVDS_25;
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NET "GPIO20_N" LOC = "Y6" | IOSTANDARD = LVDS_25;
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NET "GPIO21_P" LOC = "U7" | IOSTANDARD = LVDS_25;
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NET "GPIO21_N" LOC = "V7" | IOSTANDARD = LVDS_25;
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NET "GPIO22_P" LOC = "V6" | IOSTANDARD = LVDS_25;
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NET "GPIO22_N" LOC = "W6" | IOSTANDARD = LVDS_25;
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NET "GPIO23_P" LOC = "T5" | IOSTANDARD = LVDS_25;
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NET "GPIO23_N" LOC = "U5" | IOSTANDARD = LVDS_25;
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#######################
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# Internal constraints
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#######################
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NET "TXO_LCLK_P" TNM_NET = "TXO_LCLK_P";
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TIMESPEC "TS_TXO_LCLK_P" = PERIOD "TXO_LCLK_P" 6.6ns HIGH 50% INPUT_JITTER 100ps;
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NET "parallella/ewrapper_link_top/io_tx/CLK_IN" TNM_NET = "CLK_IN";
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TIMESPEC "TS_CLK_IN" = PERIOD "CLK_IN" 10ns HIGH 50% INPUT_JITTER 100ps;
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NET "parallella/ewrapper_link_top/io_tx/CLK_IN_90" TNM_NET = "CLK_FWD_IN";
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TIMESPEC "TS_CLK_FWD_IN" = PERIOD "CLK_FWD_IN" 10ns HIGH 50% INPUT_JITTER 100ps;
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INST "parallella/axi_elink_if/fpgacfg/reset_chip_reg_4" TNM = "SW_RESET";
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TIMESPEC "TS_SW_RESET" = FROM "SW_RESET" TIG;
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#INST "rst_sync*" ASYNC_REG = TRUE;
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#PIN "CLK_RESET" TIG;
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#PIN "IO_RESET" TIG;
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NET "system_stub/system_i/processing_system7_0/FCLK_CLK3" TNM_NET = clk_fpga_3;
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TIMESPEC TS_clk_fpga_3 = PERIOD clk_fpga_3 40000 kHz;
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NET "system_stub/system_i/processing_system7_0/FCLK_CLK2" TNM_NET = clk_fpga_2;
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TIMESPEC TS_clk_fpga_2 = PERIOD clk_fpga_2 200000 kHz;
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NET "system_stub/system_i/processing_system7_0/FCLK_CLK1" TNM_NET = clk_fpga_1;
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TIMESPEC TS_clk_fpga_1 = PERIOD clk_fpga_1 200000 kHz;
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NET "system_stub/system_i/processing_system7_0/FCLK_CLK0" TNM_NET = clk_fpga_0;
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TIMESPEC TS_clk_fpga_0 = PERIOD clk_fpga_0 100000 kHz;
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