mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-24 03:34:40 +00:00
71 lines
7.3 KiB
Tcl
71 lines
7.3 KiB
Tcl
create_clock -period 3.333 -name RX_lclk_p -waveform {0.000 1.666} [get_ports RX_lclk_p]
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#set_input_delay -clock [get_clocks RX_lclk_p] -clock_fall -min -add_delay 0.500 [get_ports {RX_data_n[*]}]
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#set_input_delay -clock [get_clocks RX_lclk_p] -clock_fall -max -add_delay 1.166 [get_ports {RX_data_n[*]}]
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#set_input_delay -clock [get_clocks RX_lclk_p] -min -add_delay 0.500 [get_ports {RX_data_n[*]}]
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#set_input_delay -clock [get_clocks RX_lclk_p] -max -add_delay 1.166 [get_ports {RX_data_n[*]}]
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#set_input_delay -clock [get_clocks RX_lclk_p] -clock_fall -min -add_delay 0.500 [get_ports {RX_data_p[*]}]
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#set_input_delay -clock [get_clocks RX_lclk_p] -clock_fall -max -add_delay 1.166 [get_ports {RX_data_p[*]}]
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#set_input_delay -clock [get_clocks RX_lclk_p] -min -add_delay 0.500 [get_ports {RX_data_p[*]}]
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#set_input_delay -clock [get_clocks RX_lclk_p] -max -add_delay 1.166 [get_ports {RX_data_p[*]}]
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#set_input_delay -clock [get_clocks RX_lclk_p] -clock_fall -min -add_delay 0.500 [get_ports RX_frame_n]
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#set_input_delay -clock [get_clocks RX_lclk_p] -clock_fall -max -add_delay 1.166 [get_ports RX_frame_n]
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#set_input_delay -clock [get_clocks RX_lclk_p] -min -add_delay 0.500 [get_ports RX_frame_n]
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#set_input_delay -clock [get_clocks RX_lclk_p] -max -add_delay 1.166 [get_ports RX_frame_n]
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#set_input_delay -clock [get_clocks RX_lclk_p] -clock_fall -min -add_delay 0.500 [get_ports RX_frame_p]
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#set_input_delay -clock [get_clocks RX_lclk_p] -clock_fall -max -add_delay 1.166 [get_ports RX_frame_p]
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#set_input_delay -clock [get_clocks RX_lclk_p] -min -add_delay 0.500 [get_ports RX_frame_p]
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#set_input_delay -clock [get_clocks RX_lclk_p] -max -add_delay 1.166 [get_ports RX_frame_p]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -clock_fall -min -add_delay 0.100 [get_ports {TX_data_n[*]}]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -clock_fall -max -add_delay 1.567 [get_ports {TX_data_n[*]}]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -min -add_delay 0.100 [get_ports {TX_data_n[*]}]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -max -add_delay 1.567 [get_ports {TX_data_n[*]}]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -clock_fall -min -add_delay 0.100 [get_ports {TX_data_p[*]}]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -clock_fall -max -add_delay 1.567 [get_ports {TX_data_p[*]}]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -min -add_delay 0.100 [get_ports {TX_data_p[*]}]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -max -add_delay 1.567 [get_ports {TX_data_p[*]}]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -clock_fall -min -add_delay 0.100 [get_ports TX_frame_n]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -clock_fall -max -add_delay 1.567 [get_ports TX_frame_n]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -min -add_delay 0.100 [get_ports TX_frame_n]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -max -add_delay 1.567 [get_ports TX_frame_n]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -clock_fall -min -add_delay 0.100 [get_ports TX_frame_p]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -clock_fall -max -add_delay 1.567 [get_ports TX_frame_p]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -min -add_delay 0.100 [get_ports TX_frame_p]
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#set_output_delay -clock [get_clocks VIRTUAL_lclk_s_src] -max -add_delay 1.567 [get_ports TX_frame_p]
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set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks cclk_p_src]
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set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks lclk_p_src]
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set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks eio_rx_0_rxlclk_p]
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set_false_path -from [get_clocks eio_rx_0_rxlclk_p] -to [get_clocks clk_fpga_0]
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#set_false_path -from [get_pins {elink2_top_i/proc_sys_reset_0/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]/C}] -to [get_pins {elink2_top_i/elink2/eio_rx_0/inst/rxenb_sync_reg[*]/CLR}]
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#set_false_path -from [get_pins {elink2_top_i/proc_sys_reset_0/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]/C}] -to [get_pins {elink2_top_i/elink2/eproto_tx_0/inst/txdata_p_reg[*]/CLR}]
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#set_false_path -from [get_pins {elink2_top_i/proc_sys_reset_0/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]/C}] -to [get_pins elink2_top_i/elink2/eclock_0/inst/gen_cclk_div.OSERDESE2_inst/RST]
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#set_false_path -from [get_pins {elink2_top_i/proc_sys_reset_0/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]/C}] -to [get_pins {elink2_top_i/elink2/eio_tx_0/inst/gen_serdes[*].OSERDESE2_txdata/RST}]
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#set_false_path -from [get_pins {elink2_top_i/proc_sys_reset_0/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]/C}] -to [get_pins elink2_top_i/elink2/eio_tx_0/inst/OSERDESE2_tframe/RST]
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#set_false_path -from [get_pins {elink2_top_i/proc_sys_reset_0/U0/PR_OUT_DFF[0].peripheral_reset_reg[0]/C}] -to [get_pins {elink2_top_i/elink2/earb_0/inst/fifo_data_reg[*]/R}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eio_tx_0/inst/txenb_out_sync_reg[0]/C}] -to [get_pins elink2_top_i/elink2/eio_tx_0/inst/oddr_lclk_inst/D1]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eio_rx_0/inst/ecfg_datain_reg[*]/C}] -to [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_datain_reg_reg[*]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgclk_reg_reg[1]/C}] -to [get_pins elink2_top_i/elink2/eclock_0/inst/gen_cclk_div.enb_sync_reg/D]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgclk_reg_reg[2]/C}] -to [get_pins elink2_top_i/elink2/eclock_0/inst/gen_cclk_div.enb_sync_reg/D]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgclk_reg_reg[*]/C}] -to [get_pins {elink2_top_i/elink2/eclock_0/inst/gen_cclk_div.clk_div_sync_reg[*]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgrx_reg_reg[0]/C}] -to [get_pins {elink2_top_i/elink2/eio_rx_0/inst/rxenb_sync_reg[*]/CLR}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgrx_reg_reg[1]/C}] -to [get_pins {elink2_top_i/elink2/edistrib_0/inst/rxmmu_sync_reg[1]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgrx_reg_reg[2]/C}] -to [get_pins {elink2_top_i/elink2/eio_rx_0/inst/rxloopback_sync_reg[1]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgrx_reg_reg[2]/C}] -to [get_pins {elink2_top_i/elink2/eio_rx_0/inst/rxgpio_sync_reg[1]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgrx_reg_reg[3]/C}] -to [get_pins {elink2_top_i/elink2/eio_rx_0/inst/rxgpio_sync_reg[1]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgrx_reg_reg[3]/C}] -to [get_pins {elink2_top_i/elink2/eio_rx_0/inst/rxloopback_sync_reg[1]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgtx_reg_reg[0]/C}] -to [get_pins {elink2_top_i/elink2/eio_tx_0/inst/txenb_out_sync_reg[1]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgtx_reg_reg[2]/C}] -to [get_pins {elink2_top_i/elink2/eio_tx_0/inst/txgpio_sync_reg[1]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_cfgtx_reg_reg[3]/C}] -to [get_pins {elink2_top_i/elink2/eio_tx_0/inst/txgpio_sync_reg[1]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_dataout_reg_reg[*]/C}] -to [get_pins {elink2_top_i/elink2/eio_tx_0/inst/pframe_reg[*]/D}]
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#set_false_path -from [get_pins {elink2_top_i/elink2/eCfg_0/inst/ecfg_dataout_reg_reg[*]/C}] -to [get_pins {elink2_top_i/elink2/eio_tx_0/inst/pdata_reg[*]/D}]
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