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40 lines
1.6 KiB
Plaintext
40 lines
1.6 KiB
Plaintext
###############################################################
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## Timing constraints for the Parallella-I board
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## 3/12/14 F. Huettig
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####
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## This file defines timing constraints for the Parallella-I
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## and Zynq 7010 or 7020.
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## Pin constraints are defined elsewhere.
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###############################################################
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#######################
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# Internal constraints
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#######################
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# TX at I/O is TX -FROM- the Epiphany, RX into the FPGA
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NET "TXO_LCLK_P" TNM_NET = "TXO_LCLK_P";
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TIMESPEC "TS_TXO_LCLK_P" = PERIOD "TXO_LCLK_P" 6.66ns HIGH 50% INPUT_JITTER 100ps;
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NET "parallella/ewrapper_link_top/io_tx/CLK_IN" TNM_NET = "CLK_IN";
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TIMESPEC "TS_CLK_IN" = PERIOD "CLK_IN" 3.33ns HIGH 50% INPUT_JITTER 100ps;
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NET "parallella/ewrapper_link_top/io_tx/CLK_IN_90" TNM_NET = "CLK_FWD_IN";
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TIMESPEC "TS_CLK_FWD_IN" = PERIOD "CLK_FWD_IN" 3.33ns HIGH 50% INPUT_JITTER 100ps;
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#INST "rst_sync*" ASYNC_REG = TRUE;
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#PIN "CLK_RESET" TIG;
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#PIN "IO_RESET" TIG;
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# These constraints will be forwarded from the PS module, no need to duplicate them here.
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#NET "system_stub/system_i/processing_system7_0/FCLK_CLK3" TNM_NET = clk_fpga_3;
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#TIMESPEC TS_clk_fpga_3 = PERIOD clk_fpga_3 40000 kHz;
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#NET "system_stub/system_i/processing_system7_0/FCLK_CLK2" TNM_NET = clk_fpga_2;
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#TIMESPEC TS_clk_fpga_2 = PERIOD clk_fpga_2 200000 kHz;
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#NET "system_stub/system_i/processing_system7_0/FCLK_CLK1" TNM_NET = clk_fpga_1;
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#TIMESPEC TS_clk_fpga_1 = PERIOD clk_fpga_1 200000 kHz;
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#NET "system_stub/system_i/processing_system7_0/FCLK_CLK0" TNM_NET = clk_fpga_0;
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#TIMESPEC TS_clk_fpga_0 = PERIOD clk_fpga_0 100000 kHz;
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