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parallella-hw/archive/fpga/ip/xilinx
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Andreas Olofsson 046706db8a Reorg
2016-02-03 00:43:14 -05:00
..
axi_bram_ctrl_16b
Reorg
2016-02-03 00:43:14 -05:00
fifo_async_103x16
Reorg
2016-02-03 00:43:14 -05:00
fifo_async_103x32
Reorg
2016-02-03 00:43:14 -05:00
memory_dp_48x4096
Reorg
2016-02-03 00:43:14 -05:00
README
Reorg
2016-02-03 00:43:14 -05:00

README 

This directory contains generated IP blocks from the Vivado tools.  

Known Issues:  
Xilinx header file 
Portability