mirror of
https://github.com/parallella/parallella-hw.git
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638 lines
26 KiB
XML
638 lines
26 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>adapteva.com</spirit:vendor>
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<spirit:library>Adapteva</spirit:library>
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<spirit:name>earb</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>emm_tx</spirit:name>
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<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>access</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emm_tx_access</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>write</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emm_tx_write</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>datamode</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emm_tx_datamode</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ctrlmode</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emm_tx_ctrlmode</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>dstaddr</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emm_tx_dstaddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>srcaddr</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emm_tx_srcaddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>data</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emm_tx_data</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>wr_wait</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emm_tx_wr_wait</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>rd_wait</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emm_tx_rd_wait</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>emrq</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RD_DATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emrq_rd_data</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RD_EN</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emrq_rd_en</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>EMPTY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emrq_empty</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>emrr</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RD_DATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emrr_rd_data</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RD_EN</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emrr_rd_en</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>EMPTY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emrr_empty</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>emwr</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
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<spirit:master/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RD_DATA</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emwr_rd_data</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RD_EN</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emwr_rd_en</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>EMPTY</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emwr_empty</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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</spirit:busInterfaces>
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<spirit:model>
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<spirit:views>
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<spirit:view>
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<spirit:name>xilinx_verilogsynthesis</spirit:name>
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<spirit:displayName>Verilog Synthesis</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>earb</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>7bd3a338</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
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<spirit:displayName>Verilog Simulation</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>earb</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>7bd3a338</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>e65e5adf</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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</spirit:views>
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<spirit:ports>
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<spirit:port>
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<spirit:name>emwr_empty</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue>1</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emrq_rd_en</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emrr_rd_en</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emm_tx_access</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emm_tx_write</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emm_tx_datamode</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">1</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emm_tx_ctrlmode</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emm_tx_dstaddr</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emm_tx_srcaddr</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emm_tx_data</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>clock</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>reset</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emwr_rd_data</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">102</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue>0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emrq_rd_data</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue>0</spirit:defaultValue>
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<spirit:port>
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<spirit:name>emwr_rd_en</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>wire</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue spirit:format="long" spirit:resolve="immediate">0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emrq_empty</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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<spirit:driver>
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<spirit:defaultValue>1</spirit:defaultValue>
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<spirit:port>
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<spirit:name>emrr_rd_data</spirit:name>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue>0</spirit:defaultValue>
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<spirit:port>
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<spirit:name>emrr_empty</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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<spirit:driver>
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<spirit:defaultValue>1</spirit:defaultValue>
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<spirit:port>
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<spirit:name>emm_tx_rd_wait</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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<spirit:port>
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<spirit:name>emm_tx_wr_wait</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDef>
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|
<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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<spirit:driver>
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<spirit:defaultValue>0</spirit:defaultValue>
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</spirit:driver>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emtx_ack</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:model>
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<spirit:fileSets>
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<spirit:fileSet>
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<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
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|
<spirit:file>
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<spirit:name>hdl/earb.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:userFileType>CHECKSUM_7bd3a338</spirit:userFileType>
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<spirit:fileSet>
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<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
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<spirit:file>
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|
<spirit:name>hdl/earb.v</spirit:name>
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|
<spirit:fileType>verilogSource</spirit:fileType>
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|
</spirit:file>
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|
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|
<spirit:fileSet>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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|
<spirit:file>
|
|
<spirit:name>xgui/earb_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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<spirit:userFileType>CHECKSUM_e65e5adf</spirit:userFileType>
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</spirit:fileSets>
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<spirit:description>eLink 3:1 Arbiter</spirit:description>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>Component_Name</spirit:name>
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|
<spirit:displayName>Component Name</spirit:displayName>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">edistrib_v1_0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
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<xilinx:supportedFamilies>
|
|
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
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|
</xilinx:supportedFamilies>
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<xilinx:taxonomies>
|
|
<xilinx:taxonomy>/BaseIP</xilinx:taxonomy>
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|
</xilinx:taxonomies>
|
|
<xilinx:displayName>earb_v1_0</xilinx:displayName>
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|
<xilinx:vendorDisplayName>Adapteva, Inc.</xilinx:vendorDisplayName>
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|
<xilinx:vendorURL>http://www.adapteva.com</xilinx:vendorURL>
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|
<xilinx:coreRevision>4</xilinx:coreRevision>
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|
<xilinx:upgrades>
|
|
<xilinx:canUpgradeFrom>user.org:user:edistrib:1.0</xilinx:canUpgradeFrom>
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|
</xilinx:upgrades>
|
|
<xilinx:coreCreationDateTime>2014-11-17T20:37:04Z</xilinx:coreCreationDateTime>
|
|
<xilinx:tags>
|
|
<xilinx:tag xilinx:name="adapteva.com:Adapteva:earb:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/earb/ip</xilinx:tag>
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</xilinx:tags>
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</xilinx:coreExtensions>
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<xilinx:packagingInfo>
|
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<xilinx:xilinxVersion>2014.3</xilinx:xilinxVersion>
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<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="0910adfc"/>
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<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="bd7329d4"/>
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<xilinx:checksum xilinx:scope="ports" xilinx:value="ced5cce0"/>
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