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155 lines
4.4 KiB
Verilog
155 lines
4.4 KiB
Verilog
/*
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File: earb.v
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This file is part of the Parallella Project.
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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/*
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########################################################################
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EPIPHANY eMesh Arbiter
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########################################################################
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This block takes three FIFO inputs (write, read request, read response),
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arbitrates between the active channels, and forwards the result on to
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the transmit channel.
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The arbitration order is (fixed, highest to lowest)
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1) read responses
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2) read requests
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3) writes
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*/
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module earb (/*AUTOARG*/
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// Outputs
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emwr_rd_en, emrq_rd_en, emrr_rd_en, emm_tx_access, emm_tx_write,
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emm_tx_datamode, emm_tx_ctrlmode, emm_tx_dstaddr, emm_tx_srcaddr,
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emm_tx_data,
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// Inputs
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clock, reset, emwr_rd_data, emwr_empty, emrq_rd_data, emrq_empty,
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emrr_rd_data, emrr_empty, emm_tx_rd_wait, emm_tx_wr_wait, emtx_ack
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);
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// TX clock
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input clock;
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input reset;
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// FIFO slave port, writes
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input [102:0] emwr_rd_data;
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output emwr_rd_en;
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input emwr_empty;
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// FIFO slave port, read requests
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input [102:0] emrq_rd_data;
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output emrq_rd_en;
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input emrq_empty;
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// FIFO slave port, read responses
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input [102:0] emrr_rd_data;
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output emrr_rd_en;
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input emrr_empty;
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// eMesh master port, to TX
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output emm_tx_access;
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output emm_tx_write;
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output [1:0] emm_tx_datamode;
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output [3:0] emm_tx_ctrlmode;
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output [31:0] emm_tx_dstaddr;
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output [31:0] emm_tx_srcaddr;
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output [31:0] emm_tx_data;
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input emm_tx_rd_wait;
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input emm_tx_wr_wait;
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// Ack from TX protocol module
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input emtx_ack;
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// Control bits inputs (none)
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// output wires
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wire emm_tx_access;
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wire emm_tx_write;
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wire [1:0] emm_tx_datamode;
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wire [3:0] emm_tx_ctrlmode;
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wire [31:0] emm_tx_dstaddr;
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wire [31:0] emm_tx_srcaddr;
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wire [31:0] emm_tx_data;
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//############
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//# Arbitrate & forward
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//############
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reg ready;
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reg [102:0] fifo_data;
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// priority-based ready signals
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wire rr_ready = ~emrr_empty & ~emm_tx_wr_wait;
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wire rq_ready = ~emrq_empty & ~emm_tx_rd_wait & ~rr_ready;
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wire wr_ready = ~emwr_empty & ~emm_tx_wr_wait & ~rr_ready & ~rq_ready;
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// FIFO read enables, when we're idle or done with the current datum
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wire emrr_rd_en = rr_ready & (~ready | emtx_ack);
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wire emrq_rd_en = rq_ready & (~ready | emtx_ack);
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wire emwr_rd_en = wr_ready & (~ready | emtx_ack);
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always @ (posedge clock) begin
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if( reset ) begin
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ready <= 1'b0;
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fifo_data <= 'd0;
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end else begin
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if( emrr_rd_en ) begin
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ready <= 1'b1;
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fifo_data <= emrr_rd_data;
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end else if( emrq_rd_en ) begin
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ready <= 1'b1;
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fifo_data <= emrq_rd_data;
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end else if( emwr_rd_en ) begin
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ready <= 1'b1;
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fifo_data <= emwr_rd_data;
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end else if( emtx_ack ) begin
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ready <= 1'b0;
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end
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end // else: !if( reset )
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end // always @ (posedge clock)
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//#############################
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//# Break-out the emesh signals
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//#############################
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assign emm_tx_access = ready;
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assign emm_tx_write = fifo_data[102];
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assign emm_tx_datamode = fifo_data[101:100];
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assign emm_tx_ctrlmode = fifo_data[99:96];
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assign emm_tx_dstaddr = fifo_data[95:64];
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assign emm_tx_srcaddr = fifo_data[63:32];
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assign emm_tx_data = fifo_data[31:0];
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endmodule // earb
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