mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-24 11:35:00 +00:00
1974 lines
80 KiB
XML
1974 lines
80 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
|
|
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
<spirit:vendor>adapteva.com</spirit:vendor>
|
|
<spirit:library>Adapteva</spirit:library>
|
|
<spirit:name>ecfg_split</spirit:name>
|
|
<spirit:version>1.0</spirit:version>
|
|
<spirit:busInterfaces>
|
|
<spirit:busInterface>
|
|
<spirit:name>mcfg0</spirit:name>
|
|
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sw_reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_sw_reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_tx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_tx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_tx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_ctrl_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_tx_ctrl_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_clkdiv</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_tx_clkdiv</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_rx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_rx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_rx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_loopback_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_rx_loopback_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>coreid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_coreid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>datain</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_datain</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dataout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg0_dataout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>mcfg1</spirit:name>
|
|
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sw_reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_sw_reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_tx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_tx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_tx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_ctrl_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_tx_ctrl_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_clkdiv</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_tx_clkdiv</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_rx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_rx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_rx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_loopback_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_rx_loopback_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>coreid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_coreid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>datain</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_datain</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dataout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg1_dataout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>mcfg2</spirit:name>
|
|
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sw_reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_sw_reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_tx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_tx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_tx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_ctrl_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_tx_ctrl_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_clkdiv</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_tx_clkdiv</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_rx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_rx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_rx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_loopback_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_rx_loopback_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>coreid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_coreid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>datain</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_datain</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dataout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg2_dataout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>mcfg3</spirit:name>
|
|
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sw_reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_sw_reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_tx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_tx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_tx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_ctrl_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_tx_ctrl_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_clkdiv</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_tx_clkdiv</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_rx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_rx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_rx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_loopback_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_rx_loopback_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>coreid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_coreid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>datain</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_datain</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dataout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg3_dataout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>mcfg4</spirit:name>
|
|
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sw_reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_sw_reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_tx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_tx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_tx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_ctrl_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_tx_ctrl_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_clkdiv</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_tx_clkdiv</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_rx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_rx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_rx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_loopback_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_rx_loopback_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>coreid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_coreid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>datain</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_datain</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dataout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>mcfg4_dataout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>slvcfg</spirit:name>
|
|
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>sw_reset</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_sw_reset</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_tx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_tx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_tx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_ctrl_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_tx_ctrl_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_clkdiv</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_tx_clkdiv</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_enable</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_rx_enable</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_mmu_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_rx_mmu_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_gpio_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_rx_gpio_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>rx_loopback_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_rx_loopback_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>coreid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_coreid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>datain</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_datain</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>dataout</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>slvcfg_dataout</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
</spirit:busInterfaces>
|
|
<spirit:model>
|
|
<spirit:views>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
|
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
|
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
|
<spirit:language>verilog</spirit:language>
|
|
<spirit:modelName>ecfg_split</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>47bd32f7</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
|
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
|
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
|
<spirit:language>verilog</spirit:language>
|
|
<spirit:modelName>ecfg_split</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>47bd32f7</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_xpgui</spirit:name>
|
|
<spirit:displayName>UI Layout</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>viewChecksum</spirit:name>
|
|
<spirit:value>e65e5adf</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:view>
|
|
</spirit:views>
|
|
<spirit:ports>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_datain</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_sw_reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_tx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_tx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_tx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_tx_ctrl_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_tx_clkdiv</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_rx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_rx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_rx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_rx_loopback_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_coreid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">11</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_dataout</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_sw_reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_tx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_tx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_tx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_tx_ctrl_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_tx_clkdiv</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_rx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_rx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_rx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_rx_loopback_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_coreid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">11</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_dataout</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_sw_reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_tx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_tx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_tx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_tx_ctrl_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_tx_clkdiv</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_rx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_rx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_rx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_rx_loopback_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_coreid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">11</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_dataout</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_sw_reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_tx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_tx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_tx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_tx_ctrl_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_tx_clkdiv</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_rx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_rx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_rx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_rx_loopback_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_coreid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">11</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_dataout</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_sw_reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_tx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_tx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_tx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_tx_ctrl_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_tx_clkdiv</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_rx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_rx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_rx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_rx_loopback_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_coreid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">11</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_dataout</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_sw_reset</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_tx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_tx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_tx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_tx_ctrl_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_tx_clkdiv</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_rx_enable</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_rx_mmu_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_rx_gpio_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_rx_loopback_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_coreid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">11</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>slvcfg_dataout</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg0_datain</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg1_datain</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg2_datain</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg3_datain</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>mcfg4_datain</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">10</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>std_logic_vector</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
</spirit:ports>
|
|
</spirit:model>
|
|
<spirit:choices>
|
|
<spirit:choice>
|
|
<spirit:name>choices_0</spirit:name>
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choices_1</spirit:name>
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choices_2</spirit:name>
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choices_3</spirit:name>
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choices_4</spirit:name>
|
|
<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
|
|
<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
|
|
</spirit:choice>
|
|
</spirit:choices>
|
|
<spirit:fileSets>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>hdl/ecfg_split.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
|
<spirit:userFileType>CHECKSUM_47bd32f7</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>hdl/ecfg_split.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xgui/ecfg_split_v1_0.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
|
<spirit:userFileType>CHECKSUM_e65e5adf</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
</spirit:fileSets>
|
|
<spirit:description>ecfg_split_v1_0</spirit:description>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>Component_Name</spirit:name>
|
|
<spirit:displayName>Component Name</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">ecfg_split_v1_0</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:coreExtensions>
|
|
<xilinx:supportedFamilies>
|
|
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
|
|
</xilinx:supportedFamilies>
|
|
<xilinx:taxonomies>
|
|
<xilinx:taxonomy>/BaseIP</xilinx:taxonomy>
|
|
</xilinx:taxonomies>
|
|
<xilinx:displayName>ecfg_split_v1_0</xilinx:displayName>
|
|
<xilinx:vendorDisplayName>eCfg Bus Splitter</xilinx:vendorDisplayName>
|
|
<xilinx:vendorURL>http://www.adapteva.com</xilinx:vendorURL>
|
|
<xilinx:coreRevision>3</xilinx:coreRevision>
|
|
<xilinx:upgrades>
|
|
<xilinx:canUpgradeFrom>user.org:user:ecfg_split:1.0</xilinx:canUpgradeFrom>
|
|
</xilinx:upgrades>
|
|
<xilinx:coreCreationDateTime>2014-11-09T03:43:55Z</xilinx:coreCreationDateTime>
|
|
<xilinx:tags>
|
|
<xilinx:tag xilinx:name="adapteva.com:Adapteva:ecfg_split:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/ecfg_split</xilinx:tag>
|
|
</xilinx:tags>
|
|
</xilinx:coreExtensions>
|
|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2014.3</xilinx:xilinxVersion>
|
|
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="e0cff54b"/>
|
|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="45b31379"/>
|
|
<xilinx:checksum xilinx:scope="ports" xilinx:value="121c9740"/>
|
|
<xilinx:checksum xilinx:scope="parameters" xilinx:value="ffab90d3"/>
|
|
</xilinx:packagingInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:component>
|