mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-24 11:35:00 +00:00
292 lines
10 KiB
Verilog
292 lines
10 KiB
Verilog
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/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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//########################################################################
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// EPIPHANY CONFIGURATION BUS SPLITTER
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//########################################################################
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/*
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NOTE: This module is (hopefully) temporary, until Vivado gains the
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ability (or I learn how) to have a custom interface with multiple
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slaves. This issue has been raised with Xilinx.
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*/
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module ecfg_split(/*AUTOARG*/
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// Outputs
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slvcfg_datain, mcfg0_sw_reset, mcfg0_tx_enable, mcfg0_tx_mmu_mode,
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mcfg0_tx_gpio_mode, mcfg0_tx_ctrl_mode, mcfg0_tx_clkdiv,
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mcfg0_rx_enable, mcfg0_rx_mmu_mode, mcfg0_rx_gpio_mode,
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mcfg0_rx_loopback_mode, mcfg0_coreid, mcfg0_dataout,
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mcfg1_sw_reset, mcfg1_tx_enable, mcfg1_tx_mmu_mode,
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mcfg1_tx_gpio_mode, mcfg1_tx_ctrl_mode, mcfg1_tx_clkdiv,
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mcfg1_rx_enable, mcfg1_rx_mmu_mode, mcfg1_rx_gpio_mode,
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mcfg1_rx_loopback_mode, mcfg1_coreid, mcfg1_dataout,
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mcfg2_sw_reset, mcfg2_tx_enable, mcfg2_tx_mmu_mode,
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mcfg2_tx_gpio_mode, mcfg2_tx_ctrl_mode, mcfg2_tx_clkdiv,
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mcfg2_rx_enable, mcfg2_rx_mmu_mode, mcfg2_rx_gpio_mode,
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mcfg2_rx_loopback_mode, mcfg2_coreid, mcfg2_dataout,
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mcfg3_sw_reset, mcfg3_tx_enable, mcfg3_tx_mmu_mode,
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mcfg3_tx_gpio_mode, mcfg3_tx_ctrl_mode, mcfg3_tx_clkdiv,
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mcfg3_rx_enable, mcfg3_rx_mmu_mode, mcfg3_rx_gpio_mode,
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mcfg3_rx_loopback_mode, mcfg3_coreid, mcfg3_dataout,
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mcfg4_sw_reset, mcfg4_tx_enable, mcfg4_tx_mmu_mode,
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mcfg4_tx_gpio_mode, mcfg4_tx_ctrl_mode, mcfg4_tx_clkdiv,
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mcfg4_rx_enable, mcfg4_rx_mmu_mode, mcfg4_rx_gpio_mode,
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mcfg4_rx_loopback_mode, mcfg4_coreid, mcfg4_dataout,
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// Inputs
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slvcfg_sw_reset, slvcfg_tx_enable, slvcfg_tx_mmu_mode,
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slvcfg_tx_gpio_mode, slvcfg_tx_ctrl_mode, slvcfg_tx_clkdiv,
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slvcfg_rx_enable, slvcfg_rx_mmu_mode, slvcfg_rx_gpio_mode,
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slvcfg_rx_loopback_mode, slvcfg_coreid, slvcfg_dataout,
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mcfg0_datain, mcfg1_datain, mcfg2_datain, mcfg3_datain,
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mcfg4_datain
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);
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/*****************************/
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/* Slave (input) Port */
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/*****************************/
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//RESET
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input slvcfg_sw_reset;
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//tx
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input slvcfg_tx_enable; //enable signal for TX
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input slvcfg_tx_mmu_mode; //enables MMU on transnmit path
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input slvcfg_tx_gpio_mode; //forces TX input pins to constants
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input [3:0] slvcfg_tx_ctrl_mode; //value for emesh ctrlmode tag
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input [3:0] slvcfg_tx_clkdiv; //transmit clock divider
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//rx
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input slvcfg_rx_enable; //enable signal for rx
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input slvcfg_rx_mmu_mode; //enables MMU on rx path
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input slvcfg_rx_gpio_mode; //forces rx wait pins to constants
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input slvcfg_rx_loopback_mode; //loops back tx to rx receiver (after serdes)
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//coreid
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input [11:0] slvcfg_coreid; //core-id of fpga elink
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//gpio
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output [10:0] slvcfg_datain; // data from elink inputs
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input [10:0] slvcfg_dataout; //data for elink outputs {rd_wait,wr_wait,frame,data[7:0]}
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/*************************************************/
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/* Master (output) Port #0 */
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/* NOTE: This is the only port that takes input */
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/*************************************************/
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//RESET
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output mcfg0_sw_reset;
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//tx
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output mcfg0_tx_enable;
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output mcfg0_tx_mmu_mode;
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output mcfg0_tx_gpio_mode;
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output [3:0] mcfg0_tx_ctrl_mode;
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output [3:0] mcfg0_tx_clkdiv;
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//rx
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output mcfg0_rx_enable;
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output mcfg0_rx_mmu_mode;
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output mcfg0_rx_gpio_mode;
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output mcfg0_rx_loopback_mode;
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//coreid
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output [11:0] mcfg0_coreid;
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//gpio
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input [10:0] mcfg0_datain;
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output [10:0] mcfg0_dataout;
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/*****************************/
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/* Master (output) Port #1 */
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/*****************************/
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//RESET
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output mcfg1_sw_reset;
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//tx
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output mcfg1_tx_enable;
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output mcfg1_tx_mmu_mode;
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output mcfg1_tx_gpio_mode;
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output [3:0] mcfg1_tx_ctrl_mode;
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output [3:0] mcfg1_tx_clkdiv;
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//rx
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output mcfg1_rx_enable;
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output mcfg1_rx_mmu_mode;
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output mcfg1_rx_gpio_mode;
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output mcfg1_rx_loopback_mode;
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//coreid
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output [11:0] mcfg1_coreid;
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//gpio
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input [10:0] mcfg1_datain;
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output [10:0] mcfg1_dataout;
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/*****************************/
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/* Master (output) Port #2 */
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/*****************************/
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//RESET
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output mcfg2_sw_reset;
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//tx
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output mcfg2_tx_enable;
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output mcfg2_tx_mmu_mode;
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output mcfg2_tx_gpio_mode;
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output [3:0] mcfg2_tx_ctrl_mode;
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output [3:0] mcfg2_tx_clkdiv;
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//rx
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output mcfg2_rx_enable;
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output mcfg2_rx_mmu_mode;
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output mcfg2_rx_gpio_mode;
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output mcfg2_rx_loopback_mode;
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//coreid
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output [11:0] mcfg2_coreid;
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//gpio
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input [10:0] mcfg2_datain;
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output [10:0] mcfg2_dataout;
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/*****************************/
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/* Master (output) Port #3 */
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/*****************************/
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//RESET
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output mcfg3_sw_reset;
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//tx
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output mcfg3_tx_enable;
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output mcfg3_tx_mmu_mode;
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output mcfg3_tx_gpio_mode;
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output [3:0] mcfg3_tx_ctrl_mode;
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output [3:0] mcfg3_tx_clkdiv;
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//rx
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output mcfg3_rx_enable;
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output mcfg3_rx_mmu_mode;
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output mcfg3_rx_gpio_mode;
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output mcfg3_rx_loopback_mode;
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//coreid
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output [11:0] mcfg3_coreid;
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//gpio
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input [10:0] mcfg3_datain;
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output [10:0] mcfg3_dataout;
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/*****************************/
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/* Master (output) Port #4 */
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/*****************************/
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//RESET
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output mcfg4_sw_reset;
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//tx
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output mcfg4_tx_enable;
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output mcfg4_tx_mmu_mode;
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output mcfg4_tx_gpio_mode;
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output [3:0] mcfg4_tx_ctrl_mode;
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output [3:0] mcfg4_tx_clkdiv;
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//rx
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output mcfg4_rx_enable;
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output mcfg4_rx_mmu_mode;
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output mcfg4_rx_gpio_mode;
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output mcfg4_rx_loopback_mode;
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//coreid
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output [11:0] mcfg4_coreid;
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//gpio
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input [10:0] mcfg4_datain;
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output [10:0] mcfg4_dataout;
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/*******************************/
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/* Copy port0 input to master */
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/*******************************/
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assign slvcfg_datain = mcfg0_datain;
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/*******************************/
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/* Split inputs to all outputs */
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/*******************************/
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assign mcfg0_sw_reset = slvcfg_sw_reset;
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assign mcfg0_tx_enable = slvcfg_tx_enable;
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assign mcfg0_tx_mmu_mode = slvcfg_tx_mmu_mode;
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assign mcfg0_tx_gpio_mode = slvcfg_tx_gpio_mode;
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assign mcfg0_tx_ctrl_mode = slvcfg_tx_ctrl_mode;
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assign mcfg0_tx_clkdiv = slvcfg_tx_clkdiv;
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assign mcfg0_rx_enable = slvcfg_rx_enable;
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assign mcfg0_rx_mmu_mode = slvcfg_rx_mmu_mode;
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assign mcfg0_rx_gpio_mode = slvcfg_rx_gpio_mode;
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assign mcfg0_rx_loopback_mode = slvcfg_rx_loopback_mode;
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assign mcfg0_coreid = slvcfg_coreid;
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assign mcfg0_dataout = slvcfg_dataout;
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assign mcfg1_sw_reset = slvcfg_sw_reset;
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assign mcfg1_tx_enable = slvcfg_tx_enable;
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assign mcfg1_tx_mmu_mode = slvcfg_tx_mmu_mode;
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assign mcfg1_tx_gpio_mode = slvcfg_tx_gpio_mode;
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assign mcfg1_tx_ctrl_mode = slvcfg_tx_ctrl_mode;
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assign mcfg1_tx_clkdiv = slvcfg_tx_clkdiv;
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assign mcfg1_rx_enable = slvcfg_rx_enable;
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assign mcfg1_rx_mmu_mode = slvcfg_rx_mmu_mode;
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assign mcfg1_rx_gpio_mode = slvcfg_rx_gpio_mode;
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assign mcfg1_rx_loopback_mode = slvcfg_rx_loopback_mode;
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assign mcfg1_coreid = slvcfg_coreid;
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assign mcfg1_dataout = slvcfg_dataout;
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assign mcfg2_sw_reset = slvcfg_sw_reset;
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assign mcfg2_tx_enable = slvcfg_tx_enable;
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assign mcfg2_tx_mmu_mode = slvcfg_tx_mmu_mode;
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assign mcfg2_tx_gpio_mode = slvcfg_tx_gpio_mode;
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assign mcfg2_tx_ctrl_mode = slvcfg_tx_ctrl_mode;
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assign mcfg2_tx_clkdiv = slvcfg_tx_clkdiv;
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assign mcfg2_rx_enable = slvcfg_rx_enable;
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assign mcfg2_rx_mmu_mode = slvcfg_rx_mmu_mode;
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assign mcfg2_rx_gpio_mode = slvcfg_rx_gpio_mode;
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assign mcfg2_rx_loopback_mode = slvcfg_rx_loopback_mode;
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assign mcfg2_coreid = slvcfg_coreid;
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assign mcfg2_dataout = slvcfg_dataout;
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assign mcfg3_sw_reset = slvcfg_sw_reset;
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assign mcfg3_tx_enable = slvcfg_tx_enable;
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assign mcfg3_tx_mmu_mode = slvcfg_tx_mmu_mode;
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assign mcfg3_tx_gpio_mode = slvcfg_tx_gpio_mode;
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assign mcfg3_tx_ctrl_mode = slvcfg_tx_ctrl_mode;
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assign mcfg3_tx_clkdiv = slvcfg_tx_clkdiv;
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assign mcfg3_rx_enable = slvcfg_rx_enable;
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assign mcfg3_rx_mmu_mode = slvcfg_rx_mmu_mode;
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assign mcfg3_rx_gpio_mode = slvcfg_rx_gpio_mode;
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assign mcfg3_rx_loopback_mode = slvcfg_rx_loopback_mode;
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assign mcfg3_coreid = slvcfg_coreid;
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assign mcfg3_dataout = slvcfg_dataout;
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assign mcfg4_sw_reset = slvcfg_sw_reset;
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assign mcfg4_tx_enable = slvcfg_tx_enable;
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assign mcfg4_tx_mmu_mode = slvcfg_tx_mmu_mode;
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assign mcfg4_tx_gpio_mode = slvcfg_tx_gpio_mode;
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assign mcfg4_tx_ctrl_mode = slvcfg_tx_ctrl_mode;
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assign mcfg4_tx_clkdiv = slvcfg_tx_clkdiv;
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assign mcfg4_rx_enable = slvcfg_rx_enable;
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assign mcfg4_rx_mmu_mode = slvcfg_rx_mmu_mode;
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assign mcfg4_rx_gpio_mode = slvcfg_rx_gpio_mode;
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assign mcfg4_rx_loopback_mode = slvcfg_rx_loopback_mode;
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assign mcfg4_coreid = slvcfg_coreid;
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assign mcfg4_dataout = slvcfg_dataout;
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endmodule // ecfg_split
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