mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-24 11:35:00 +00:00
89 lines
3.5 KiB
XML
89 lines
3.5 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
|
|
<!-- Product Version: Vivado v2014.3 (64-bit) -->
|
|
<!-- -->
|
|
<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
|
|
|
|
<Project Version="7" Minor="2" Path="/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/edistrib/ip_prj/ip_prj.xpr">
|
|
<DefaultLaunch Dir="$PRUNDIR"/>
|
|
<Configuration>
|
|
<Option Name="Id" Val="ecd00d5f19034e309d97ddb757c25c63"/>
|
|
<Option Name="Part" Val="xc7z020clg400-1"/>
|
|
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
|
|
<Option Name="BoardPart" Val=""/>
|
|
<Option Name="ActiveSimSet" Val="sim_1"/>
|
|
<Option Name="DefaultLib" Val="xil_defaultlib"/>
|
|
<Option Name="IPRepoPath" Val="$PPRDIR/../../../src"/>
|
|
</Configuration>
|
|
<FileSets Version="1" Minor="31">
|
|
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
|
|
<Filter Type="Srcs"/>
|
|
<File Path="$PPRDIR/../hdl/edistrib.v">
|
|
<FileInfo>
|
|
<Attr Name="UsedIn" Val="synthesis"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<File Path="$PPRDIR/../component.xml">
|
|
<FileInfo SFType="IPXACT"/>
|
|
</File>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="edistrib"/>
|
|
<Option Name="TopRTLFile" Val="$PPRDIR/../hdl/edistrib.v"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
|
|
<Filter Type="Constrs"/>
|
|
<Config>
|
|
<Option Name="ConstrsType" Val="XDC"/>
|
|
</Config>
|
|
</FileSet>
|
|
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
|
|
<Filter Type="Srcs"/>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="edistrib"/>
|
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
|
<Option Name="TopAutoSet" Val="TRUE"/>
|
|
<Option Name="SrcSet" Val="sources_1"/>
|
|
</Config>
|
|
</FileSet>
|
|
</FileSets>
|
|
<Simulators>
|
|
<Simulator Name="XSim">
|
|
<Option Name="Description" Val="Vivado Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="ModelSim">
|
|
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="IES">
|
|
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
|
</Simulator>
|
|
<Simulator Name="VCS">
|
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
|
</Simulator>
|
|
</Simulators>
|
|
<Runs Version="1" Minor="9">
|
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
</Run>
|
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
</Run>
|
|
</Runs>
|
|
</Project>
|