mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-24 11:35:00 +00:00
420 lines
24 KiB
Plaintext
420 lines
24 KiB
Plaintext
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PARAMETER VERSION = 2.1.0
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PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
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PORT processing_system7_0_PS_SRSTB_pin = processing_system7_0_PS_SRSTB, DIR = I
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PORT processing_system7_0_PS_CLK_pin = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
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PORT processing_system7_0_PS_PORB_pin = processing_system7_0_PS_PORB, DIR = I
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PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
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PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
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PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
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PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
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PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
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PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
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PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
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PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
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PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
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PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
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PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
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PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
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PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
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PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
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PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
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PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
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PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
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PORT hdmi_clk = axi_hdmi_tx_16b_0_hdmi_clk, DIR = O
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PORT hdmi_data = axi_hdmi_tx_16b_0_hdmi_data, DIR = O, VEC = [15:0]
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PORT hdmi_hsync = axi_hdmi_tx_16b_0_hdmi_hsync, DIR = O
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PORT hdmi_vsync = axi_hdmi_tx_16b_0_hdmi_vsync, DIR = O
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PORT hdmi_data_e = axi_hdmi_tx_16b_0_hdmi_data_e, DIR = O
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PORT processing_system7_0_I2C0_SDA_pin = processing_system7_0_I2C0_SDA, DIR = IO
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PORT processing_system7_0_I2C0_SCL_pin = processing_system7_0_I2C0_SCL, DIR = IO
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PORT processing_system7_0_M_AXI_GP1_ARESETN_pin = processing_system7_0_M_AXI_GP1_ARESETN, DIR = O, SIGIS = RST
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PORT processing_system7_0_S_AXI_HP1_ARESETN_pin = processing_system7_0_S_AXI_HP1_ARESETN, DIR = O, SIGIS = RST
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PORT processing_system7_0_FCLK_CLK3_pin = processing_system7_0_FCLK_CLK3, DIR = O, SIGIS = CLK, CLK_FREQ = 40000000
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PORT processing_system7_0_M_AXI_GP1_ARVALID_pin = processing_system7_0_M_AXI_GP1_ARVALID, DIR = O
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PORT processing_system7_0_M_AXI_GP1_AWVALID_pin = processing_system7_0_M_AXI_GP1_AWVALID, DIR = O
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PORT processing_system7_0_M_AXI_GP1_BREADY_pin = processing_system7_0_M_AXI_GP1_BREADY, DIR = O
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PORT processing_system7_0_M_AXI_GP1_RREADY_pin = processing_system7_0_M_AXI_GP1_RREADY, DIR = O
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PORT processing_system7_0_M_AXI_GP1_WLAST_pin = processing_system7_0_M_AXI_GP1_WLAST, DIR = O
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PORT processing_system7_0_M_AXI_GP1_WVALID_pin = processing_system7_0_M_AXI_GP1_WVALID, DIR = O
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PORT processing_system7_0_M_AXI_GP1_ARID_pin = processing_system7_0_M_AXI_GP1_ARID, DIR = O, VEC = [11:0]
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PORT processing_system7_0_M_AXI_GP1_AWID_pin = processing_system7_0_M_AXI_GP1_AWID, DIR = O, VEC = [11:0]
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PORT processing_system7_0_M_AXI_GP1_WID_pin = processing_system7_0_M_AXI_GP1_WID, DIR = O, VEC = [11:0]
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PORT processing_system7_0_M_AXI_GP1_ARBURST_pin = processing_system7_0_M_AXI_GP1_ARBURST, DIR = O, VEC = [1:0]
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PORT processing_system7_0_M_AXI_GP1_ARLOCK_pin = processing_system7_0_M_AXI_GP1_ARLOCK, DIR = O, VEC = [1:0]
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PORT processing_system7_0_M_AXI_GP1_ARSIZE_pin = processing_system7_0_M_AXI_GP1_ARSIZE, DIR = O, VEC = [2:0]
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PORT processing_system7_0_M_AXI_GP1_AWBURST_pin = processing_system7_0_M_AXI_GP1_AWBURST, DIR = O, VEC = [1:0]
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PORT processing_system7_0_M_AXI_GP1_AWLOCK_pin = processing_system7_0_M_AXI_GP1_AWLOCK, DIR = O, VEC = [1:0]
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PORT processing_system7_0_M_AXI_GP1_AWSIZE_pin = processing_system7_0_M_AXI_GP1_AWSIZE, DIR = O, VEC = [2:0]
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PORT processing_system7_0_M_AXI_GP1_ARPROT_pin = processing_system7_0_M_AXI_GP1_ARPROT, DIR = O, VEC = [2:0]
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PORT processing_system7_0_M_AXI_GP1_AWPROT_pin = processing_system7_0_M_AXI_GP1_AWPROT, DIR = O, VEC = [2:0]
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PORT processing_system7_0_M_AXI_GP1_ARADDR_pin = processing_system7_0_M_AXI_GP1_ARADDR, DIR = O, VEC = [31:0]
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PORT processing_system7_0_M_AXI_GP1_AWADDR_pin = processing_system7_0_M_AXI_GP1_AWADDR, DIR = O, VEC = [31:0]
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PORT processing_system7_0_M_AXI_GP1_WDATA_pin = processing_system7_0_M_AXI_GP1_WDATA, DIR = O, VEC = [31:0]
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PORT processing_system7_0_M_AXI_GP1_ARCACHE_pin = processing_system7_0_M_AXI_GP1_ARCACHE, DIR = O, VEC = [3:0]
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PORT processing_system7_0_M_AXI_GP1_ARLEN_pin = processing_system7_0_M_AXI_GP1_ARLEN, DIR = O, VEC = [3:0]
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PORT processing_system7_0_M_AXI_GP1_ARQOS_pin = processing_system7_0_M_AXI_GP1_ARQOS, DIR = O, VEC = [3:0]
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PORT processing_system7_0_M_AXI_GP1_AWCACHE_pin = processing_system7_0_M_AXI_GP1_AWCACHE, DIR = O, VEC = [3:0]
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PORT processing_system7_0_M_AXI_GP1_AWLEN_pin = processing_system7_0_M_AXI_GP1_AWLEN, DIR = O, VEC = [3:0]
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PORT processing_system7_0_M_AXI_GP1_AWQOS_pin = processing_system7_0_M_AXI_GP1_AWQOS, DIR = O, VEC = [3:0]
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PORT processing_system7_0_M_AXI_GP1_WSTRB_pin = processing_system7_0_M_AXI_GP1_WSTRB, DIR = O, VEC = [3:0]
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PORT processing_system7_0_M_AXI_GP1_ACLK_pin = processing_system7_0_M_AXI_GP1_ACLK, DIR = I, SIGIS = CLK
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PORT processing_system7_0_M_AXI_GP1_ARREADY_pin = processing_system7_0_M_AXI_GP1_ARREADY, DIR = I
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PORT processing_system7_0_M_AXI_GP1_AWREADY_pin = processing_system7_0_M_AXI_GP1_AWREADY, DIR = I
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PORT processing_system7_0_M_AXI_GP1_BVALID_pin = processing_system7_0_M_AXI_GP1_BVALID, DIR = I
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PORT processing_system7_0_M_AXI_GP1_RLAST_pin = processing_system7_0_M_AXI_GP1_RLAST, DIR = I
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PORT processing_system7_0_M_AXI_GP1_RVALID_pin = processing_system7_0_M_AXI_GP1_RVALID, DIR = I
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PORT processing_system7_0_M_AXI_GP1_WREADY_pin = processing_system7_0_M_AXI_GP1_WREADY, DIR = I
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PORT processing_system7_0_M_AXI_GP1_BID_pin = processing_system7_0_M_AXI_GP1_BID, DIR = I, VEC = [11:0]
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PORT processing_system7_0_M_AXI_GP1_RID_pin = processing_system7_0_M_AXI_GP1_RID, DIR = I, VEC = [11:0]
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PORT processing_system7_0_M_AXI_GP1_BRESP_pin = processing_system7_0_M_AXI_GP1_BRESP, DIR = I, VEC = [1:0]
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PORT processing_system7_0_M_AXI_GP1_RRESP_pin = processing_system7_0_M_AXI_GP1_RRESP, DIR = I, VEC = [1:0]
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PORT processing_system7_0_M_AXI_GP1_RDATA_pin = processing_system7_0_M_AXI_GP1_RDATA, DIR = I, VEC = [31:0]
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PORT processing_system7_0_S_AXI_HP1_ARREADY_pin = processing_system7_0_S_AXI_HP1_ARREADY, DIR = O
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PORT processing_system7_0_S_AXI_HP1_AWREADY_pin = processing_system7_0_S_AXI_HP1_AWREADY, DIR = O
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PORT processing_system7_0_S_AXI_HP1_BVALID_pin = processing_system7_0_S_AXI_HP1_BVALID, DIR = O
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PORT processing_system7_0_S_AXI_HP1_RLAST_pin = processing_system7_0_S_AXI_HP1_RLAST, DIR = O
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PORT processing_system7_0_S_AXI_HP1_RVALID_pin = processing_system7_0_S_AXI_HP1_RVALID, DIR = O
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PORT processing_system7_0_S_AXI_HP1_WREADY_pin = processing_system7_0_S_AXI_HP1_WREADY, DIR = O
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PORT processing_system7_0_S_AXI_HP1_BRESP_pin = processing_system7_0_S_AXI_HP1_BRESP, DIR = O, VEC = [1:0]
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PORT processing_system7_0_S_AXI_HP1_RRESP_pin = processing_system7_0_S_AXI_HP1_RRESP, DIR = O, VEC = [1:0]
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PORT processing_system7_0_S_AXI_HP1_BID_pin = processing_system7_0_S_AXI_HP1_BID, DIR = O, VEC = [5:0]
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PORT processing_system7_0_S_AXI_HP1_RID_pin = processing_system7_0_S_AXI_HP1_RID, DIR = O, VEC = [5:0]
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PORT processing_system7_0_S_AXI_HP1_RDATA_pin = processing_system7_0_S_AXI_HP1_RDATA, DIR = O, VEC = [63:0]
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PORT processing_system7_0_S_AXI_HP1_ACLK_pin = processing_system7_0_S_AXI_HP1_ACLK, DIR = I, SIGIS = CLK
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PORT processing_system7_0_S_AXI_HP1_ARVALID_pin = processing_system7_0_S_AXI_HP1_ARVALID, DIR = I
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PORT processing_system7_0_S_AXI_HP1_AWVALID_pin = processing_system7_0_S_AXI_HP1_AWVALID, DIR = I
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PORT processing_system7_0_S_AXI_HP1_BREADY_pin = processing_system7_0_S_AXI_HP1_BREADY, DIR = I
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PORT processing_system7_0_S_AXI_HP1_RREADY_pin = processing_system7_0_S_AXI_HP1_RREADY, DIR = I
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PORT processing_system7_0_S_AXI_HP1_WLAST_pin = processing_system7_0_S_AXI_HP1_WLAST, DIR = I
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PORT processing_system7_0_S_AXI_HP1_WVALID_pin = processing_system7_0_S_AXI_HP1_WVALID, DIR = I
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PORT processing_system7_0_S_AXI_HP1_ARBURST_pin = processing_system7_0_S_AXI_HP1_ARBURST, DIR = I, VEC = [1:0]
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PORT processing_system7_0_S_AXI_HP1_ARLOCK_pin = processing_system7_0_S_AXI_HP1_ARLOCK, DIR = I, VEC = [1:0]
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PORT processing_system7_0_S_AXI_HP1_ARSIZE_pin = processing_system7_0_S_AXI_HP1_ARSIZE, DIR = I, VEC = [2:0]
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PORT processing_system7_0_S_AXI_HP1_AWBURST_pin = processing_system7_0_S_AXI_HP1_AWBURST, DIR = I, VEC = [1:0]
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PORT processing_system7_0_S_AXI_HP1_AWLOCK_pin = processing_system7_0_S_AXI_HP1_AWLOCK, DIR = I, VEC = [1:0]
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PORT processing_system7_0_S_AXI_HP1_AWSIZE_pin = processing_system7_0_S_AXI_HP1_AWSIZE, DIR = I, VEC = [2:0]
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PORT processing_system7_0_S_AXI_HP1_ARPROT_pin = processing_system7_0_S_AXI_HP1_ARPROT, DIR = I, VEC = [2:0]
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PORT processing_system7_0_S_AXI_HP1_AWPROT_pin = processing_system7_0_S_AXI_HP1_AWPROT, DIR = I, VEC = [2:0]
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PORT processing_system7_0_S_AXI_HP1_ARADDR_pin = processing_system7_0_S_AXI_HP1_ARADDR, DIR = I, VEC = [31:0]
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PORT processing_system7_0_S_AXI_HP1_AWADDR_pin = processing_system7_0_S_AXI_HP1_AWADDR, DIR = I, VEC = [31:0]
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PORT processing_system7_0_S_AXI_HP1_ARCACHE_pin = processing_system7_0_S_AXI_HP1_ARCACHE, DIR = I, VEC = [3:0]
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PORT processing_system7_0_S_AXI_HP1_ARLEN_pin = processing_system7_0_S_AXI_HP1_ARLEN, DIR = I, VEC = [3:0]
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PORT processing_system7_0_S_AXI_HP1_ARQOS_pin = processing_system7_0_S_AXI_HP1_ARQOS, DIR = I, VEC = [3:0]
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PORT processing_system7_0_S_AXI_HP1_AWCACHE_pin = processing_system7_0_S_AXI_HP1_AWCACHE, DIR = I, VEC = [3:0]
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PORT processing_system7_0_S_AXI_HP1_AWLEN_pin = processing_system7_0_S_AXI_HP1_AWLEN, DIR = I, VEC = [3:0]
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PORT processing_system7_0_S_AXI_HP1_AWQOS_pin = processing_system7_0_S_AXI_HP1_AWQOS, DIR = I, VEC = [3:0]
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PORT processing_system7_0_S_AXI_HP1_ARID_pin = processing_system7_0_S_AXI_HP1_ARID, DIR = I, VEC = [5:0]
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PORT processing_system7_0_S_AXI_HP1_AWID_pin = processing_system7_0_S_AXI_HP1_AWID, DIR = I, VEC = [5:0]
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PORT processing_system7_0_S_AXI_HP1_WID_pin = processing_system7_0_S_AXI_HP1_WID, DIR = I, VEC = [5:0]
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PORT processing_system7_0_S_AXI_HP1_WDATA_pin = processing_system7_0_S_AXI_HP1_WDATA, DIR = I, VEC = [63:0]
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PORT processing_system7_0_S_AXI_HP1_WSTRB_pin = processing_system7_0_S_AXI_HP1_WSTRB, DIR = I, VEC = [7:0]
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PORT axi_spdif_tx_0_spdif_tx_o_pin = axi_spdif_tx_0_spdif_tx_o, DIR = O
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PORT processing_system7_0_GPIO_I_pin = processing_system7_0_GPIO_I, DIR = I, VEC = [47:0]
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PORT processing_system7_0_GPIO_O_pin = processing_system7_0_GPIO_O, DIR = O, VEC = [47:0]
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PORT processing_system7_0_GPIO_T_pin = processing_system7_0_GPIO_T, DIR = O, VEC = [47:0]
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PORT processing_system7_0_FCLK_CLK0_pin = processing_system7_0_FCLK_CLK0_0, DIR = O, SIGIS = CLK, CLK_FREQ = 100000000
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BEGIN processing_system7
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PARAMETER INSTANCE = processing_system7_0
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PARAMETER HW_VER = 4.03.a
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PARAMETER C_DDR_RAM_HIGHADDR = 0x3FFFFFFF
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PARAMETER C_EN_EMIO_CAN0 = 0
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PARAMETER C_EN_EMIO_CAN1 = 0
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PARAMETER C_EN_EMIO_ENET0 = 0
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PARAMETER C_EN_EMIO_ENET1 = 0
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PARAMETER C_EN_EMIO_I2C0 = 1
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PARAMETER C_EN_EMIO_I2C1 = 0
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PARAMETER C_EN_EMIO_PJTAG = 0
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PARAMETER C_EN_EMIO_SDIO0 = 0
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PARAMETER C_EN_EMIO_SDIO1 = 0
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PARAMETER C_EN_EMIO_SPI0 = 0
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PARAMETER C_EN_EMIO_SPI1 = 0
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PARAMETER C_EN_EMIO_SRAM_INT = 0
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PARAMETER C_EN_EMIO_TRACE = 0
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PARAMETER C_EN_EMIO_TTC0 = 0
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PARAMETER C_EN_EMIO_TTC1 = 0
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PARAMETER C_EN_EMIO_UART0 = 0
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PARAMETER C_EN_EMIO_UART1 = 0
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PARAMETER C_EN_EMIO_MODEM_UART0 = 0
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PARAMETER C_EN_EMIO_MODEM_UART1 = 0
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PARAMETER C_EN_EMIO_WDT = 0
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PARAMETER C_EN_QSPI = 1
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PARAMETER C_EN_SMC = 0
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PARAMETER C_EN_CAN0 = 0
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PARAMETER C_EN_CAN1 = 0
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PARAMETER C_EN_ENET0 = 1
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PARAMETER C_EN_ENET1 = 0
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PARAMETER C_EN_I2C0 = 1
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PARAMETER C_EN_I2C1 = 0
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PARAMETER C_EN_PJTAG = 0
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PARAMETER C_EN_SDIO0 = 0
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PARAMETER C_EN_SDIO1 = 1
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PARAMETER C_EN_SPI0 = 0
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PARAMETER C_EN_SPI1 = 0
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PARAMETER C_EN_TRACE = 0
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PARAMETER C_EN_TTC0 = 0
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PARAMETER C_EN_TTC1 = 0
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PARAMETER C_EN_UART0 = 0
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PARAMETER C_EN_UART1 = 1
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PARAMETER C_EN_MODEM_UART0 = 0
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PARAMETER C_EN_MODEM_UART1 = 0
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PARAMETER C_EN_USB0 = 1
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PARAMETER C_EN_USB1 = 1
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PARAMETER C_EN_WDT = 0
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PARAMETER C_EN_DDR = 1
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PARAMETER C_FCLK_CLK0_FREQ = 100000000
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PARAMETER C_FCLK_CLK1_FREQ = 125000000
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PARAMETER C_FCLK_CLK2_FREQ = 200000000
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PARAMETER C_FCLK_CLK3_FREQ = 40000000
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PARAMETER C_USE_M_AXI_GP0 = 1
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PARAMETER C_USE_S_AXI_HP0 = 1
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PARAMETER C_USE_S_AXI_HP2 = 0
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PARAMETER C_INTERCONNECT_S_AXI_HP0_MASTERS = axi_vdma_0.M_AXI_MM2S
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PARAMETER C_INTERCONNECT_S_AXI_HP2_MASTERS = axi_dma_i2s.M_AXI_MM2S & axi_dma_i2s.M_AXI_SG & axi_dma_i2s.M_AXI_S2MM
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PARAMETER C_EN_GPIO = 1
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PARAMETER C_EN_EMIO_CD_SDIO0 = 0
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PARAMETER C_EN_EMIO_WP_SDIO0 = 0
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PARAMETER C_EN_EMIO_CD_SDIO1 = 0
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PARAMETER C_EN_EMIO_WP_SDIO1 = 0
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PARAMETER C_USE_DMA0 = 1
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PARAMETER C_USE_DMA1 = 1
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PARAMETER C_USE_DMA2 = 1
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PARAMETER C_USE_M_AXI_GP1 = 1
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PARAMETER C_USE_S_AXI_HP1 = 1
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PARAMETER C_EN_EMIO_GPIO = 1
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PARAMETER C_EMIO_GPIO_WIDTH = 48
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BUS_INTERFACE M_AXI_GP0 = axi_interconnect_1
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BUS_INTERFACE S_AXI_HP0 = axi_interconnect_2
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PORT MIO = processing_system7_0_MIO
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PORT PS_SRSTB = processing_system7_0_PS_SRSTB
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PORT PS_CLK = processing_system7_0_PS_CLK
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PORT PS_PORB = processing_system7_0_PS_PORB
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PORT DDR_Clk = processing_system7_0_DDR_Clk
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PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
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PORT DDR_CKE = processing_system7_0_DDR_CKE
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PORT DDR_CS_n = processing_system7_0_DDR_CS_n
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PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
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PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
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PORT DDR_WEB = processing_system7_0_DDR_WEB
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PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
|
|
PORT DDR_Addr = processing_system7_0_DDR_Addr
|
|
PORT DDR_ODT = processing_system7_0_DDR_ODT
|
|
PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
|
|
PORT DDR_DQ = processing_system7_0_DDR_DQ
|
|
PORT DDR_DM = processing_system7_0_DDR_DM
|
|
PORT DDR_DQS = processing_system7_0_DDR_DQS
|
|
PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
|
|
PORT DDR_VRN = processing_system7_0_DDR_VRN
|
|
PORT DDR_VRP = processing_system7_0_DDR_VRP
|
|
PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0_0
|
|
PORT FCLK_CLK1 = processing_system7_0_FCLK_CLK1
|
|
PORT FCLK_CLK2 = processing_system7_0_FCLK_CLK2
|
|
PORT FCLK_RESET0_N = processing_system7_0_FCLK_RESET0_N
|
|
PORT FCLK_RESET1_N = processing_system7_0_FCLK_RESET1_N
|
|
PORT M_AXI_GP0_ACLK = processing_system7_0_FCLK_CLK0_0
|
|
PORT S_AXI_HP0_ACLK = processing_system7_0_FCLK_CLK1
|
|
PORT IRQ_F2P = axi_vdma_0_mm2s_introut
|
|
PORT DMA0_ACLK = processing_system7_0_FCLK_CLK0_0
|
|
PORT DMA1_ACLK = processing_system7_0_FCLK_CLK0_0
|
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PORT DMA2_ACLK = processing_system7_0_FCLK_CLK0_0
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PORT I2C0_SDA = processing_system7_0_I2C0_SDA
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PORT I2C0_SCL = processing_system7_0_I2C0_SCL
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PORT M_AXI_GP1_ARESETN = processing_system7_0_M_AXI_GP1_ARESETN
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PORT S_AXI_HP1_ARESETN = processing_system7_0_S_AXI_HP1_ARESETN
|
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PORT M_AXI_GP1_ARVALID = processing_system7_0_M_AXI_GP1_ARVALID
|
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PORT M_AXI_GP1_AWVALID = processing_system7_0_M_AXI_GP1_AWVALID
|
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PORT M_AXI_GP1_BREADY = processing_system7_0_M_AXI_GP1_BREADY
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PORT M_AXI_GP1_RREADY = processing_system7_0_M_AXI_GP1_RREADY
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PORT M_AXI_GP1_WLAST = processing_system7_0_M_AXI_GP1_WLAST
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PORT M_AXI_GP1_WVALID = processing_system7_0_M_AXI_GP1_WVALID
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PORT M_AXI_GP1_ARID = processing_system7_0_M_AXI_GP1_ARID
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PORT M_AXI_GP1_AWID = processing_system7_0_M_AXI_GP1_AWID
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PORT M_AXI_GP1_WID = processing_system7_0_M_AXI_GP1_WID
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PORT M_AXI_GP1_ARBURST = processing_system7_0_M_AXI_GP1_ARBURST
|
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PORT M_AXI_GP1_ARLOCK = processing_system7_0_M_AXI_GP1_ARLOCK
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PORT M_AXI_GP1_ARSIZE = processing_system7_0_M_AXI_GP1_ARSIZE
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PORT M_AXI_GP1_AWBURST = processing_system7_0_M_AXI_GP1_AWBURST
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PORT M_AXI_GP1_AWLOCK = processing_system7_0_M_AXI_GP1_AWLOCK
|
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PORT M_AXI_GP1_AWSIZE = processing_system7_0_M_AXI_GP1_AWSIZE
|
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PORT M_AXI_GP1_ARPROT = processing_system7_0_M_AXI_GP1_ARPROT
|
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PORT M_AXI_GP1_AWPROT = processing_system7_0_M_AXI_GP1_AWPROT
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PORT M_AXI_GP1_ARADDR = processing_system7_0_M_AXI_GP1_ARADDR
|
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PORT M_AXI_GP1_AWADDR = processing_system7_0_M_AXI_GP1_AWADDR
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PORT M_AXI_GP1_WDATA = processing_system7_0_M_AXI_GP1_WDATA
|
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PORT M_AXI_GP1_ARCACHE = processing_system7_0_M_AXI_GP1_ARCACHE
|
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PORT M_AXI_GP1_ARLEN = processing_system7_0_M_AXI_GP1_ARLEN
|
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PORT M_AXI_GP1_ARQOS = processing_system7_0_M_AXI_GP1_ARQOS
|
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PORT M_AXI_GP1_AWCACHE = processing_system7_0_M_AXI_GP1_AWCACHE
|
|
PORT M_AXI_GP1_AWLEN = processing_system7_0_M_AXI_GP1_AWLEN
|
|
PORT M_AXI_GP1_AWQOS = processing_system7_0_M_AXI_GP1_AWQOS
|
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PORT M_AXI_GP1_WSTRB = processing_system7_0_M_AXI_GP1_WSTRB
|
|
PORT M_AXI_GP1_ACLK = processing_system7_0_M_AXI_GP1_ACLK
|
|
PORT M_AXI_GP1_ARREADY = processing_system7_0_M_AXI_GP1_ARREADY
|
|
PORT M_AXI_GP1_AWREADY = processing_system7_0_M_AXI_GP1_AWREADY
|
|
PORT M_AXI_GP1_BVALID = processing_system7_0_M_AXI_GP1_BVALID
|
|
PORT M_AXI_GP1_RLAST = processing_system7_0_M_AXI_GP1_RLAST
|
|
PORT M_AXI_GP1_RVALID = processing_system7_0_M_AXI_GP1_RVALID
|
|
PORT M_AXI_GP1_WREADY = processing_system7_0_M_AXI_GP1_WREADY
|
|
PORT M_AXI_GP1_BID = processing_system7_0_M_AXI_GP1_BID
|
|
PORT M_AXI_GP1_RID = processing_system7_0_M_AXI_GP1_RID
|
|
PORT M_AXI_GP1_BRESP = processing_system7_0_M_AXI_GP1_BRESP
|
|
PORT M_AXI_GP1_RRESP = processing_system7_0_M_AXI_GP1_RRESP
|
|
PORT M_AXI_GP1_RDATA = processing_system7_0_M_AXI_GP1_RDATA
|
|
PORT S_AXI_HP1_ARREADY = processing_system7_0_S_AXI_HP1_ARREADY
|
|
PORT S_AXI_HP1_AWREADY = processing_system7_0_S_AXI_HP1_AWREADY
|
|
PORT S_AXI_HP1_BVALID = processing_system7_0_S_AXI_HP1_BVALID
|
|
PORT S_AXI_HP1_RLAST = processing_system7_0_S_AXI_HP1_RLAST
|
|
PORT S_AXI_HP1_RVALID = processing_system7_0_S_AXI_HP1_RVALID
|
|
PORT S_AXI_HP1_WREADY = processing_system7_0_S_AXI_HP1_WREADY
|
|
PORT S_AXI_HP1_BRESP = processing_system7_0_S_AXI_HP1_BRESP
|
|
PORT S_AXI_HP1_RRESP = processing_system7_0_S_AXI_HP1_RRESP
|
|
PORT S_AXI_HP1_BID = processing_system7_0_S_AXI_HP1_BID
|
|
PORT S_AXI_HP1_RID = processing_system7_0_S_AXI_HP1_RID
|
|
PORT S_AXI_HP1_RDATA = processing_system7_0_S_AXI_HP1_RDATA
|
|
PORT S_AXI_HP1_ACLK = processing_system7_0_S_AXI_HP1_ACLK
|
|
PORT S_AXI_HP1_ARVALID = processing_system7_0_S_AXI_HP1_ARVALID
|
|
PORT S_AXI_HP1_AWVALID = processing_system7_0_S_AXI_HP1_AWVALID
|
|
PORT S_AXI_HP1_BREADY = processing_system7_0_S_AXI_HP1_BREADY
|
|
PORT S_AXI_HP1_RREADY = processing_system7_0_S_AXI_HP1_RREADY
|
|
PORT S_AXI_HP1_WLAST = processing_system7_0_S_AXI_HP1_WLAST
|
|
PORT S_AXI_HP1_WVALID = processing_system7_0_S_AXI_HP1_WVALID
|
|
PORT S_AXI_HP1_ARBURST = processing_system7_0_S_AXI_HP1_ARBURST
|
|
PORT S_AXI_HP1_ARLOCK = processing_system7_0_S_AXI_HP1_ARLOCK
|
|
PORT S_AXI_HP1_ARSIZE = processing_system7_0_S_AXI_HP1_ARSIZE
|
|
PORT S_AXI_HP1_AWBURST = processing_system7_0_S_AXI_HP1_AWBURST
|
|
PORT S_AXI_HP1_AWLOCK = processing_system7_0_S_AXI_HP1_AWLOCK
|
|
PORT S_AXI_HP1_AWSIZE = processing_system7_0_S_AXI_HP1_AWSIZE
|
|
PORT S_AXI_HP1_ARPROT = processing_system7_0_S_AXI_HP1_ARPROT
|
|
PORT S_AXI_HP1_AWPROT = processing_system7_0_S_AXI_HP1_AWPROT
|
|
PORT S_AXI_HP1_ARADDR = processing_system7_0_S_AXI_HP1_ARADDR
|
|
PORT S_AXI_HP1_AWADDR = processing_system7_0_S_AXI_HP1_AWADDR
|
|
PORT S_AXI_HP1_ARCACHE = processing_system7_0_S_AXI_HP1_ARCACHE
|
|
PORT S_AXI_HP1_ARLEN = processing_system7_0_S_AXI_HP1_ARLEN
|
|
PORT S_AXI_HP1_ARQOS = processing_system7_0_S_AXI_HP1_ARQOS
|
|
PORT S_AXI_HP1_AWCACHE = processing_system7_0_S_AXI_HP1_AWCACHE
|
|
PORT S_AXI_HP1_AWLEN = processing_system7_0_S_AXI_HP1_AWLEN
|
|
PORT S_AXI_HP1_AWQOS = processing_system7_0_S_AXI_HP1_AWQOS
|
|
PORT S_AXI_HP1_ARID = processing_system7_0_S_AXI_HP1_ARID
|
|
PORT S_AXI_HP1_AWID = processing_system7_0_S_AXI_HP1_AWID
|
|
PORT S_AXI_HP1_WID = processing_system7_0_S_AXI_HP1_WID
|
|
PORT S_AXI_HP1_WDATA = processing_system7_0_S_AXI_HP1_WDATA
|
|
PORT S_AXI_HP1_WSTRB = processing_system7_0_S_AXI_HP1_WSTRB
|
|
PORT FCLK_CLK3 = processing_system7_0_FCLK_CLK3
|
|
PORT DMA0_DATYPE = axi_spdif_tx_0_DMA_REQ_DATYPE
|
|
PORT DMA0_DAVALID = axi_spdif_tx_0_DMA_REQ_DAVALID
|
|
PORT DMA0_DRREADY = axi_spdif_tx_0_DMA_REQ_DRREADY
|
|
PORT DMA0_RSTN = axi_spdif_tx_0_DMA_REQ_RSTN
|
|
PORT DMA0_DAREADY = axi_spdif_tx_0_DMA_REQ_DAREADY
|
|
PORT DMA0_DRLAST = axi_spdif_tx_0_DMA_REQ_DRLAST
|
|
PORT DMA0_DRVALID = axi_spdif_tx_0_DMA_REQ_DRVALID
|
|
PORT DMA0_DRTYPE = axi_spdif_tx_0_DMA_REQ_DRTYPE
|
|
PORT GPIO_I = processing_system7_0_GPIO_I
|
|
PORT GPIO_O = processing_system7_0_GPIO_O
|
|
PORT GPIO_T = processing_system7_0_GPIO_T
|
|
END
|
|
|
|
BEGIN axi_vdma
|
|
PARAMETER INSTANCE = axi_vdma_0
|
|
PARAMETER HW_VER = 5.04.a
|
|
PARAMETER C_USE_FSYNC = 1
|
|
PARAMETER C_INCLUDE_S2MM = 0
|
|
PARAMETER C_M_AXI_MM2S_DATA_WIDTH = 64
|
|
PARAMETER C_M_AXIS_MM2S_TDATA_WIDTH = 64
|
|
PARAMETER C_MM2S_LINEBUFFER_THRESH = 8
|
|
PARAMETER C_BASEADDR = 0x43000000
|
|
PARAMETER C_HIGHADDR = 0x4300ffff
|
|
BUS_INTERFACE S_AXI_LITE = axi_interconnect_1
|
|
BUS_INTERFACE M_AXI_MM2S = axi_interconnect_2
|
|
BUS_INTERFACE M_AXIS_MM2S = axi_vdma_0_M_AXIS_MM2S
|
|
PORT m_axis_mm2s_aclk = processing_system7_0_FCLK_CLK1
|
|
PORT mm2s_fsync_out = axi_vdma_0_mm2s_fsync_out
|
|
PORT mm2s_buffer_almost_empty = axi_vdma_0_mm2s_buffer_almost_empty
|
|
PORT mm2s_buffer_empty = axi_vdma_0_mm2s_buffer_empty
|
|
PORT mm2s_fsync = axi_hdmi_tx_16b_0_vdma_fs
|
|
PORT s_axi_lite_aclk = processing_system7_0_FCLK_CLK0_0
|
|
PORT m_axi_mm2s_aclk = processing_system7_0_FCLK_CLK1
|
|
PORT mm2s_introut = axi_vdma_0_mm2s_introut
|
|
END
|
|
|
|
BEGIN axi_interconnect
|
|
PARAMETER INSTANCE = axi_interconnect_1
|
|
PARAMETER HW_VER = 1.06.a
|
|
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 0
|
|
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET0_N
|
|
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK0_0
|
|
END
|
|
|
|
BEGIN axi_interconnect
|
|
PARAMETER INSTANCE = axi_interconnect_2
|
|
PARAMETER HW_VER = 1.06.a
|
|
PARAMETER C_INTERCONNECT_CONNECTIVITY_MODE = 1
|
|
PORT INTERCONNECT_ACLK = processing_system7_0_FCLK_CLK1
|
|
PORT INTERCONNECT_ARESETN = processing_system7_0_FCLK_RESET1_N
|
|
END
|
|
|
|
BEGIN axi_hdmi_tx_16b
|
|
PARAMETER INSTANCE = axi_hdmi_tx_16b_0
|
|
PARAMETER HW_VER = 1.00.a
|
|
PARAMETER C_BASEADDR = 0x6c000000
|
|
PARAMETER C_HIGHADDR = 0x6c00ffff
|
|
BUS_INTERFACE S_AXI = axi_interconnect_1
|
|
BUS_INTERFACE M_AXIS_MM2S = axi_vdma_0_M_AXIS_MM2S
|
|
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0_0
|
|
PORT hdmi_ref_clk = axi_hdmi_tx_16b_0_hdmi_ref_clk
|
|
PORT hdmi_clk = axi_hdmi_tx_16b_0_hdmi_clk
|
|
PORT hdmi_data = axi_hdmi_tx_16b_0_hdmi_data
|
|
PORT hdmi_hsync = axi_hdmi_tx_16b_0_hdmi_hsync
|
|
PORT hdmi_vsync = axi_hdmi_tx_16b_0_hdmi_vsync
|
|
PORT hdmi_data_e = axi_hdmi_tx_16b_0_hdmi_data_e
|
|
PORT vdma_clk = processing_system7_0_FCLK_CLK1
|
|
PORT vdma_fs = axi_hdmi_tx_16b_0_vdma_fs
|
|
PORT vdma_fs_ret = axi_vdma_0_mm2s_fsync_out
|
|
PORT vdma_empty = axi_vdma_0_mm2s_buffer_empty
|
|
PORT vdma_almost_empty = axi_vdma_0_mm2s_buffer_almost_empty
|
|
END
|
|
|
|
BEGIN axi_clkgen
|
|
PARAMETER INSTANCE = axi_clkgen_0
|
|
PARAMETER HW_VER = 1.00.a
|
|
PARAMETER C_BASEADDR = 0x66000000
|
|
PARAMETER C_HIGHADDR = 0x6600ffff
|
|
BUS_INTERFACE S_AXI = axi_interconnect_1
|
|
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0_0
|
|
PORT ref_clk = processing_system7_0_FCLK_CLK2
|
|
PORT clk = axi_hdmi_tx_16b_0_hdmi_ref_clk
|
|
END
|
|
|
|
BEGIN axi_spdif_tx
|
|
PARAMETER INSTANCE = axi_spdif_tx_0
|
|
PARAMETER HW_VER = 1.00.a
|
|
PARAMETER C_BASEADDR = 0x75c00000
|
|
PARAMETER C_HIGHADDR = 0x75c0ffff
|
|
PARAMETER C_DMA_TYPE = 1
|
|
BUS_INTERFACE S_AXI = axi_interconnect_1
|
|
PORT S_AXI_ACLK = processing_system7_0_FCLK_CLK0_0
|
|
PORT spdif_tx_o = axi_spdif_tx_0_spdif_tx_o
|
|
PORT spdif_data_clk = clock_generator_0_CLKOUT0
|
|
PORT DMA_REQ_ACLK = processing_system7_0_FCLK_CLK0_0
|
|
PORT DMA_REQ_RSTN = axi_spdif_tx_0_DMA_REQ_RSTN
|
|
PORT DMA_REQ_DAVALID = axi_spdif_tx_0_DMA_REQ_DAVALID
|
|
PORT DMA_REQ_DATYPE = axi_spdif_tx_0_DMA_REQ_DATYPE
|
|
PORT DMA_REQ_DRREADY = axi_spdif_tx_0_DMA_REQ_DRREADY
|
|
PORT DMA_REQ_DRVALID = axi_spdif_tx_0_DMA_REQ_DRVALID
|
|
PORT DMA_REQ_DRTYPE = axi_spdif_tx_0_DMA_REQ_DRTYPE
|
|
PORT DMA_REQ_DRLAST = axi_spdif_tx_0_DMA_REQ_DRLAST
|
|
PORT DMA_REQ_DAREADY = axi_spdif_tx_0_DMA_REQ_DAREADY
|
|
END
|
|
|
|
BEGIN clock_generator
|
|
PARAMETER INSTANCE = clock_generator_0
|
|
PARAMETER HW_VER = 4.03.a
|
|
PORT CLKOUT0 = clock_generator_0_CLKOUT0
|
|
PORT RST = net_gnd
|
|
PORT CLKIN = processing_system7_0_FCLK_CLK0_0
|
|
END
|
|
|