parallella-hw/archive/fpga/old/edk/parallella_7020_headless/system.mhs

 PARAMETER VERSION = 2.1.0


 PORT processing_system7_0_MIO = processing_system7_0_MIO, DIR = IO, VEC = [53:0]
 PORT processing_system7_0_PS_SRSTB_pin = processing_system7_0_PS_SRSTB, DIR = I
 PORT processing_system7_0_PS_CLK_pin = processing_system7_0_PS_CLK, DIR = I, SIGIS = CLK
 PORT processing_system7_0_PS_PORB_pin = processing_system7_0_PS_PORB, DIR = I
 PORT processing_system7_0_DDR_Clk = processing_system7_0_DDR_Clk, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_Clk_n = processing_system7_0_DDR_Clk_n, DIR = IO, SIGIS = CLK
 PORT processing_system7_0_DDR_CKE = processing_system7_0_DDR_CKE, DIR = IO
 PORT processing_system7_0_DDR_CS_n = processing_system7_0_DDR_CS_n, DIR = IO
 PORT processing_system7_0_DDR_RAS_n = processing_system7_0_DDR_RAS_n, DIR = IO
 PORT processing_system7_0_DDR_CAS_n = processing_system7_0_DDR_CAS_n, DIR = IO
 PORT processing_system7_0_DDR_WEB_pin = processing_system7_0_DDR_WEB, DIR = O
 PORT processing_system7_0_DDR_BankAddr = processing_system7_0_DDR_BankAddr, DIR = IO, VEC = [2:0]
 PORT processing_system7_0_DDR_Addr = processing_system7_0_DDR_Addr, DIR = IO, VEC = [14:0]
 PORT processing_system7_0_DDR_ODT = processing_system7_0_DDR_ODT, DIR = IO
 PORT processing_system7_0_DDR_DRSTB = processing_system7_0_DDR_DRSTB, DIR = IO, SIGIS = RST
 PORT processing_system7_0_DDR_DQ = processing_system7_0_DDR_DQ, DIR = IO, VEC = [31:0]
 PORT processing_system7_0_DDR_DM = processing_system7_0_DDR_DM, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS = processing_system7_0_DDR_DQS, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_DQS_n = processing_system7_0_DDR_DQS_n, DIR = IO, VEC = [3:0]
 PORT processing_system7_0_DDR_VRN = processing_system7_0_DDR_VRN, DIR = IO
 PORT processing_system7_0_DDR_VRP = processing_system7_0_DDR_VRP, DIR = IO
 PORT processing_system7_0_M_AXI_GP1_ARESETN_pin = processing_system7_0_M_AXI_GP1_ARESETN, DIR = O, SIGIS = RST
 PORT processing_system7_0_S_AXI_HP1_ARESETN_pin = processing_system7_0_S_AXI_HP1_ARESETN, DIR = O, SIGIS = RST
 PORT processing_system7_0_FCLK_CLK3_pin = processing_system7_0_FCLK_CLK3, DIR = O, SIGIS = CLK, CLK_FREQ = 40000000
 PORT processing_system7_0_FCLK_CLK0_pin = processing_system7_0_FCLK_CLK0, DIR = O, SIGIS = CLK, CLK_FREQ = 100000000
 PORT processing_system7_0_M_AXI_GP1_ARVALID_pin = processing_system7_0_M_AXI_GP1_ARVALID, DIR = O
 PORT processing_system7_0_M_AXI_GP1_AWVALID_pin = processing_system7_0_M_AXI_GP1_AWVALID, DIR = O
 PORT processing_system7_0_M_AXI_GP1_BREADY_pin = processing_system7_0_M_AXI_GP1_BREADY, DIR = O
 PORT processing_system7_0_M_AXI_GP1_RREADY_pin = processing_system7_0_M_AXI_GP1_RREADY, DIR = O
 PORT processing_system7_0_M_AXI_GP1_WLAST_pin = processing_system7_0_M_AXI_GP1_WLAST, DIR = O
 PORT processing_system7_0_M_AXI_GP1_WVALID_pin = processing_system7_0_M_AXI_GP1_WVALID, DIR = O
 PORT processing_system7_0_M_AXI_GP1_ARID_pin = processing_system7_0_M_AXI_GP1_ARID, DIR = O, VEC = [11:0]
 PORT processing_system7_0_M_AXI_GP1_AWID_pin = processing_system7_0_M_AXI_GP1_AWID, DIR = O, VEC = [11:0]
 PORT processing_system7_0_M_AXI_GP1_WID_pin = processing_system7_0_M_AXI_GP1_WID, DIR = O, VEC = [11:0]
 PORT processing_system7_0_M_AXI_GP1_ARBURST_pin = processing_system7_0_M_AXI_GP1_ARBURST, DIR = O, VEC = [1:0]
 PORT processing_system7_0_M_AXI_GP1_ARLOCK_pin = processing_system7_0_M_AXI_GP1_ARLOCK, DIR = O, VEC = [1:0]
 PORT processing_system7_0_M_AXI_GP1_ARSIZE_pin = processing_system7_0_M_AXI_GP1_ARSIZE, DIR = O, VEC = [2:0]
 PORT processing_system7_0_M_AXI_GP1_AWBURST_pin = processing_system7_0_M_AXI_GP1_AWBURST, DIR = O, VEC = [1:0]
 PORT processing_system7_0_M_AXI_GP1_AWLOCK_pin = processing_system7_0_M_AXI_GP1_AWLOCK, DIR = O, VEC = [1:0]
 PORT processing_system7_0_M_AXI_GP1_AWSIZE_pin = processing_system7_0_M_AXI_GP1_AWSIZE, DIR = O, VEC = [2:0]
 PORT processing_system7_0_M_AXI_GP1_ARPROT_pin = processing_system7_0_M_AXI_GP1_ARPROT, DIR = O, VEC = [2:0]
 PORT processing_system7_0_M_AXI_GP1_AWPROT_pin = processing_system7_0_M_AXI_GP1_AWPROT, DIR = O, VEC = [2:0]
 PORT processing_system7_0_M_AXI_GP1_ARADDR_pin = processing_system7_0_M_AXI_GP1_ARADDR, DIR = O, VEC = [31:0]
 PORT processing_system7_0_M_AXI_GP1_AWADDR_pin = processing_system7_0_M_AXI_GP1_AWADDR, DIR = O, VEC = [31:0]
 PORT processing_system7_0_M_AXI_GP1_WDATA_pin = processing_system7_0_M_AXI_GP1_WDATA, DIR = O, VEC = [31:0]
 PORT processing_system7_0_M_AXI_GP1_ARCACHE_pin = processing_system7_0_M_AXI_GP1_ARCACHE, DIR = O, VEC = [3:0]
 PORT processing_system7_0_M_AXI_GP1_ARLEN_pin = processing_system7_0_M_AXI_GP1_ARLEN, DIR = O, VEC = [3:0]
 PORT processing_system7_0_M_AXI_GP1_ARQOS_pin = processing_system7_0_M_AXI_GP1_ARQOS, DIR = O, VEC = [3:0]
 PORT processing_system7_0_M_AXI_GP1_AWCACHE_pin = processing_system7_0_M_AXI_GP1_AWCACHE, DIR = O, VEC = [3:0]
 PORT processing_system7_0_M_AXI_GP1_AWLEN_pin = processing_system7_0_M_AXI_GP1_AWLEN, DIR = O, VEC = [3:0]
 PORT processing_system7_0_M_AXI_GP1_AWQOS_pin = processing_system7_0_M_AXI_GP1_AWQOS, DIR = O, VEC = [3:0]
 PORT processing_system7_0_M_AXI_GP1_WSTRB_pin = processing_system7_0_M_AXI_GP1_WSTRB, DIR = O, VEC = [3:0]
 PORT processing_system7_0_M_AXI_GP1_ACLK_pin = processing_system7_0_M_AXI_GP1_ACLK, DIR = I, SIGIS = CLK
 PORT processing_system7_0_M_AXI_GP1_ARREADY_pin = processing_system7_0_M_AXI_GP1_ARREADY, DIR = I
 PORT processing_system7_0_M_AXI_GP1_AWREADY_pin = processing_system7_0_M_AXI_GP1_AWREADY, DIR = I
 PORT processing_system7_0_M_AXI_GP1_BVALID_pin = processing_system7_0_M_AXI_GP1_BVALID, DIR = I
 PORT processing_system7_0_M_AXI_GP1_RLAST_pin = processing_system7_0_M_AXI_GP1_RLAST, DIR = I
 PORT processing_system7_0_M_AXI_GP1_RVALID_pin = processing_system7_0_M_AXI_GP1_RVALID, DIR = I
 PORT processing_system7_0_M_AXI_GP1_WREADY_pin = processing_system7_0_M_AXI_GP1_WREADY, DIR = I
 PORT processing_system7_0_M_AXI_GP1_BID_pin = processing_system7_0_M_AXI_GP1_BID, DIR = I, VEC = [11:0]
 PORT processing_system7_0_M_AXI_GP1_RID_pin = processing_system7_0_M_AXI_GP1_RID, DIR = I, VEC = [11:0]
 PORT processing_system7_0_M_AXI_GP1_BRESP_pin = processing_system7_0_M_AXI_GP1_BRESP, DIR = I, VEC = [1:0]
 PORT processing_system7_0_M_AXI_GP1_RRESP_pin = processing_system7_0_M_AXI_GP1_RRESP, DIR = I, VEC = [1:0]
 PORT processing_system7_0_M_AXI_GP1_RDATA_pin = processing_system7_0_M_AXI_GP1_RDATA, DIR = I, VEC = [31:0]
 PORT processing_system7_0_S_AXI_HP1_ARREADY_pin = processing_system7_0_S_AXI_HP1_ARREADY, DIR = O
 PORT processing_system7_0_S_AXI_HP1_AWREADY_pin = processing_system7_0_S_AXI_HP1_AWREADY, DIR = O
 PORT processing_system7_0_S_AXI_HP1_BVALID_pin = processing_system7_0_S_AXI_HP1_BVALID, DIR = O
 PORT processing_system7_0_S_AXI_HP1_RLAST_pin = processing_system7_0_S_AXI_HP1_RLAST, DIR = O
 PORT processing_system7_0_S_AXI_HP1_RVALID_pin = processing_system7_0_S_AXI_HP1_RVALID, DIR = O
 PORT processing_system7_0_S_AXI_HP1_WREADY_pin = processing_system7_0_S_AXI_HP1_WREADY, DIR = O
 PORT processing_system7_0_S_AXI_HP1_BRESP_pin = processing_system7_0_S_AXI_HP1_BRESP, DIR = O, VEC = [1:0]
 PORT processing_system7_0_S_AXI_HP1_RRESP_pin = processing_system7_0_S_AXI_HP1_RRESP, DIR = O, VEC = [1:0]
 PORT processing_system7_0_S_AXI_HP1_BID_pin = processing_system7_0_S_AXI_HP1_BID, DIR = O, VEC = [5:0]
 PORT processing_system7_0_S_AXI_HP1_RID_pin = processing_system7_0_S_AXI_HP1_RID, DIR = O, VEC = [5:0]
 PORT processing_system7_0_S_AXI_HP1_RDATA_pin = processing_system7_0_S_AXI_HP1_RDATA, DIR = O, VEC = [63:0]
 PORT processing_system7_0_S_AXI_HP1_ACLK_pin = processing_system7_0_S_AXI_HP1_ACLK, DIR = I, SIGIS = CLK
 PORT processing_system7_0_S_AXI_HP1_ARVALID_pin = processing_system7_0_S_AXI_HP1_ARVALID, DIR = I
 PORT processing_system7_0_S_AXI_HP1_AWVALID_pin = processing_system7_0_S_AXI_HP1_AWVALID, DIR = I
 PORT processing_system7_0_S_AXI_HP1_BREADY_pin = processing_system7_0_S_AXI_HP1_BREADY, DIR = I
 PORT processing_system7_0_S_AXI_HP1_RREADY_pin = processing_system7_0_S_AXI_HP1_RREADY, DIR = I
 PORT processing_system7_0_S_AXI_HP1_WLAST_pin = processing_system7_0_S_AXI_HP1_WLAST, DIR = I
 PORT processing_system7_0_S_AXI_HP1_WVALID_pin = processing_system7_0_S_AXI_HP1_WVALID, DIR = I
 PORT processing_system7_0_S_AXI_HP1_ARBURST_pin = processing_system7_0_S_AXI_HP1_ARBURST, DIR = I, VEC = [1:0]
 PORT processing_system7_0_S_AXI_HP1_ARLOCK_pin = processing_system7_0_S_AXI_HP1_ARLOCK, DIR = I, VEC = [1:0]
 PORT processing_system7_0_S_AXI_HP1_ARSIZE_pin = processing_system7_0_S_AXI_HP1_ARSIZE, DIR = I, VEC = [2:0]
 PORT processing_system7_0_S_AXI_HP1_AWBURST_pin = processing_system7_0_S_AXI_HP1_AWBURST, DIR = I, VEC = [1:0]
 PORT processing_system7_0_S_AXI_HP1_AWLOCK_pin = processing_system7_0_S_AXI_HP1_AWLOCK, DIR = I, VEC = [1:0]
 PORT processing_system7_0_S_AXI_HP1_AWSIZE_pin = processing_system7_0_S_AXI_HP1_AWSIZE, DIR = I, VEC = [2:0]
 PORT processing_system7_0_S_AXI_HP1_ARPROT_pin = processing_system7_0_S_AXI_HP1_ARPROT, DIR = I, VEC = [2:0]
 PORT processing_system7_0_S_AXI_HP1_AWPROT_pin = processing_system7_0_S_AXI_HP1_AWPROT, DIR = I, VEC = [2:0]
 PORT processing_system7_0_S_AXI_HP1_ARADDR_pin = processing_system7_0_S_AXI_HP1_ARADDR, DIR = I, VEC = [31:0]
 PORT processing_system7_0_S_AXI_HP1_AWADDR_pin = processing_system7_0_S_AXI_HP1_AWADDR, DIR = I, VEC = [31:0]
 PORT processing_system7_0_S_AXI_HP1_ARCACHE_pin = processing_system7_0_S_AXI_HP1_ARCACHE, DIR = I, VEC = [3:0]
 PORT processing_system7_0_S_AXI_HP1_ARLEN_pin = processing_system7_0_S_AXI_HP1_ARLEN, DIR = I, VEC = [3:0]
 PORT processing_system7_0_S_AXI_HP1_ARQOS_pin = processing_system7_0_S_AXI_HP1_ARQOS, DIR = I, VEC = [3:0]
 PORT processing_system7_0_S_AXI_HP1_AWCACHE_pin = processing_system7_0_S_AXI_HP1_AWCACHE, DIR = I, VEC = [3:0]
 PORT processing_system7_0_S_AXI_HP1_AWLEN_pin = processing_system7_0_S_AXI_HP1_AWLEN, DIR = I, VEC = [3:0]
 PORT processing_system7_0_S_AXI_HP1_AWQOS_pin = processing_system7_0_S_AXI_HP1_AWQOS, DIR = I, VEC = [3:0]
 PORT processing_system7_0_S_AXI_HP1_ARID_pin = processing_system7_0_S_AXI_HP1_ARID, DIR = I, VEC = [5:0]
 PORT processing_system7_0_S_AXI_HP1_AWID_pin = processing_system7_0_S_AXI_HP1_AWID, DIR = I, VEC = [5:0]
 PORT processing_system7_0_S_AXI_HP1_WID_pin = processing_system7_0_S_AXI_HP1_WID, DIR = I, VEC = [5:0]
 PORT processing_system7_0_S_AXI_HP1_WDATA_pin = processing_system7_0_S_AXI_HP1_WDATA, DIR = I, VEC = [63:0]
 PORT processing_system7_0_S_AXI_HP1_WSTRB_pin = processing_system7_0_S_AXI_HP1_WSTRB, DIR = I, VEC = [7:0]
 PORT processing_system7_0_I2C0_SDA_pin = processing_system7_0_I2C0_SDA, DIR = IO
 PORT processing_system7_0_I2C0_SCL_pin = processing_system7_0_I2C0_SCL, DIR = IO
 PORT processing_system7_0_GPIO_I_pin = processing_system7_0_GPIO_I_0, DIR = I, VEC = [47:0]
 PORT processing_system7_0_GPIO_O_pin = processing_system7_0_GPIO_O, DIR = O, VEC = [47:0]
 PORT processing_system7_0_GPIO_T_pin = processing_system7_0_GPIO_T, DIR = O, VEC = [47:0]


BEGIN processing_system7
 PARAMETER INSTANCE = processing_system7_0
 PARAMETER HW_VER = 4.03.a
 PARAMETER C_DDR_RAM_HIGHADDR = 0x3FFFFFFF
 PARAMETER C_EN_EMIO_CAN0 = 0
 PARAMETER C_EN_EMIO_CAN1 = 0
 PARAMETER C_EN_EMIO_ENET0 = 0
 PARAMETER C_EN_EMIO_ENET1 = 0
 PARAMETER C_EN_EMIO_I2C0 = 1
 PARAMETER C_EN_EMIO_I2C1 = 0
 PARAMETER C_EN_EMIO_PJTAG = 0
 PARAMETER C_EN_EMIO_SDIO0 = 0
 PARAMETER C_EN_EMIO_CD_SDIO0 = 0
 PARAMETER C_EN_EMIO_WP_SDIO0 = 0
 PARAMETER C_EN_EMIO_SDIO1 = 0
 PARAMETER C_EN_EMIO_CD_SDIO1 = 0
 PARAMETER C_EN_EMIO_WP_SDIO1 = 0
 PARAMETER C_EN_EMIO_SPI0 = 0
 PARAMETER C_EN_EMIO_SPI1 = 0
 PARAMETER C_EN_EMIO_SRAM_INT = 0
 PARAMETER C_EN_EMIO_TRACE = 0
 PARAMETER C_EN_EMIO_TTC0 = 0
 PARAMETER C_EN_EMIO_TTC1 = 0
 PARAMETER C_EN_EMIO_UART0 = 0
 PARAMETER C_EN_EMIO_UART1 = 0
 PARAMETER C_EN_EMIO_MODEM_UART0 = 0
 PARAMETER C_EN_EMIO_MODEM_UART1 = 0
 PARAMETER C_EN_EMIO_WDT = 0
 PARAMETER C_EN_EMIO_GPIO = 1
 PARAMETER C_EMIO_GPIO_WIDTH = 48
 PARAMETER C_EN_QSPI = 1
 PARAMETER C_EN_SMC = 0
 PARAMETER C_EN_CAN0 = 0
 PARAMETER C_EN_CAN1 = 0
 PARAMETER C_EN_ENET0 = 1
 PARAMETER C_EN_ENET1 = 0
 PARAMETER C_EN_I2C0 = 1
 PARAMETER C_EN_I2C1 = 0
 PARAMETER C_EN_PJTAG = 0
 PARAMETER C_EN_SDIO0 = 0
 PARAMETER C_EN_SDIO1 = 1
 PARAMETER C_EN_SPI0 = 0
 PARAMETER C_EN_SPI1 = 0
 PARAMETER C_EN_TRACE = 0
 PARAMETER C_EN_TTC0 = 0
 PARAMETER C_EN_TTC1 = 0
 PARAMETER C_EN_UART0 = 0
 PARAMETER C_EN_UART1 = 1
 PARAMETER C_EN_MODEM_UART0 = 0
 PARAMETER C_EN_MODEM_UART1 = 0
 PARAMETER C_EN_USB0 = 1
 PARAMETER C_EN_USB1 = 1
 PARAMETER C_EN_WDT = 0
 PARAMETER C_EN_DDR = 1
 PARAMETER C_EN_GPIO = 1
 PARAMETER C_FCLK_CLK0_FREQ = 100000000
 PARAMETER C_FCLK_CLK1_FREQ = 200000000
 PARAMETER C_FCLK_CLK2_FREQ = 200000000
 PARAMETER C_FCLK_CLK3_FREQ = 40000000
 PARAMETER C_USE_M_AXI_GP1 = 1
 PARAMETER C_USE_S_AXI_HP1 = 1
 PORT MIO = processing_system7_0_MIO
 PORT PS_SRSTB = processing_system7_0_PS_SRSTB
 PORT PS_CLK = processing_system7_0_PS_CLK
 PORT PS_PORB = processing_system7_0_PS_PORB
 PORT DDR_Clk = processing_system7_0_DDR_Clk
 PORT DDR_Clk_n = processing_system7_0_DDR_Clk_n
 PORT DDR_CKE = processing_system7_0_DDR_CKE
 PORT DDR_CS_n = processing_system7_0_DDR_CS_n
 PORT DDR_RAS_n = processing_system7_0_DDR_RAS_n
 PORT DDR_CAS_n = processing_system7_0_DDR_CAS_n
 PORT DDR_WEB = processing_system7_0_DDR_WEB
 PORT DDR_BankAddr = processing_system7_0_DDR_BankAddr
 PORT DDR_Addr = processing_system7_0_DDR_Addr
 PORT DDR_ODT = processing_system7_0_DDR_ODT
 PORT DDR_DRSTB = processing_system7_0_DDR_DRSTB
 PORT DDR_DQ = processing_system7_0_DDR_DQ
 PORT DDR_DM = processing_system7_0_DDR_DM
 PORT DDR_DQS = processing_system7_0_DDR_DQS
 PORT DDR_DQS_n = processing_system7_0_DDR_DQS_n
 PORT DDR_VRN = processing_system7_0_DDR_VRN
 PORT DDR_VRP = processing_system7_0_DDR_VRP
 PORT M_AXI_GP1_ARESETN = processing_system7_0_M_AXI_GP1_ARESETN
 PORT S_AXI_HP1_ARESETN = processing_system7_0_S_AXI_HP1_ARESETN
 PORT FCLK_CLK3 = processing_system7_0_FCLK_CLK3
 PORT FCLK_CLK0 = processing_system7_0_FCLK_CLK0
 PORT M_AXI_GP1_ARVALID = processing_system7_0_M_AXI_GP1_ARVALID
 PORT M_AXI_GP1_AWVALID = processing_system7_0_M_AXI_GP1_AWVALID
 PORT M_AXI_GP1_BREADY = processing_system7_0_M_AXI_GP1_BREADY
 PORT M_AXI_GP1_RREADY = processing_system7_0_M_AXI_GP1_RREADY
 PORT M_AXI_GP1_WLAST = processing_system7_0_M_AXI_GP1_WLAST
 PORT M_AXI_GP1_WVALID = processing_system7_0_M_AXI_GP1_WVALID
 PORT M_AXI_GP1_ARID = processing_system7_0_M_AXI_GP1_ARID
 PORT M_AXI_GP1_AWID = processing_system7_0_M_AXI_GP1_AWID
 PORT M_AXI_GP1_WID = processing_system7_0_M_AXI_GP1_WID
 PORT M_AXI_GP1_ARBURST = processing_system7_0_M_AXI_GP1_ARBURST
 PORT M_AXI_GP1_ARLOCK = processing_system7_0_M_AXI_GP1_ARLOCK
 PORT M_AXI_GP1_ARSIZE = processing_system7_0_M_AXI_GP1_ARSIZE
 PORT M_AXI_GP1_AWBURST = processing_system7_0_M_AXI_GP1_AWBURST
 PORT M_AXI_GP1_AWLOCK = processing_system7_0_M_AXI_GP1_AWLOCK
 PORT M_AXI_GP1_AWSIZE = processing_system7_0_M_AXI_GP1_AWSIZE
 PORT M_AXI_GP1_ARPROT = processing_system7_0_M_AXI_GP1_ARPROT
 PORT M_AXI_GP1_AWPROT = processing_system7_0_M_AXI_GP1_AWPROT
 PORT M_AXI_GP1_ARADDR = processing_system7_0_M_AXI_GP1_ARADDR
 PORT M_AXI_GP1_AWADDR = processing_system7_0_M_AXI_GP1_AWADDR
 PORT M_AXI_GP1_WDATA = processing_system7_0_M_AXI_GP1_WDATA
 PORT M_AXI_GP1_ARCACHE = processing_system7_0_M_AXI_GP1_ARCACHE
 PORT M_AXI_GP1_ARLEN = processing_system7_0_M_AXI_GP1_ARLEN
 PORT M_AXI_GP1_ARQOS = processing_system7_0_M_AXI_GP1_ARQOS
 PORT M_AXI_GP1_AWCACHE = processing_system7_0_M_AXI_GP1_AWCACHE
 PORT M_AXI_GP1_AWLEN = processing_system7_0_M_AXI_GP1_AWLEN
 PORT M_AXI_GP1_AWQOS = processing_system7_0_M_AXI_GP1_AWQOS
 PORT M_AXI_GP1_WSTRB = processing_system7_0_M_AXI_GP1_WSTRB
 PORT M_AXI_GP1_ACLK = processing_system7_0_M_AXI_GP1_ACLK
 PORT M_AXI_GP1_ARREADY = processing_system7_0_M_AXI_GP1_ARREADY
 PORT M_AXI_GP1_AWREADY = processing_system7_0_M_AXI_GP1_AWREADY
 PORT M_AXI_GP1_BVALID = processing_system7_0_M_AXI_GP1_BVALID
 PORT M_AXI_GP1_RLAST = processing_system7_0_M_AXI_GP1_RLAST
 PORT M_AXI_GP1_RVALID = processing_system7_0_M_AXI_GP1_RVALID
 PORT M_AXI_GP1_WREADY = processing_system7_0_M_AXI_GP1_WREADY
 PORT M_AXI_GP1_BID = processing_system7_0_M_AXI_GP1_BID
 PORT M_AXI_GP1_RID = processing_system7_0_M_AXI_GP1_RID
 PORT M_AXI_GP1_BRESP = processing_system7_0_M_AXI_GP1_BRESP
 PORT M_AXI_GP1_RRESP = processing_system7_0_M_AXI_GP1_RRESP
 PORT M_AXI_GP1_RDATA = processing_system7_0_M_AXI_GP1_RDATA
 PORT S_AXI_HP1_ARREADY = processing_system7_0_S_AXI_HP1_ARREADY
 PORT S_AXI_HP1_AWREADY = processing_system7_0_S_AXI_HP1_AWREADY
 PORT S_AXI_HP1_BVALID = processing_system7_0_S_AXI_HP1_BVALID
 PORT S_AXI_HP1_RLAST = processing_system7_0_S_AXI_HP1_RLAST
 PORT S_AXI_HP1_RVALID = processing_system7_0_S_AXI_HP1_RVALID
 PORT S_AXI_HP1_WREADY = processing_system7_0_S_AXI_HP1_WREADY
 PORT S_AXI_HP1_BRESP = processing_system7_0_S_AXI_HP1_BRESP
 PORT S_AXI_HP1_RRESP = processing_system7_0_S_AXI_HP1_RRESP
 PORT S_AXI_HP1_BID = processing_system7_0_S_AXI_HP1_BID
 PORT S_AXI_HP1_RID = processing_system7_0_S_AXI_HP1_RID
 PORT S_AXI_HP1_RDATA = processing_system7_0_S_AXI_HP1_RDATA
 PORT S_AXI_HP1_ACLK = processing_system7_0_S_AXI_HP1_ACLK
 PORT S_AXI_HP1_ARVALID = processing_system7_0_S_AXI_HP1_ARVALID
 PORT S_AXI_HP1_AWVALID = processing_system7_0_S_AXI_HP1_AWVALID
 PORT S_AXI_HP1_BREADY = processing_system7_0_S_AXI_HP1_BREADY
 PORT S_AXI_HP1_RREADY = processing_system7_0_S_AXI_HP1_RREADY
 PORT S_AXI_HP1_WLAST = processing_system7_0_S_AXI_HP1_WLAST
 PORT S_AXI_HP1_WVALID = processing_system7_0_S_AXI_HP1_WVALID
 PORT S_AXI_HP1_ARBURST = processing_system7_0_S_AXI_HP1_ARBURST
 PORT S_AXI_HP1_ARLOCK = processing_system7_0_S_AXI_HP1_ARLOCK
 PORT S_AXI_HP1_ARSIZE = processing_system7_0_S_AXI_HP1_ARSIZE
 PORT S_AXI_HP1_AWBURST = processing_system7_0_S_AXI_HP1_AWBURST
 PORT S_AXI_HP1_AWLOCK = processing_system7_0_S_AXI_HP1_AWLOCK
 PORT S_AXI_HP1_AWSIZE = processing_system7_0_S_AXI_HP1_AWSIZE
 PORT S_AXI_HP1_ARPROT = processing_system7_0_S_AXI_HP1_ARPROT
 PORT S_AXI_HP1_AWPROT = processing_system7_0_S_AXI_HP1_AWPROT
 PORT S_AXI_HP1_ARADDR = processing_system7_0_S_AXI_HP1_ARADDR
 PORT S_AXI_HP1_AWADDR = processing_system7_0_S_AXI_HP1_AWADDR
 PORT S_AXI_HP1_ARCACHE = processing_system7_0_S_AXI_HP1_ARCACHE
 PORT S_AXI_HP1_ARLEN = processing_system7_0_S_AXI_HP1_ARLEN
 PORT S_AXI_HP1_ARQOS = processing_system7_0_S_AXI_HP1_ARQOS
 PORT S_AXI_HP1_AWCACHE = processing_system7_0_S_AXI_HP1_AWCACHE
 PORT S_AXI_HP1_AWLEN = processing_system7_0_S_AXI_HP1_AWLEN
 PORT S_AXI_HP1_AWQOS = processing_system7_0_S_AXI_HP1_AWQOS
 PORT S_AXI_HP1_ARID = processing_system7_0_S_AXI_HP1_ARID
 PORT S_AXI_HP1_AWID = processing_system7_0_S_AXI_HP1_AWID
 PORT S_AXI_HP1_WID = processing_system7_0_S_AXI_HP1_WID
 PORT S_AXI_HP1_WDATA = processing_system7_0_S_AXI_HP1_WDATA
 PORT S_AXI_HP1_WSTRB = processing_system7_0_S_AXI_HP1_WSTRB
 PORT I2C0_SDA = processing_system7_0_I2C0_SDA
 PORT I2C0_SCL = processing_system7_0_I2C0_SCL
 PORT GPIO_I = processing_system7_0_GPIO_I_0
 PORT GPIO_O = processing_system7_0_GPIO_O
 PORT GPIO_T = processing_system7_0_GPIO_T
END