mirror of
https://github.com/parallella/parallella-hw.git
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168 lines
5.6 KiB
Verilog
168 lines
5.6 KiB
Verilog
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`timescale 1 ns / 1 ps
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module emaxi_v1_0 #
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(
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// Users to add parameters here
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// User parameters ends
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// Do not modify the parameters beyond this line
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// Parameters of Axi Master Bus Interface M00_AXI
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parameter C_M00_AXI_TARGET_SLAVE_BASE_ADDR = 32'h40000000,
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parameter integer C_M00_AXI_BURST_LEN = 16,
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parameter integer C_M00_AXI_ID_WIDTH = 1,
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parameter integer C_M00_AXI_ADDR_WIDTH = 32,
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parameter integer C_M00_AXI_DATA_WIDTH = 64,
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parameter integer C_M00_AXI_AWUSER_WIDTH = 0,
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parameter integer C_M00_AXI_ARUSER_WIDTH = 0,
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parameter integer C_M00_AXI_WUSER_WIDTH = 0,
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parameter integer C_M00_AXI_RUSER_WIDTH = 0,
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parameter integer C_M00_AXI_BUSER_WIDTH = 0
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)
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(
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// Users to add ports here
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// FIFO read-master port, writes from RX channel
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input wire [102:0] emwr_rd_data,
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output wire emwr_rd_en,
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input wire emwr_empty,
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// FIFO read-master port, read requests from RX channel
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input wire [102:0] emrq_rd_data,
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output wire emrq_rd_en,
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input wire emrq_empty,
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// FIFO write-master port, read responses to TX channel
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output wire [102:0] emrr_wr_data,
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output wire emrr_wr_en,
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input wire emrr_full,
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input wire emrr_prog_full,
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// User ports ends
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// Do not modify the ports beyond this line
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// Ports of Axi Master Bus Interface M00_AXI
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input wire m00_axi_aclk,
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input wire m00_axi_aresetn,
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output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_awid,
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output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_awaddr,
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output wire [7 : 0] m00_axi_awlen,
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output wire [2 : 0] m00_axi_awsize,
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output wire [1 : 0] m00_axi_awburst,
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output wire m00_axi_awlock,
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output wire [3 : 0] m00_axi_awcache,
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output wire [2 : 0] m00_axi_awprot,
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output wire [3 : 0] m00_axi_awqos,
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output wire [C_M00_AXI_AWUSER_WIDTH-1 : 0] m00_axi_awuser,
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output wire m00_axi_awvalid,
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input wire m00_axi_awready,
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output wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_wdata,
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output wire [C_M00_AXI_DATA_WIDTH/8-1 : 0] m00_axi_wstrb,
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output wire m00_axi_wlast,
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output wire [C_M00_AXI_WUSER_WIDTH-1 : 0] m00_axi_wuser,
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output wire m00_axi_wvalid,
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input wire m00_axi_wready,
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input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_bid,
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input wire [1 : 0] m00_axi_bresp,
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input wire [C_M00_AXI_BUSER_WIDTH-1 : 0] m00_axi_buser,
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input wire m00_axi_bvalid,
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output wire m00_axi_bready,
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output wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_arid,
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output wire [C_M00_AXI_ADDR_WIDTH-1 : 0] m00_axi_araddr,
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output wire [7 : 0] m00_axi_arlen,
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output wire [2 : 0] m00_axi_arsize,
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output wire [1 : 0] m00_axi_arburst,
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output wire m00_axi_arlock,
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output wire [3 : 0] m00_axi_arcache,
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output wire [2 : 0] m00_axi_arprot,
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output wire [3 : 0] m00_axi_arqos,
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output wire [C_M00_AXI_ARUSER_WIDTH-1 : 0] m00_axi_aruser,
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output wire m00_axi_arvalid,
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input wire m00_axi_arready,
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input wire [C_M00_AXI_ID_WIDTH-1 : 0] m00_axi_rid,
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input wire [C_M00_AXI_DATA_WIDTH-1 : 0] m00_axi_rdata,
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input wire [1 : 0] m00_axi_rresp,
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input wire m00_axi_rlast,
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input wire [C_M00_AXI_RUSER_WIDTH-1 : 0] m00_axi_ruser,
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input wire m00_axi_rvalid,
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output wire m00_axi_rready
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);
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// Instantiation of Axi Bus Interface M00_AXI
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emaxi_v1_0_M00_AXI # (
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.C_M_TARGET_SLAVE_BASE_ADDR(C_M00_AXI_TARGET_SLAVE_BASE_ADDR),
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.C_M_AXI_BURST_LEN(C_M00_AXI_BURST_LEN),
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.C_M_AXI_ID_WIDTH(C_M00_AXI_ID_WIDTH),
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.C_M_AXI_ADDR_WIDTH(C_M00_AXI_ADDR_WIDTH),
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.C_M_AXI_DATA_WIDTH(C_M00_AXI_DATA_WIDTH),
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.C_M_AXI_AWUSER_WIDTH(C_M00_AXI_AWUSER_WIDTH),
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.C_M_AXI_ARUSER_WIDTH(C_M00_AXI_ARUSER_WIDTH),
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.C_M_AXI_WUSER_WIDTH(C_M00_AXI_WUSER_WIDTH),
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.C_M_AXI_RUSER_WIDTH(C_M00_AXI_RUSER_WIDTH),
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.C_M_AXI_BUSER_WIDTH(C_M00_AXI_BUSER_WIDTH)
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) emaxi_v1_0_M00_AXI_inst (
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.emwr_rd_data(emwr_rd_data),
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.emwr_rd_en(emwr_rd_en),
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.emwr_empty(emwr_empty),
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.emrq_rd_data(emrq_rd_data),
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.emrq_rd_en(emrq_rd_en),
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.emrq_empty(emrq_empty),
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.emrr_wr_data(emrr_wr_data),
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.emrr_wr_en(emrr_wr_en),
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.emrr_full(emrr_full),
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.emrr_prog_full(emrr_prog_full),
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.M_AXI_ACLK(m00_axi_aclk),
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.M_AXI_ARESETN(m00_axi_aresetn),
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.M_AXI_AWID(m00_axi_awid),
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.M_AXI_AWADDR(m00_axi_awaddr),
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.M_AXI_AWLEN(m00_axi_awlen),
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.M_AXI_AWSIZE(m00_axi_awsize),
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.M_AXI_AWBURST(m00_axi_awburst),
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.M_AXI_AWLOCK(m00_axi_awlock),
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.M_AXI_AWCACHE(m00_axi_awcache),
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.M_AXI_AWPROT(m00_axi_awprot),
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.M_AXI_AWQOS(m00_axi_awqos),
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.M_AXI_AWUSER(m00_axi_awuser),
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.M_AXI_AWVALID(m00_axi_awvalid),
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.M_AXI_AWREADY(m00_axi_awready),
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.M_AXI_WDATA(m00_axi_wdata),
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.M_AXI_WSTRB(m00_axi_wstrb),
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.M_AXI_WLAST(m00_axi_wlast),
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.M_AXI_WUSER(m00_axi_wuser),
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.M_AXI_WVALID(m00_axi_wvalid),
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.M_AXI_WREADY(m00_axi_wready),
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.M_AXI_BID(m00_axi_bid),
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.M_AXI_BRESP(m00_axi_bresp),
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.M_AXI_BUSER(m00_axi_buser),
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.M_AXI_BVALID(m00_axi_bvalid),
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.M_AXI_BREADY(m00_axi_bready),
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.M_AXI_ARID(m00_axi_arid),
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.M_AXI_ARADDR(m00_axi_araddr),
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.M_AXI_ARLEN(m00_axi_arlen),
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.M_AXI_ARSIZE(m00_axi_arsize),
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.M_AXI_ARBURST(m00_axi_arburst),
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.M_AXI_ARLOCK(m00_axi_arlock),
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.M_AXI_ARCACHE(m00_axi_arcache),
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.M_AXI_ARPROT(m00_axi_arprot),
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.M_AXI_ARQOS(m00_axi_arqos),
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.M_AXI_ARUSER(m00_axi_aruser),
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.M_AXI_ARVALID(m00_axi_arvalid),
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.M_AXI_ARREADY(m00_axi_arready),
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.M_AXI_RID(m00_axi_rid),
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.M_AXI_RDATA(m00_axi_rdata),
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.M_AXI_RRESP(m00_axi_rresp),
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.M_AXI_RLAST(m00_axi_rlast),
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.M_AXI_RUSER(m00_axi_ruser),
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.M_AXI_RVALID(m00_axi_rvalid),
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.M_AXI_RREADY(m00_axi_rready)
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);
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// Add user logic here
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// User logic ends
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endmodule
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