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108 lines
3.5 KiB
Verilog
108 lines
3.5 KiB
Verilog
/*
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File: emesh_split.v
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This file is part of the Parallella Project.
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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/*
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########################################################################
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EPIPHANY eMesh Splitter
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########################################################################
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This block takes one eMesh input (104-bit transactions) and
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copies it to two outputs. The wait signals are taken only from the
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first slave port.
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This block will hopefully be removed once I figure out how to get
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Vivado to allow multiple slaves on one interface!
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*/
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module emesh_split (/*AUTOARG*/
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// Outputs
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ems_rd_wait, ems_wr_wait, emm0_access, emm0_write, emm0_datamode,
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emm0_ctrlmode, emm0_dstaddr, emm0_srcaddr, emm0_data, emm1_access,
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emm1_write, emm1_datamode, emm1_ctrlmode, emm1_dstaddr,
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emm1_srcaddr, emm1_data,
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// Inputs
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ems_access, ems_write, ems_datamode, ems_ctrlmode, ems_dstaddr,
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ems_srcaddr, ems_data, emm0_rd_wait, emm0_wr_wait
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);
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// Slave port
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input ems_access;
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input ems_write;
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input [1:0] ems_datamode;
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input [3:0] ems_ctrlmode;
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input [31:0] ems_dstaddr;
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input [31:0] ems_srcaddr;
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input [31:0] ems_data;
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output ems_rd_wait;
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output ems_wr_wait;
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// Master port #0 (with wait inputs)
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output emm0_access;
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output emm0_write;
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output [1:0] emm0_datamode;
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output [3:0] emm0_ctrlmode;
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output [31:0] emm0_dstaddr;
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output [31:0] emm0_srcaddr;
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output [31:0] emm0_data;
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input emm0_rd_wait;
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input emm0_wr_wait;
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// Master port #1 (NO wait inputs)
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output emm1_access;
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output emm1_write;
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output [1:0] emm1_datamode;
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output [3:0] emm1_ctrlmode;
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output [31:0] emm1_dstaddr;
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output [31:0] emm1_srcaddr;
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output [31:0] emm1_data;
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//############
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//# Duplicate all slave->master signals
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//############
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wire emm0_access = ems_access;
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wire emm0_write = ems_write;
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wire [1:0] emm0_datamode = ems_datamode;
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wire [3:0] emm0_ctrlmode = ems_ctrlmode;
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wire [31:0] emm0_dstaddr = ems_dstaddr;
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wire [31:0] emm0_srcaddr = ems_srcaddr;
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wire [31:0] emm0_data = ems_data;
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// Master port #1 (NO wait inputs)
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wire emm1_access = ems_access;
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wire emm1_write = ems_write;
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wire [1:0] emm1_datamode = ems_datamode;
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wire [3:0] emm1_ctrlmode = ems_ctrlmode;
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wire [31:0] emm1_dstaddr = ems_dstaddr;
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wire [31:0] emm1_srcaddr = ems_srcaddr;
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wire [31:0] emm1_data = ems_data;
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//#############################
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//# Wait signal passthroughs, port 0 only
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//#############################
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wire ems_rd_wait = emm0_rd_wait;
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wire ems_wr_wait = emm0_wr_wait;
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endmodule // emesh_split
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