mirror of
https://github.com/parallella/parallella-hw.git
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156 lines
3.9 KiB
Verilog
156 lines
3.9 KiB
Verilog
//`timescale 1 ns / 100 ps
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module dv_emon();
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parameter DW = 32;
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//Stimulus to drive
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reg clk;
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reg reset;
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reg mi_access;
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reg [19:0] mi_addr;
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reg [31:0] mi_data_in;
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reg mi_write;
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reg [1:0] test_state;
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reg go;
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reg erx_rdfifo_access; // To emon of emon.v
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reg erx_rdfifo_wait; // To emon of emon.v
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reg erx_wbfifo_access; // To emon of emon.v
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reg erx_wbfifo_wait; // To emon of emon.v
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reg erx_wrfifo_access; // To emon of emon.v
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reg erx_wrfifo_wait; // To emon of emon.v
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reg etx_rdfifo_access; // To emon of emon.v
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reg etx_rdfifo_wait; // To emon of emon.v
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reg etx_wbfifo_access; // To emon of emon.v
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reg etx_wbfifo_wait; // To emon of emon.v
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reg etx_wrfifo_access; // To emon of emon.v
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reg etx_wrfifo_wait; // To emon of emon.v
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//Reset
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initial
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begin
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$display($time, " << Starting the Simulation >>");
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#0
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clk = 1'b0; // at time 0
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reset = 1'b1; // reset is active
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mi_write = 1'b0;
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mi_access = 1'b0;
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mi_addr[19:0] = 20'h0;
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mi_data_in[31:0] = 32'h0;
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test_state[1:0] = 2'b00;
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go = 1'b0;
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erx_rdfifo_access = 1'b1;
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erx_rdfifo_wait = 1'b1;
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erx_wbfifo_access = 1'b1;
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erx_wbfifo_wait = 1'b1;
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erx_wrfifo_access = 1'b1;
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erx_wrfifo_wait = 1'b1;
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etx_rdfifo_access = 1'b1;
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etx_rdfifo_wait = 1'b1;
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etx_wbfifo_access = 1'b1;
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etx_wbfifo_wait = 1'b1;
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etx_wrfifo_access = 1'b1;
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etx_wrfifo_wait = 1'b1;
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#100
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reset = 1'b0; // at time 100 release reset
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#100
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go = 1'b1;
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#10000
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$finish;
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end
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//Clock
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always
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#10 clk = ~clk;
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//Pattern generator
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//1.) Write in 8 transactions (split into low and high)
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//2.) Read back 8 transactions (split into low and high)
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always @ (negedge clk)
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if(go)
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begin
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case(test_state[1:0])
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2'b00://write
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if(~done)
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begin
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mi_access <= 1'b1;
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mi_write <= 1'b1;
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mi_addr[19:0] <= 20'hf036c;
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mi_data_in[31:0] <= 32'h8_7_6_5_4_3_2_1;
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test_state <= 2'b01;
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end
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2'b01://read
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if(~done)
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begin
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mi_write <= 1'b0;
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mi_access <= 1'b1;
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mi_addr[19:0] <= mi_addr[19:0]+20'h4;
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mi_data_in[31:0] <= mi_data_in[31:0]-4'h8;
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end
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else
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begin
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test_state <= 2'b10;
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mi_write <= 1'b0;
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end // else: !if(~done)
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2'b10://init array
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begin
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mi_addr[19:0] <= mi_addr[19:0]-20'h4;
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end
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endcase // case (test_state[1:0])
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end
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wire done = (mi_addr[19:0]==6'b001101);
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire [5:0] emon_zero_flag; // From emon of emon.v
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wire [DW-1:0] mi_data_out; // From emon of emon.v
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// End of automatics
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/*AUTOWIRE*/
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//DUT
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emon emon(
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/*AUTOINST*/
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// Outputs
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.mi_data_out (mi_data_out[DW-1:0]),
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.emon_zero_flag (emon_zero_flag[5:0]),
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// Inputs
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.clk (clk),
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.reset (reset),
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.mi_access (mi_access),
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.mi_write (mi_write),
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.mi_addr (mi_addr[19:0]),
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.mi_data_in (mi_data_in[DW-1:0]),
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.erx_rdfifo_access (erx_rdfifo_access),
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.erx_rdfifo_wait (erx_rdfifo_wait),
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.erx_wrfifo_access (erx_wrfifo_access),
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.erx_wrfifo_wait (erx_wrfifo_wait),
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.erx_wbfifo_access (erx_wbfifo_access),
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.erx_wbfifo_wait (erx_wbfifo_wait),
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.etx_rdfifo_access (etx_rdfifo_access),
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.etx_rdfifo_wait (etx_rdfifo_wait),
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.etx_wrfifo_access (etx_wrfifo_access),
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.etx_wrfifo_wait (etx_wrfifo_wait),
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.etx_wbfifo_access (etx_wbfifo_access),
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.etx_wbfifo_wait (etx_wbfifo_wait));
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//Waveform dump
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initial
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begin
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$dumpfile("test.vcd");
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$dumpvars(0, dv_emon);
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end
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endmodule // dv_emon
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// Local Variables:
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// verilog-library-directories:("." "../hdl" "../../memory/hdl ")
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// End:
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