mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-24 03:34:40 +00:00
473 lines
20 KiB
XML
473 lines
20 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
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<spirit:vendor>adapteva.com</spirit:vendor>
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<spirit:library>Adatpeva</spirit:library>
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<spirit:name>eproto_tx</spirit:name>
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<spirit:version>1.0</spirit:version>
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<spirit:busInterfaces>
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<spirit:busInterface>
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<spirit:name>signal_reset</spirit:name>
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<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>RST</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>reset</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>POLARITY</spirit:name>
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<spirit:value spirit:format="string" spirit:resolve="immediate" spirit:id="BUSIFPARAM_VALUE.SIGNAL_RESET.POLARITY" spirit:choiceRef="choices_0">ACTIVE_HIGH</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:busInterface>
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<spirit:busInterface>
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<spirit:name>emtx</spirit:name>
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<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh" spirit:version="1.0"/>
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<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eMesh_rtl" spirit:version="1.0"/>
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<spirit:slave/>
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<spirit:portMaps>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>srcaddr</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emtx_srcaddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>access</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emtx_access</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>datamode</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emtx_datamode</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>data</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emtx_data</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>wr_wait</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emtx_wr_wait</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>ctrlmode</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emtx_ctrlmode</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>dstaddr</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emtx_dstaddr</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>write</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emtx_write</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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<spirit:portMap>
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<spirit:logicalPort>
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<spirit:name>rd_wait</spirit:name>
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</spirit:logicalPort>
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<spirit:physicalPort>
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<spirit:name>emtx_rd_wait</spirit:name>
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</spirit:physicalPort>
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</spirit:portMap>
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</spirit:portMaps>
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</spirit:busInterface>
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</spirit:busInterfaces>
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<spirit:model>
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<spirit:views>
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<spirit:view>
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<spirit:name>xilinx_verilogsynthesis</spirit:name>
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<spirit:displayName>Verilog Synthesis</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>eproto_tx</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>6b919726</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
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<spirit:displayName>Verilog Simulation</spirit:displayName>
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<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
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<spirit:language>verilog</spirit:language>
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<spirit:modelName>eproto_tx</spirit:modelName>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>6b919726</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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<spirit:view>
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<spirit:name>xilinx_xpgui</spirit:name>
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<spirit:displayName>UI Layout</spirit:displayName>
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<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
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<spirit:fileSetRef>
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<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
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</spirit:fileSetRef>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>viewChecksum</spirit:name>
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<spirit:value>e65e5adf</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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</spirit:view>
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</spirit:views>
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<spirit:ports>
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<spirit:port>
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<spirit:name>emtx_rd_wait</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>reg</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emtx_wr_wait</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>reg</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emtx_ack</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>reg</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>txframe_p</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">7</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>reg</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>txdata_p</spirit:name>
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<spirit:wire>
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<spirit:direction>out</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">63</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>reg</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>reset</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emtx_access</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emtx_write</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emtx_datamode</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">1</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emtx_ctrlmode</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emtx_dstaddr</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emtx_srcaddr</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>emtx_data</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:vector>
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<spirit:left spirit:format="long" spirit:resolve="immediate">31</spirit:left>
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<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
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</spirit:vector>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic_vector</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>txlclk_p</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>tx_rd_wait</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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<spirit:port>
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<spirit:name>tx_wr_wait</spirit:name>
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<spirit:wire>
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<spirit:direction>in</spirit:direction>
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<spirit:wireTypeDefs>
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<spirit:wireTypeDef>
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<spirit:typeName>std_logic</spirit:typeName>
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<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
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<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
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</spirit:wireTypeDef>
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</spirit:wireTypeDefs>
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</spirit:wire>
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</spirit:port>
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</spirit:ports>
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</spirit:model>
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<spirit:choices>
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<spirit:choice>
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<spirit:name>choices_0</spirit:name>
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<spirit:enumeration>ACTIVE_HIGH</spirit:enumeration>
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<spirit:enumeration>ACTIVE_LOW</spirit:enumeration>
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</spirit:choice>
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</spirit:choices>
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<spirit:fileSets>
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<spirit:fileSet>
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<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>hdl/eproto_tx.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
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<spirit:userFileType>CHECKSUM_046587b3</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>hdl/eproto_tx.v</spirit:name>
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<spirit:fileType>verilogSource</spirit:fileType>
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<spirit:userFileType>IMPORTED_FILE</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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<spirit:fileSet>
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<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
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<spirit:file>
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<spirit:name>xgui/eproto_tx_v1_0.tcl</spirit:name>
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<spirit:fileType>tclSource</spirit:fileType>
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<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
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<spirit:userFileType>CHECKSUM_e65e5adf</spirit:userFileType>
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</spirit:file>
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</spirit:fileSet>
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</spirit:fileSets>
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<spirit:description>eLink TX Protocol Generator</spirit:description>
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<spirit:parameters>
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<spirit:parameter>
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<spirit:name>Component_Name</spirit:name>
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<spirit:displayName>Component Name</spirit:displayName>
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<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">eproto_tx_v1_0</spirit:value>
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</spirit:parameter>
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</spirit:parameters>
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<spirit:vendorExtensions>
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<xilinx:coreExtensions>
|
|
<xilinx:supportedFamilies>
|
|
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
|
|
</xilinx:supportedFamilies>
|
|
<xilinx:taxonomies>
|
|
<xilinx:taxonomy>/BaseIP</xilinx:taxonomy>
|
|
</xilinx:taxonomies>
|
|
<xilinx:displayName>eproto_tx_v1_0</xilinx:displayName>
|
|
<xilinx:vendorDisplayName>Adapteva, Inc.</xilinx:vendorDisplayName>
|
|
<xilinx:vendorURL>http://www.adapteva.com</xilinx:vendorURL>
|
|
<xilinx:coreRevision>4</xilinx:coreRevision>
|
|
<xilinx:upgrades>
|
|
<xilinx:canUpgradeFrom>user.org:user:eproto_tx:1.0</xilinx:canUpgradeFrom>
|
|
</xilinx:upgrades>
|
|
<xilinx:coreCreationDateTime>2014-11-20T19:17:25Z</xilinx:coreCreationDateTime>
|
|
<xilinx:tags>
|
|
<xilinx:tag xilinx:name="user.org:user:eproto_tx:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eproto_tx/ip</xilinx:tag>
|
|
<xilinx:tag xilinx:name="adapteva.com:user:eproto_tx:1.0_ARCHIVE_LOCATION">/mnt/windowsC/Adapteva/Parallella/parallella-hwelink/fpga/src/eproto_tx/ip</xilinx:tag>
|
|
<xilinx:tag xilinx:name="adapteva.com:Adatpeva:eproto_tx:1.0_ARCHIVE_LOCATION">/home/frhuettig</xilinx:tag>
|
|
</xilinx:tags>
|
|
</xilinx:coreExtensions>
|
|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2014.3</xilinx:xilinxVersion>
|
|
<xilinx:checksum xilinx:scope="busInterfaces" xilinx:value="b3ee788f"/>
|
|
<xilinx:checksum xilinx:scope="fileGroups" xilinx:value="b31d678a"/>
|
|
<xilinx:checksum xilinx:scope="ports" xilinx:value="88ac7c75"/>
|
|
<xilinx:checksum xilinx:scope="parameters" xilinx:value="d0bdb522"/>
|
|
</xilinx:packagingInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:component>
|