mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-24 03:34:40 +00:00
1926 lines
86 KiB
XML
1926 lines
86 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
|
|
<spirit:component xmlns:xilinx="http://www.xilinx.com" xmlns:spirit="http://www.spiritconsortium.org/XMLSchema/SPIRIT/1685-2009" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance">
|
|
<spirit:vendor>adapteva.com</spirit:vendor>
|
|
<spirit:library>Adapteva</spirit:library>
|
|
<spirit:name>esaxi</spirit:name>
|
|
<spirit:version>1.0</spirit:version>
|
|
<spirit:busInterfaces>
|
|
<spirit:busInterface>
|
|
<spirit:name>S00_AXI</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="aximm_rtl" spirit:version="1.0"/>
|
|
<spirit:slave>
|
|
<spirit:memoryMapRef spirit:memoryMapRef="S00_AXI"/>
|
|
</spirit:slave>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awaddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWLOCK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWCACHE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awcache</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWREGION</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awregion</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWQOS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awqos</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>AWREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_awready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_wdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WSTRB</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_wstrb</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_wlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_wuser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_wvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_wready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_bid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_bresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_buser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_bvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>BREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_bready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARADDR</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_araddr</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLEN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arlen</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARSIZE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arsize</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARBURST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arburst</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARLOCK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arlock</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARCACHE</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arcache</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARPROT</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arprot</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARREGION</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arregion</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARQOS</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arqos</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_aruser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>ARREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_arready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_rid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RDATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_rdata</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RRESP</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_rresp</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RLAST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_rlast</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RUSER</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_ruser</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RVALID</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_rvalid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RREADY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_rready</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>WIZ.DATA_WIDTH</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ.DATA_WIDTH" spirit:choiceRef="choices_0">32</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>WIZ.MEMORY_SIZE</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.WIZ.MEMORY_SIZE" spirit:choiceRef="choices_1">64</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>SUPPORTS_NARROW_BURST</spirit:name>
|
|
<spirit:value spirit:format="long" spirit:id="BUSIFPARAM_VALUE.S00_AXI.SUPPORTS_NARROW_BURST" spirit:choiceRef="choices_2">0</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>S00_AXI_RST</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="reset_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RST</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_aresetn</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>POLARITY</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_RST.POLARITY">ACTIVE_LOW</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>S00_AXI_CLK</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="signal" spirit:name="clock_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>CLK</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>s00_axi_aclk</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_BUSIF</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_BUSIF">S00_AXI</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>ASSOCIATED_RESET</spirit:name>
|
|
<spirit:value spirit:id="BUSIFPARAM_VALUE.S00_AXI_CLK.ASSOCIATED_RESET">s00_axi_aresetn</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>emrq</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WR_DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>emrq_wr_data</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WR_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>emrq_wr_en</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>FULL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>emrq_full</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>emwr</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_write_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WR_DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>emwr_wr_data</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>WR_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>emwr_wr_en</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>FULL</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>emwr_full</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>emrr</spirit:name>
|
|
<spirit:busType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="xilinx.com" spirit:library="interface" spirit:name="fifo_read_rtl" spirit:version="1.0"/>
|
|
<spirit:master/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RD_DATA</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>emrr_rd_data</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>RD_EN</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>emrr_rd_en</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>EMPTY</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>emrr_empty</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
<spirit:busInterface>
|
|
<spirit:name>ecfg</spirit:name>
|
|
<spirit:busType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig" spirit:version="1.0"/>
|
|
<spirit:abstractionType spirit:vendor="adapteva.com" spirit:library="Adapteva" spirit:name="eConfig_rtl" spirit:version="1.0"/>
|
|
<spirit:slave/>
|
|
<spirit:portMaps>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>tx_ctrl_mode</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ecfg_tx_ctrl_mode</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
<spirit:portMap>
|
|
<spirit:logicalPort>
|
|
<spirit:name>coreid</spirit:name>
|
|
</spirit:logicalPort>
|
|
<spirit:physicalPort>
|
|
<spirit:name>ecfg_coreid</spirit:name>
|
|
</spirit:physicalPort>
|
|
</spirit:portMap>
|
|
</spirit:portMaps>
|
|
</spirit:busInterface>
|
|
</spirit:busInterfaces>
|
|
<spirit:memoryMaps>
|
|
<spirit:memoryMap>
|
|
<spirit:name>S00_AXI</spirit:name>
|
|
<spirit:addressBlock>
|
|
<spirit:name>S00_AXI_mem</spirit:name>
|
|
<spirit:baseAddress spirit:format="long" spirit:resolve="user">0</spirit:baseAddress>
|
|
<spirit:range spirit:format="long">4096</spirit:range>
|
|
<spirit:width spirit:format="long">32</spirit:width>
|
|
<spirit:usage>memory</spirit:usage>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_BASE_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI_MEM.OFFSET_BASE_PARAM" spirit:dependency="ADDRBLOCKPARAM_VALUE.S00_AXI_mem.OFFSET_BASE_PARAM">C_S00_AXI_BASEADDR</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>OFFSET_HIGH_PARAM</spirit:name>
|
|
<spirit:value spirit:id="ADDRBLOCKPARAM_VALUE.S00_AXI_MEM.OFFSET_HIGH_PARAM" spirit:dependency="ADDRBLOCKPARAM_VALUE.S00_AXI_mem.OFFSET_HIGH_PARAM">C_S00_AXI_HIGHADDR</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
</spirit:addressBlock>
|
|
</spirit:memoryMap>
|
|
</spirit:memoryMaps>
|
|
<spirit:model>
|
|
<spirit:views>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_verilogsynthesis</spirit:name>
|
|
<spirit:displayName>Verilog Synthesis</spirit:displayName>
|
|
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:synthesis</spirit:envIdentifier>
|
|
<spirit:language>verilog</spirit:language>
|
|
<spirit:modelName>esaxi_v1_0</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_verilogsynthesis_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_verilogbehavioralsimulation</spirit:name>
|
|
<spirit:displayName>Verilog Simulation</spirit:displayName>
|
|
<spirit:envIdentifier>verilogSource:vivado.xilinx.com:simulation</spirit:envIdentifier>
|
|
<spirit:language>verilog</spirit:language>
|
|
<spirit:modelName>esaxi_v1_0</spirit:modelName>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_verilogbehavioralsimulation_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_softwaredriver</spirit:name>
|
|
<spirit:displayName>Software Driver</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:sw.driver</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_softwaredriver_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>xilinx_xpgui</spirit:name>
|
|
<spirit:displayName>UI Layout</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:xgui.ui</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>xilinx_xpgui_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
</spirit:view>
|
|
<spirit:view>
|
|
<spirit:name>bd_tcl</spirit:name>
|
|
<spirit:displayName>Block Diagram</spirit:displayName>
|
|
<spirit:envIdentifier>:vivado.xilinx.com:block.diagram</spirit:envIdentifier>
|
|
<spirit:fileSetRef>
|
|
<spirit:localName>bd_tcl_view_fileset</spirit:localName>
|
|
</spirit:fileSetRef>
|
|
</spirit:view>
|
|
</spirit:views>
|
|
<spirit:ports>
|
|
<spirit:port>
|
|
<spirit:name>emwr_wr_data</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">102</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>emwr_wr_en</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>emwr_full</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>emwr_prog_full</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>emrq_wr_data</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">102</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>emrq_wr_en</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>emrq_full</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>emrq_prog_full</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>emrr_rd_data</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">102</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>emrr_rd_en</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>emrr_empty</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>1</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ecfg_tx_ctrl_mode</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>ecfg_coreid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">11</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>optional</xilinx:presence>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH')) >0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awaddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">29</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awlen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">7</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awsize</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">2</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awburst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">1</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awlock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awcache</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">2</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awregion</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awqos</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_AWUSER_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>optional</xilinx:presence>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:dependency="spirit:decode(id('PARAM_VALUE.C_S00_AXI_AWUSER_WIDTH')) >0">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_awready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_wdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_wstrb</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="((spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) / 8) - 1)">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_wlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_wuser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_WUSER_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>optional</xilinx:presence>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:dependency="spirit:decode(id('PARAM_VALUE.C_S00_AXI_WUSER_WIDTH')) >0">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_wvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_wready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_bid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>optional</xilinx:presence>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH')) >0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_bresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">1</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_buser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_BUSER_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>optional</xilinx:presence>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:dependency="spirit:decode(id('PARAM_VALUE.C_S00_AXI_BUSER_WIDTH')) >0">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_bvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_bready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>optional</xilinx:presence>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH')) >0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_araddr</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH')) - 1)">29</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arlen</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">7</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arsize</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">2</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arburst</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">1</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arlock</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arcache</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arprot</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">2</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arregion</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arqos</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">3</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_aruser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ARUSER_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>optional</xilinx:presence>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:dependency="spirit:decode(id('PARAM_VALUE.C_S00_AXI_ARUSER_WIDTH')) >0">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_arready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_rid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>optional</xilinx:presence>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:dependency="spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH')) >0">true</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_rdata</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH')) - 1)">31</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_rresp</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="immediate">1</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_rlast</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_ruser</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:vector>
|
|
<spirit:left spirit:format="long" spirit:resolve="dependent" spirit:dependency="(spirit:decode(id('MODELPARAM_VALUE.C_S00_AXI_RUSER_WIDTH')) - 1)">0</spirit:left>
|
|
<spirit:right spirit:format="long" spirit:resolve="immediate">0</spirit:right>
|
|
</spirit:vector>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
<spirit:driver>
|
|
<spirit:defaultValue>0</spirit:defaultValue>
|
|
</spirit:driver>
|
|
</spirit:wire>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:portInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:presence>optional</xilinx:presence>
|
|
<xilinx:isEnabled xilinx:resolve="dependent" xilinx:dependency="spirit:decode(id('PARAM_VALUE.C_S00_AXI_RUSER_WIDTH')) >0">false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:portInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_rvalid</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>out</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_rready</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_aclk</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
<spirit:port>
|
|
<spirit:name>s00_axi_aresetn</spirit:name>
|
|
<spirit:wire>
|
|
<spirit:direction>in</spirit:direction>
|
|
<spirit:wireTypeDefs>
|
|
<spirit:wireTypeDef>
|
|
<spirit:typeName>wire</spirit:typeName>
|
|
<spirit:viewNameRef>xilinx_verilogsynthesis</spirit:viewNameRef>
|
|
<spirit:viewNameRef>xilinx_verilogbehavioralsimulation</spirit:viewNameRef>
|
|
</spirit:wireTypeDef>
|
|
</spirit:wireTypeDefs>
|
|
</spirit:wire>
|
|
</spirit:port>
|
|
</spirit:ports>
|
|
<spirit:modelParameters>
|
|
<spirit:modelParameter xsi:type="spirit:nameValueTypeType" spirit:dataType="integer">
|
|
<spirit:name>C_S00_AXI_ID_WIDTH</spirit:name>
|
|
<spirit:displayName>C_S00_AXI_ID_WIDTH</spirit:displayName>
|
|
<spirit:description>Width of ID for for write address, write data, read address and read data</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ID_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_S00_AXI_ID_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_S00_AXI_ID_WIDTH'))))" spirit:order="3" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
|
|
<spirit:displayName>C_S00_AXI_DATA_WIDTH</spirit:displayName>
|
|
<spirit:description>Width of S_AXI data bus</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="4" spirit:rangeType="long">32</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
|
|
<spirit:displayName>C_S00_AXI_ADDR_WIDTH</spirit:displayName>
|
|
<spirit:description>Width of S_AXI address bus</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="5" spirit:rangeType="long">30</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S00_AXI_AWUSER_WIDTH</spirit:name>
|
|
<spirit:displayName>C_S00_AXI_AWUSER_WIDTH</spirit:displayName>
|
|
<spirit:description>Width of optional user defined signal in write address channel</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_AWUSER_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_S00_AXI_AWUSER_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_S00_AXI_AWUSER_WIDTH'))))" spirit:order="6" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S00_AXI_ARUSER_WIDTH</spirit:name>
|
|
<spirit:displayName>C_S00_AXI_ARUSER_WIDTH</spirit:displayName>
|
|
<spirit:description>Width of optional user defined signal in read address channel</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_ARUSER_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_S00_AXI_ARUSER_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_S00_AXI_ARUSER_WIDTH'))))" spirit:order="7" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S00_AXI_WUSER_WIDTH</spirit:name>
|
|
<spirit:displayName>C_S00_AXI_WUSER_WIDTH</spirit:displayName>
|
|
<spirit:description>Width of optional user defined signal in write data channel</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_WUSER_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_S00_AXI_WUSER_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_S00_AXI_WUSER_WIDTH'))))" spirit:order="8" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S00_AXI_RUSER_WIDTH</spirit:name>
|
|
<spirit:displayName>C_S00_AXI_RUSER_WIDTH</spirit:displayName>
|
|
<spirit:description>Width of optional user defined signal in read data channel</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_RUSER_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_S00_AXI_RUSER_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_S00_AXI_RUSER_WIDTH'))))" spirit:order="9" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_S00_AXI_BUSER_WIDTH</spirit:name>
|
|
<spirit:displayName>C_S00_AXI_BUSER_WIDTH</spirit:displayName>
|
|
<spirit:description>Width of optional user defined signal in write response channel</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_S00_AXI_BUSER_WIDTH" spirit:dependency="((spirit:decode(id('PARAM_VALUE.C_S00_AXI_BUSER_WIDTH')) <= 0 ) + (spirit:decode(id('PARAM_VALUE.C_S00_AXI_BUSER_WIDTH'))))" spirit:order="10" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">1</spirit:value>
|
|
</spirit:modelParameter>
|
|
<spirit:modelParameter spirit:dataType="integer">
|
|
<spirit:name>C_READ_TAG_ADDR</spirit:name>
|
|
<spirit:displayName>C Read Tag Addr</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="generated" spirit:id="MODELPARAM_VALUE.C_READ_TAG_ADDR" spirit:bitStringLength="12">0x810</spirit:value>
|
|
</spirit:modelParameter>
|
|
</spirit:modelParameters>
|
|
</spirit:model>
|
|
<spirit:choices>
|
|
<spirit:choice>
|
|
<spirit:name>choices_0</spirit:name>
|
|
<spirit:enumeration>32</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choices_1</spirit:name>
|
|
<spirit:enumeration>64</spirit:enumeration>
|
|
<spirit:enumeration>128</spirit:enumeration>
|
|
<spirit:enumeration>256</spirit:enumeration>
|
|
<spirit:enumeration>512</spirit:enumeration>
|
|
<spirit:enumeration>1024</spirit:enumeration>
|
|
<spirit:enumeration>2048</spirit:enumeration>
|
|
<spirit:enumeration>4096</spirit:enumeration>
|
|
</spirit:choice>
|
|
<spirit:choice>
|
|
<spirit:name>choices_2</spirit:name>
|
|
<spirit:enumeration spirit:text="true">1</spirit:enumeration>
|
|
<spirit:enumeration spirit:text="false">0</spirit:enumeration>
|
|
</spirit:choice>
|
|
</spirit:choices>
|
|
<spirit:fileSets>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_verilogsynthesis_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>hdl/esaxi_v1_0_S00_AXI.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/esaxi_v1_0.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
<spirit:userFileType>CHECKSUM_9e9b3bf8</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_verilogbehavioralsimulation_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>hdl/esaxi_v1_0_S00_AXI.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>hdl/esaxi_v1_0.v</spirit:name>
|
|
<spirit:fileType>verilogSource</spirit:fileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_softwaredriver_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>drivers/esaxi_v1_0/data/esaxi.mdd</spirit:name>
|
|
<spirit:userFileType>mdd</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>drivers/esaxi_v1_0/data/esaxi.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
<spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>drivers/esaxi_v1_0/src/Makefile</spirit:name>
|
|
<spirit:userFileType>unknown</spirit:userFileType>
|
|
<spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>drivers/esaxi_v1_0/src/esaxi.h</spirit:name>
|
|
<spirit:fileType>cSource</spirit:fileType>
|
|
<spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>drivers/esaxi_v1_0/src/esaxi.c</spirit:name>
|
|
<spirit:fileType>cSource</spirit:fileType>
|
|
<spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
|
|
</spirit:file>
|
|
<spirit:file>
|
|
<spirit:name>drivers/esaxi_v1_0/src/esaxi_selftest.c</spirit:name>
|
|
<spirit:fileType>cSource</spirit:fileType>
|
|
<spirit:userFileType>USED_IN_hw_handoff</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>xilinx_xpgui_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>xgui/esaxi_v1_0.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
<spirit:userFileType>XGUI_VERSION_2</spirit:userFileType>
|
|
<spirit:userFileType>CHECKSUM_e7426bc9</spirit:userFileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
<spirit:fileSet>
|
|
<spirit:name>bd_tcl_view_fileset</spirit:name>
|
|
<spirit:file>
|
|
<spirit:name>bd/bd.tcl</spirit:name>
|
|
<spirit:fileType>tclSource</spirit:fileType>
|
|
</spirit:file>
|
|
</spirit:fileSet>
|
|
</spirit:fileSets>
|
|
<spirit:description>AXI4 Slave - eLink interface</spirit:description>
|
|
<spirit:parameters>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_ID_WIDTH</spirit:name>
|
|
<spirit:displayName>C S00 AXI ID WIDTH</spirit:displayName>
|
|
<spirit:description>Width of ID for for write address, write data, read address and read data</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ID_WIDTH" spirit:order="3" spirit:minimum="0" spirit:maximum="32" spirit:rangeType="long">1</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_DATA_WIDTH</spirit:name>
|
|
<spirit:displayName>C S00 AXI DATA WIDTH</spirit:displayName>
|
|
<spirit:description>Width of S_AXI data bus</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_DATA_WIDTH" spirit:order="4" spirit:rangeType="long">32</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled>false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_ADDR_WIDTH</spirit:name>
|
|
<spirit:displayName>C S00 AXI ADDR WIDTH</spirit:displayName>
|
|
<spirit:description>Width of S_AXI address bus</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ADDR_WIDTH" spirit:order="5" spirit:rangeType="long">30</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled>false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_AWUSER_WIDTH</spirit:name>
|
|
<spirit:displayName>C S00 AXI AWUSER WIDTH</spirit:displayName>
|
|
<spirit:description>Width of optional user defined signal in write address channel</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_AWUSER_WIDTH" spirit:order="6" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_ARUSER_WIDTH</spirit:name>
|
|
<spirit:displayName>C S00 AXI ARUSER WIDTH</spirit:displayName>
|
|
<spirit:description>Width of optional user defined signal in read address channel</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_ARUSER_WIDTH" spirit:order="7" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_WUSER_WIDTH</spirit:name>
|
|
<spirit:displayName>C S00 AXI WUSER WIDTH</spirit:displayName>
|
|
<spirit:description>Width of optional user defined signal in write data channel</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_WUSER_WIDTH" spirit:order="8" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_RUSER_WIDTH</spirit:name>
|
|
<spirit:displayName>C S00 AXI RUSER WIDTH</spirit:displayName>
|
|
<spirit:description>Width of optional user defined signal in read data channel</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_RUSER_WIDTH" spirit:order="9" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_BUSER_WIDTH</spirit:name>
|
|
<spirit:displayName>C S00 AXI BUSER WIDTH</spirit:displayName>
|
|
<spirit:description>Width of optional user defined signal in write response channel</spirit:description>
|
|
<spirit:value spirit:format="long" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BUSER_WIDTH" spirit:order="10" spirit:minimum="0" spirit:maximum="1024" spirit:rangeType="long">0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_BASEADDR</spirit:name>
|
|
<spirit:displayName>C S00 AXI BASEADDR</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_BASEADDR" spirit:order="11" spirit:bitStringLength="32">0xFFFFFFFF</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled>false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_S00_AXI_HIGHADDR</spirit:name>
|
|
<spirit:displayName>C S00 AXI HIGHADDR</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_S00_AXI_HIGHADDR" spirit:order="12" spirit:bitStringLength="32">0x00000000</spirit:value>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:parameterInfo>
|
|
<xilinx:enablement>
|
|
<xilinx:isEnabled>false</xilinx:isEnabled>
|
|
</xilinx:enablement>
|
|
</xilinx:parameterInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>Component_Name</spirit:name>
|
|
<spirit:displayName>Component Name</spirit:displayName>
|
|
<spirit:value spirit:resolve="user" spirit:id="PARAM_VALUE.Component_Name" spirit:order="1">esaxi_v1_0</spirit:value>
|
|
</spirit:parameter>
|
|
<spirit:parameter>
|
|
<spirit:name>C_READ_TAG_ADDR</spirit:name>
|
|
<spirit:displayName>C Read Tag Addr</spirit:displayName>
|
|
<spirit:value spirit:format="bitString" spirit:resolve="user" spirit:id="PARAM_VALUE.C_READ_TAG_ADDR" spirit:configGroups="0 UnGrouped hexEdit" spirit:bitStringLength="12">0x810</spirit:value>
|
|
</spirit:parameter>
|
|
</spirit:parameters>
|
|
<spirit:vendorExtensions>
|
|
<xilinx:coreExtensions>
|
|
<xilinx:supportedFamilies>
|
|
<xilinx:family xilinx:lifeCycle="Pre-Production">zynq</xilinx:family>
|
|
</xilinx:supportedFamilies>
|
|
<xilinx:taxonomies>
|
|
<xilinx:taxonomy>AXI_Peripheral</xilinx:taxonomy>
|
|
</xilinx:taxonomies>
|
|
<xilinx:displayName>esaxi_v1.0</xilinx:displayName>
|
|
<xilinx:vendorDisplayName>Adapteva, Inc.</xilinx:vendorDisplayName>
|
|
<xilinx:vendorURL>http://www.adapteva.com</xilinx:vendorURL>
|
|
<xilinx:coreRevision>6</xilinx:coreRevision>
|
|
<xilinx:coreCreationDateTime>2014-12-17T23:20:19Z</xilinx:coreCreationDateTime>
|
|
<xilinx:tags>
|
|
<xilinx:tag xilinx:name="adapteva.com:Adapteva:esaxi:1.0_ARCHIVE_LOCATION">/home/frhuettig</xilinx:tag>
|
|
</xilinx:tags>
|
|
</xilinx:coreExtensions>
|
|
<xilinx:packagingInfo>
|
|
<xilinx:xilinxVersion>2014.3</xilinx:xilinxVersion>
|
|
</xilinx:packagingInfo>
|
|
</spirit:vendorExtensions>
|
|
</spirit:component>
|