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79 lines
2.4 KiB
Verilog
79 lines
2.4 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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Contributed by Andreas Olofsson <andreas@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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module esaxilite (/*AUTOARG*/
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// Outputs
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s_axicfg_arready, s_axicfg_awready, s_axicfg_bresp,
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s_axicfg_bvalid, s_axicfg_rdata, s_axicfg_rresp, s_axicfg_rvalid,
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s_axicfg_wready, mi_clk, mi_en, mi_we, mi_addr, mi_din,
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// Inputs
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s_axicfg_araddr, s_axicfg_arprot, s_axicfg_arvalid,
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s_axicfg_awaddr, s_axicfg_awprot, s_axicfg_awvalid,
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s_axicfg_bready, s_axicfg_rready, s_axicfg_wdata, s_axicfg_wstrb,
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s_axicfg_wvalid, mi_rd_data
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);
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parameter RFAW = 16;
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/*****************************/
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/*AXI 32 bit lite interface */
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/*****************************/
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//read address channel
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input [15:0] s_axicfg_araddr;
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input [2:0] s_axicfg_arprot;
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output s_axicfg_arready;
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input s_axicfg_arvalid;
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//write address channel
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input [15:0] s_axicfg_awaddr;
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input [2:0] s_axicfg_awprot;
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output s_axicfg_awready;
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input s_axicfg_awvalid;
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//buffered read response channel
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input s_axicfg_bready;
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output [1:0] s_axicfg_bresp;
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output s_axicfg_bvalid;
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//read channel
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output [31:0] s_axicfg_rdata;
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input s_axicfg_rready;
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output [1:0] s_axicfg_rresp;
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output s_axicfg_rvalid;
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//write channel
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input [31:0] s_axicfg_wdata;
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output s_axicfg_wready;
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input [3:0] s_axicfg_wstrb;
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input s_axicfg_wvalid;
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/*****************************/
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/*Simple memory interface */
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/*****************************/
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output mi_clk;
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output mi_en;
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output mi_we;
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output [RFAW-1:0] mi_addr;
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output [31:0] mi_din;
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input [31:0] mi_rd_data;
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//muxing done outside
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endmodule // esaxilite
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