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54 lines
1.7 KiB
Verilog
54 lines
1.7 KiB
Verilog
/*
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File: version.v
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This file is part of the Parallella Project
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Copyright (C) 2013 Adapteva, Inc.
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Contributed by Andreas Olofsson <support@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program (see the file COPYING). If not, see
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<http://www.gnu.org/licenses/>.
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*/
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// This version info is local to each project.
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// Version register is {8'Generation, 8'Platform, 8'Type, 8'Version}
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// Please see versions.txt in the top-level fpga directory.
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// Generation 1 - Parallella-I
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// Platform 3 - E16, 7Z010, GPIO
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// Type 3 - Headless, 24 singled-ended GPIOs from EMIO
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// Version 1 - First 7010 type 3, 4/22/14, FH
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// 2 - Added cclk gating on e-reset, tx-disable, 5/5/14, FH
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`define VERSION_VALUE {8'h01, 8'd03, 8'd03, 8'd02}
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// Define one of the following for target FPGA
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`define TARGET_7Z010 1
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//`define TARGET_7Z020 1
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// Define one of the following for target processor
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`define TARGET_E16 1
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//`define TARGET_E64 1
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// Define included features
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//`define FEATURE_HDMI 1
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`define FEATURE_GPIO_EMIO 1
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//`define FEATURE_GPIO_DIFF 1
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`define FEATURE_CCLK_DIV 1
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// Set IOSTANDARD for GPIO pins
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`define IOSTD_GPIO "LVCMOS25"
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//`define IOSTD_GPIO "LVDS_25"
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