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https://github.com/parallella/parallella-hw.git
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73 lines
1.5 KiB
Verilog
73 lines
1.5 KiB
Verilog
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`timescale 1 ns / 1 ps
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module elink2_tb;
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reg aclk;
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reg aresetn;
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reg start;
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wire csysreq = 1'b0;
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wire [1:0] done;
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wire [1:0] error;
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// Create an instance of the example tb
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elink_testbench dut
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(.aclk (aclk),
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.aresetn (aresetn),
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.csysreq (csysreq),
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.done0 (done[0]),
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.done1 (done[1]),
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.error0 (error[0]),
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.error1 (error[1]),
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.start (start));
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// Reset Generator
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initial begin
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aresetn = 1'b0;
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#500;
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// Release the reset on the posedge of the clk.
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@(posedge aclk);
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aresetn = 1'b1;
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end
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// Clock Generator
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initial aclk = 1'b0;
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always #5 aclk = ~aclk;
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// Drive the BFM
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initial begin
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start = 1'b0;
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// Wait for end of reset
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wait(aresetn === 0) @(posedge aclk);
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wait(aresetn === 1) @(posedge aclk);
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wait(aresetn === 1) @(posedge aclk);
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wait(aresetn === 1) @(posedge aclk);
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wait(aresetn === 1) @(posedge aclk);
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#500 start = 1'b1;
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$display("=== TB Started");
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wait( done == 2'b11);
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$display("=== TEST_FINISHED");
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if ( error != 2'b00 ) begin
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$display("===_TEST: FAILED!");
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end else begin
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$display("=== TEST: PASSED!");
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end
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end
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always @ (posedge error[0])
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if( error[0] == 1'b1 )
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$display("=== ERROR FLAG 0 @ %t", $time);
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always @ (posedge error[1])
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if( error[1] == 1'b1 )
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$display("=== ERROR FLAG 1 @ %T", $time);
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endmodule
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