mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-24 03:34:40 +00:00
712 lines
17 KiB
Verilog
712 lines
17 KiB
Verilog
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`timescale 1 ns / 1 ps
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module elink2stream_tb;
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reg aclk;
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reg aresetn;
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reg start;
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wire reset = ~aresetn;
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wire done0;
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wire error0;
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wire rx_cclk_n;
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wire rx_cclk_p;
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wire [11:0] param_coreid = 12'h810;
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wire TX_rd_wait_n = 1'b1;
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wire TX_rd_wait_p = 1'b0;
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wire TX_wr_wait_n = 1'b1;
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wire TX_wr_wait_p = 1'b0;
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wire [31:0]M00_AXI_araddr;
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wire [1:0]M00_AXI_arburst;
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wire [3:0]M00_AXI_arcache;
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wire [0:0]M00_AXI_arid;
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wire [7:0]M00_AXI_arlen;
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wire M00_AXI_arlock;
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wire [2:0]M00_AXI_arprot;
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wire [3:0]M00_AXI_arqos;
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wire M00_AXI_arready = 1'b1;
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wire [2:0]M00_AXI_arsize;
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wire M00_AXI_arvalid;
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wire [31:0]M00_AXI_awaddr;
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wire [1:0]M00_AXI_awburst;
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wire [3:0]M00_AXI_awcache;
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wire [0:0]M00_AXI_awid;
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wire [7:0]M00_AXI_awlen;
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wire M00_AXI_awlock;
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wire [2:0]M00_AXI_awprot;
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wire [3:0]M00_AXI_awqos;
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wire M00_AXI_awready = 1'b1;
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wire [2:0]M00_AXI_awsize;
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wire M00_AXI_awvalid;
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wire [0:0]M00_AXI_bid = 1'b0;
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wire M00_AXI_bready;
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wire [1:0]M00_AXI_bresp = 2'b00;
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reg M00_AXI_bvalid;
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reg [63:0]M00_AXI_rdata;
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reg [0:0]M00_AXI_rid = 1'b0;
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reg M00_AXI_rlast;
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wire M00_AXI_rready;
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wire [1:0]M00_AXI_rresp = 2'b00;
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reg M00_AXI_rvalid;
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wire [63:0]M00_AXI_wdata;
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wire M00_AXI_wlast;
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wire M00_AXI_wready = 1'b1;
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wire [7:0]M00_AXI_wstrb;
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wire M00_AXI_wvalid;
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wire [7:0]TX_data_n;
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wire [7:0]TX_data_p;
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wire TX_frame_n;
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wire TX_frame_p;
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wire TX_lclk_n;
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wire TX_lclk_p;
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reg [7:0]RX_data_p;
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wire [7:0]RX_data_n = ~RX_data_p;
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reg RX_frame_p;
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wire RX_frame_n = ~RX_frame_p;
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wire RX_lclk_n = TX_lclk_n;
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wire RX_lclk_p = TX_lclk_p;
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wire RX_rd_wait_n;
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wire RX_rd_wait_p;
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wire RX_wr_wait_n;
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wire RX_wr_wait_p;
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// Transaction parameters
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reg [31:0] src, dst, data;
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reg [3:0] ctrlmode;
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reg [1:0] datamode;
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reg write;
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reg access;
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reg stream;
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reg [31:0] delay;
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reg done;
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wire all_done;
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assign #5000 all_done = done;
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// Transmitter state machine
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reg [15:0] pc;
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reg [4:0] txstate;
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reg [15:0] delaycnt;
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reg isstream;
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integer writecount;
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integer readcount;
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integer fileid;
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initial begin
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fileid = $fopen("../../test_prog.dat", "r");
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if(fileid == 0) begin
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$display("Unable to open file!");
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$finish;
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end
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end
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task getnext;
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begin // delay src dst data cmode dmode write access stream done
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$fscanf(fileid, "%d %h %h %h %h %d %d %d %d %d",
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delay, src, dst, data, ctrlmode, datamode, write, access, stream, done);
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if($feof(fileid)) begin
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$display "Unexpected EOF\n";
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$finish;
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end
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end
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endtask // getnext
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always @ ( * ) begin
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// defaults
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src = 32'd0;
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dst = 32'd0;
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data = 32'd0;
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ctrlmode = 4'd0;
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datamode = 2'd0;
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write = 1'b0;
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access = 1'b0;
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stream = 1'b0;
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delay = 32'd0;
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done = 1'b0;
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case(pc)
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0: delay = 32'd50;
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1: begin
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dst = 32'hE0000005;
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data = 32'h00000012;
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datamode = 2'd0; // Byte write
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write = 1'b1;
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access = 1'b1;
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end
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2: delay = 32'd5;
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3: begin
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dst = 32'hE000000A;
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data = 32'h0000ABCD;
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datamode = 2'd1; // 16b HWord write
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write = 1'b1;
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access = 1'b1;
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end
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4: delay = 32'd6;
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5: begin
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dst = 32'hE0000010;
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data = 32'h87654321;
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datamode = 2'd2; // 32b Word write
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write = 1'b1;
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access = 1'b1;
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end
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6: delay = 32'd3;
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7: begin
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dst = 32'hE0000020;
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data = 32'h9ABCDEF0;
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src = 32'h12345678;
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datamode = 2'd3; // 64b DWord write
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write = 1'b1;
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access = 1'b1;
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end
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8: delay = 32'd25;
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9: begin
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dst = 32'hE0000040;
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data = 32'h11111111;
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src = 32'h22222222;
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datamode = 2'd3;
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stream = 1'b1;
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write = 1'b1;
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access = 1'b1;
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end
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10: begin
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data = 32'h33333333;
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src = 32'h44444444;
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stream = 1'b1;
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end
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11: begin
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data = 32'h55555555;
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src = 32'h66666666;
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end
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12: delay = 32'd2;
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13: begin
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dst = 32'hE0000040;
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data = 32'h11111111;
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src = 32'h22222222;
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datamode = 2'd3;
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stream = 1'b1;
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write = 1'b1;
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access = 1'b1;
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end
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14: begin
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data = 32'h33333333;
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src = 32'h44444444;
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stream = 1'b1;
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end
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15: begin
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data = 32'h55555555;
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src = 32'h66666666;
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end
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16: delay = 32'd2;
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17: begin
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dst = 32'hE0000040;
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data = 32'h11111111;
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src = 32'h22222222;
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datamode = 2'd3;
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stream = 1'b1;
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write = 1'b1;
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access = 1'b1;
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end
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18: begin
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data = 32'h33333333;
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src = 32'h44444444;
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stream = 1'b1;
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end
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19: begin
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data = 32'h55555555;
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src = 32'h66666666;
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end
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20: delay = 32'd2;
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21: begin
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dst = 32'hE0000040;
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data = 32'h11111111;
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src = 32'h22222222;
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datamode = 2'd3;
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stream = 1'b1;
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write = 1'b1;
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access = 1'b1;
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end
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22: begin
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data = 32'h33333333;
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src = 32'h44444444;
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stream = 1'b1;
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end
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23: begin
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data = 32'h55555555;
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src = 32'h66666666;
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end
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24: delay = 32'd2;
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25: begin
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dst = 32'hE0000040;
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data = 32'h11111111;
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src = 32'h22222222;
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datamode = 2'd3;
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stream = 1'b1;
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write = 1'b1;
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access = 1'b1;
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end
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26: begin
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data = 32'h33333333;
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src = 32'h44444444;
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stream = 1'b1;
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end
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27: begin
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data = 32'h55555555;
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src = 32'h66666666;
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end
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28: delay = 32'd2;
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29: begin
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dst = 32'hE0000040;
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data = 32'h11111111;
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src = 32'h22222222;
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datamode = 2'd3;
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stream = 1'b1;
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write = 1'b1;
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access = 1'b1;
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end
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30: begin
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data = 32'h33333333;
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src = 32'h44444444;
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stream = 1'b1;
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end
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31: begin
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data = 32'h55555555;
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src = 32'h66666666;
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end
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32: delay = 32'd2;
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33: begin
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dst = 32'hE0000040;
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data = 32'h11111111;
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src = 32'h22222222;
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datamode = 2'd3;
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stream = 1'b1;
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write = 1'b1;
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access = 1'b1;
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end
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34: begin
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data = 32'h33333333;
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src = 32'h44444444;
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stream = 1'b1;
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end
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35: begin
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data = 32'h55555555;
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src = 32'h66666666;
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end
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36: delay = 32'd2;
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37: begin
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dst = 32'hE0000040;
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data = 32'h11111111;
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src = 32'h22222222;
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datamode = 2'd3;
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stream = 1'b1;
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write = 1'b1;
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access = 1'b1;
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end
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38: begin
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data = 32'h33333333;
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src = 32'h44444444;
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stream = 1'b1;
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end
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39: begin
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data = 32'h55555555;
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src = 32'h66666666;
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end
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40: begin
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delay = 32'd1;
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end
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41: begin
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dst = 32'h88880000;
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data = 32'hDEADBEEF;
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datamode = 2'd2;
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write = 1'b1;
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access = 1'b1;
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end
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42: begin
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delay = 32'd12;
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end
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43: begin
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dst = 32'h88880000;
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data = 32'hFEEDF00D;
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datamode = 2'd2;
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write = 1'b1;
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access = 1'b1;
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end
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44: begin
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done = 1'b1;
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end
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default: begin
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src = 32'hXXXXXXXX;
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dst = 32'hXXXXXXXX;
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data = 32'hXXXXXXXX;
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ctrlmode = 4'hX;
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datamode = 2'bXX;
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write = 1'bX;
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access = 1'bX;
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stream = 1'bX;
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delay = 32'hXXXXXXXX;
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done = 1'b1;
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end
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endcase // case (pc)
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end // always @ ( * )
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wire lclk_delay;
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assign #0.8333 lclk_delay = TX_lclk_p;
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// Test transmitter
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always @ (lclk_delay) begin
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if(~done0) begin
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pc <= 16'd0;
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txstate <= 5'd0;
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delaycnt <= 16'd0;
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RX_data_p <= 8'd0;
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RX_frame_p <= 1'b0;
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isstream <= 1'b0;
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writecount <= 0;
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readcount <= 0;
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end else begin
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// default is to advance to next state
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txstate <= txstate + 1;
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case(txstate)
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5'd0: begin // Start new transaction or delay
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RX_frame_p <= 1'b0;
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delaycnt <= delay - 16'd2;
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isstream <= 1'b0;
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if(done) begin
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txstate <= 5'd31;
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$display("<-- Transmission complete!");
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end else if(delay == 16'd1) begin
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txstate <= 5'd0;
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pc <= pc + 16'd1;
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$display("<-- Waiting 1 cycle");
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end else if(|delay) begin
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txstate <= 5'd16;
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$display("<-- Waiting %d cycles", delay);
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end else if(RX_wr_wait_p | RX_rd_wait_p) begin
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txstate <= 5'd0;
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end else begin
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if(write) begin
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$write("<-- %d Writing ", writecount);
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writecount <= writecount + 1;
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end else begin
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$write("<-- %d Reading ", readcount);
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readcount <= readcount + 1;
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end
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case(datamode)
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2'd0: $write("BYTE ");
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2'd1: $write("HWORD ");
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2'd2: $write("WORD ");
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2'd3: $write("DWORD ");
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endcase // case (datamode)
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if(write && datamode == 3'd3)
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$display("0x%H:0x%H to address 0x%H", src, data, dst);
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else if(write)
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$display("0x%H to address 0x%H", data, dst);
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else
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$display("from address 0x%H, return to 0x%H", dst, src);
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end
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end
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5'd1: begin // TRAN byte
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RX_data_p <= {~write, 7'd0};
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RX_frame_p <= 1'b1;
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end
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5'd2:
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RX_data_p <= {ctrlmode, dst[31:28]};
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5'd3:
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RX_data_p <= dst[27:20];
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5'd4:
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RX_data_p <= dst[19:12];
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5'd5:
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RX_data_p <= dst[11:4];
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5'd6:
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RX_data_p <= {dst[3:0], datamode, write, access};
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5'd7: begin
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if(isstream) begin
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$display("<-- %d Streaming data 0x%H:0x%H",
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writecount, src, data);
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writecount <= writecount + 1;
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end
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RX_data_p <= data[31:24];
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end
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5'd8:
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RX_data_p <= data[23:16];
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5'd9:
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RX_data_p <= data[15:8];
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5'd10:
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RX_data_p <= data[7:0];
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5'd11:
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RX_data_p <= src[31:24];
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5'd12:
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RX_data_p <= src[23:16];
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5'd13:
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RX_data_p <= src[15:8];
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5'd14: begin
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RX_data_p <= src[7:0];
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pc <= pc + 1;
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isstream <= stream;
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if(stream)
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txstate <= 5'd7; // next 'data'
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else
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txstate <= 5'd0;
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end
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5'd16: begin // delay, hold eLink idle
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delaycnt <= delaycnt - 1;
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if(~|delaycnt) begin
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pc <= pc + 1;
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txstate <= 5'd0;
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end else begin
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txstate <= txstate; // override default
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end
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end
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5'd31: txstate <= txstate; // All done
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endcase // case (txstate)
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end // else: !if(reset)
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end // always @ (TX_lclk_p)
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integer awcount, wcount, arcount;
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initial begin
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awcount = 0;
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wcount = 0;
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arcount = 0;
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end
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always @ (posedge aclk) begin
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if(M00_AXI_awvalid & M00_AXI_awready) begin
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$display("--> %d Write address: 0x%H, size: %d, len: %d",
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awcount, M00_AXI_awaddr, M00_AXI_awsize, M00_AXI_awlen);
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awcount <= awcount + 1;
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end
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end
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// Respond to write requests
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always @ (posedge aclk) begin
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if(reset) begin
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M00_AXI_bvalid <= 1'b0;
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end else begin
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if(M00_AXI_awvalid & M00_AXI_awready) begin
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$display("--> %d Write data: 0x%H", wcount, M00_AXI_wdata);
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M00_AXI_bvalid <= 1'b1;
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wcount <= wcount + 1;
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end else if(M00_AXI_bready) begin
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M00_AXI_bvalid <= 1'b0;
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end
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end
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end
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// Respond to read requests
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always @ (posedge aclk) begin
|
|
if(reset) begin
|
|
M00_AXI_rdata <= 64'd0;
|
|
M00_AXI_rlast <= 1'b0;
|
|
M00_AXI_rvalid <= 1'b0;
|
|
end else begin
|
|
|
|
if(M00_AXI_arvalid & M00_AXI_arready) begin
|
|
$display("--> %d Read request: <TBD>", arcount);
|
|
arcount <= arcount + 1;
|
|
end
|
|
|
|
end
|
|
end
|
|
|
|
|
|
// Reset Generator
|
|
initial begin
|
|
aresetn = 1'b0;
|
|
#500;
|
|
// Release the reset on the posedge of the clk.
|
|
@(posedge aclk);
|
|
aresetn = 1'b1;
|
|
end
|
|
|
|
// Clock Generator
|
|
initial aclk = 1'b0;
|
|
always #5 aclk = ~aclk;
|
|
|
|
// Drive the BFM
|
|
initial begin
|
|
|
|
start = 1'b0;
|
|
|
|
// Wait for end of reset
|
|
wait(aresetn === 0) @(posedge aclk);
|
|
wait(aresetn === 1) @(posedge aclk);
|
|
|
|
#500 start = 1'b1;
|
|
@(posedge aclk);
|
|
|
|
$display("=== TB Started");
|
|
|
|
wait( all_done == 1'b1);
|
|
$display("=== TEST_FINISHED");
|
|
if ( wcount != writecount || arcount != readcount ) begin
|
|
$display("=== TEST: FAILED!\n %d writes sent, %d writes rcvd\n %d reads sent, %d reads rcvd",
|
|
writecount, wcount, readcount, arcount);
|
|
end else begin
|
|
$display("=== TEST: PASSED!");
|
|
end
|
|
|
|
end
|
|
|
|
always @ (posedge done0)
|
|
$display("=== INIT Complete");
|
|
|
|
always @ (posedge error0)
|
|
if( done0 == 1'b0)
|
|
$display("=== ERROR FLAG INIT @ %T", $time);
|
|
|
|
// Create an instance of the example
|
|
elink2_stream dut
|
|
(.M00_AXI_araddr(M00_AXI_araddr),
|
|
.M00_AXI_arburst(M00_AXI_arburst),
|
|
.M00_AXI_arcache(M00_AXI_arcache),
|
|
.M00_AXI_arid(M00_AXI_arid),
|
|
.M00_AXI_arlen(M00_AXI_arlen),
|
|
.M00_AXI_arlock(M00_AXI_arlock),
|
|
.M00_AXI_arprot(M00_AXI_arprot),
|
|
.M00_AXI_arqos(M00_AXI_arqos),
|
|
.M00_AXI_arready(M00_AXI_arready),
|
|
.M00_AXI_arsize(M00_AXI_arsize),
|
|
.M00_AXI_arvalid(M00_AXI_arvalid),
|
|
.M00_AXI_awaddr(M00_AXI_awaddr),
|
|
.M00_AXI_awburst(M00_AXI_awburst),
|
|
.M00_AXI_awcache(M00_AXI_awcache),
|
|
.M00_AXI_awid(M00_AXI_awid),
|
|
.M00_AXI_awlen(M00_AXI_awlen),
|
|
.M00_AXI_awlock(M00_AXI_awlock),
|
|
.M00_AXI_awprot(M00_AXI_awprot),
|
|
.M00_AXI_awqos(M00_AXI_awqos),
|
|
.M00_AXI_awready(M00_AXI_awready),
|
|
.M00_AXI_awsize(M00_AXI_awsize),
|
|
.M00_AXI_awvalid(M00_AXI_awvalid),
|
|
.M00_AXI_bid(M00_AXI_bid),
|
|
.M00_AXI_bready(M00_AXI_bready),
|
|
.M00_AXI_bresp(M00_AXI_bresp),
|
|
.M00_AXI_bvalid(M00_AXI_bvalid),
|
|
.M00_AXI_rdata(M00_AXI_rdata),
|
|
.M00_AXI_rid(M00_AXI_rid),
|
|
.M00_AXI_rlast(M00_AXI_rlast),
|
|
.M00_AXI_rready(M00_AXI_rready),
|
|
.M00_AXI_rresp(M00_AXI_rresp),
|
|
.M00_AXI_rvalid(M00_AXI_rvalid),
|
|
.M00_AXI_wdata(M00_AXI_wdata),
|
|
.M00_AXI_wlast(M00_AXI_wlast),
|
|
.M00_AXI_wready(M00_AXI_wready),
|
|
.M00_AXI_wstrb(M00_AXI_wstrb),
|
|
.M00_AXI_wvalid(M00_AXI_wvalid),
|
|
.RX_data_n(RX_data_n),
|
|
.RX_data_p(RX_data_p),
|
|
.RX_frame_n(RX_frame_n),
|
|
.RX_frame_p(RX_frame_p),
|
|
.RX_lclk_n(RX_lclk_n),
|
|
.RX_lclk_p(RX_lclk_p),
|
|
.RX_rd_wait_n(RX_rd_wait_n),
|
|
.RX_rd_wait_p(RX_rd_wait_p),
|
|
.RX_wr_wait_n(RX_wr_wait_n),
|
|
.RX_wr_wait_p(RX_wr_wait_p),
|
|
.TX_data_n(TX_data_n),
|
|
.TX_data_p(TX_data_p),
|
|
.TX_frame_n(TX_frame_n),
|
|
.TX_frame_p(TX_frame_p),
|
|
.TX_lclk_n(TX_lclk_n),
|
|
.TX_lclk_p(TX_lclk_p),
|
|
.TX_rd_wait_n(TX_rd_wait_n),
|
|
.TX_rd_wait_p(TX_rd_wait_p),
|
|
.TX_wr_wait_n(TX_wr_wait_n),
|
|
.TX_wr_wait_p(TX_wr_wait_p),
|
|
.aclk(aclk),
|
|
.aresetn(aresetn),
|
|
.done0(done0),
|
|
.error0(error0),
|
|
.param_coreid(param_coreid),
|
|
.reset(reset),
|
|
.rx_cclk_n(rx_cclk_n),
|
|
.rx_cclk_p(rx_cclk_p),
|
|
.start(start));
|
|
|
|
|
|
endmodule
|