mirror of
https://github.com/parallella/parallella-hw.git
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304 lines
9.8 KiB
Verilog
304 lines
9.8 KiB
Verilog
//////////////////////////////////////////////////////////////////////////////////
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// Company:
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// Engineer:
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//
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// Create Date: 12/09/2014 02:03:49 PM
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// Design Name:
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// Module Name: estream_tb
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// Project Name:
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// Target Devices:
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// Tool Versions:
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// Description:
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//
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// Dependencies:
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//
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// Revision:
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// Revision 0.01 - File Created
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// Additional Comments:
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//
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//////////////////////////////////////////////////////////////////////////////////
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`timescale 1ns / 1ps
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`define NULL 0
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`define EOF 32'hFFFF_FFFF
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`define MAX_LINE_LENGTH 200
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module estream_tb( );
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/*AUTOWIRE*/
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// Beginning of automatic wires (for undeclared instantiated-module outputs)
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wire rx_access; // From rxi of ewrapper_link_rxi.v
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wire [3:0] rx_ctrlmode; // From rxi of ewrapper_link_rxi.v
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wire [31:0] rx_data; // From rxi of ewrapper_link_rxi.v
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wire [1:0] rx_datamode; // From rxi of ewrapper_link_rxi.v
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wire [31:0] rx_dstaddr; // From rxi of ewrapper_link_rxi.v
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wire [31:0] rx_srcaddr; // From rxi of ewrapper_link_rxi.v
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wire rx_write; // From rxi of ewrapper_link_rxi.v
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wire rxo_wait; // From rxi of ewrapper_link_rxi.v
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wire [71:0] tx_in; // From txo of ewrapper_link_txo.v
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wire txo_wait; // From txo of ewrapper_link_txo.v
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// End of automatics
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// Static inputs
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wire burst_en = 1'b1;
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wire rxi_rd = 1'b0;
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wire rx_wait = 1'b0; // RXI FIFO hold-off
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wire [63:0] rxi_data = tx_in[63:0];
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wire [7:0] rxi_frame = tx_in[71:64];
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// Transaction parameters
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reg [31:0] srcaddr, dstaddr, data;
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reg [3:0] ctrlmode;
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reg [1:0] datamode;
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reg write;
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reg access;
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reg stream;
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reg [31:0] delay;
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reg done;
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wire all_done;
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assign #5000 all_done = done;
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// Transmitter state machine
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reg clock;
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reg reset;
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reg [15:0] pc;
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reg [4:0] txstate;
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reg [15:0] delaycnt;
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reg isstream;
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integer writecount;
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integer readcount;
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integer fileid;
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integer fscanret;
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reg [8*`MAX_LINE_LENGTH:0] line;
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initial begin
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reset <= 1'b1;
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clock <= 1'b1;
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#500;
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reset <= 1'b0;
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end
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always
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#5 clock <= ~clock;
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wire txo_lclk = clock;
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wire rxi_lclk = clock;
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task getnext;
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begin // delay srcaddr dstaddr data cmode dmode write access stream done
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if($feof(fileid)) begin
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$display("Unexpected EOF");
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$finish;
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end
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fscanret = $fgets(line, fileid);
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fscanret = $sscanf(line, "%d %h %h %h %h %d %d %d %d %d",
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delay, srcaddr, dstaddr, data, ctrlmode, datamode,
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write, access, stream, done);
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if(fscanret == 1) begin
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srcaddr <= 32'd0;
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dstaddr <= 32'd0;
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data <= 32'd0;
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ctrlmode <= 4'd0;
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datamode <= 2'd0;
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write <= 1'b0;
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access <= 1'b0;
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stream <= 1'b0;
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done <= 1'b0;
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end else if(fscanret != 10) begin
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$display("ERROR: Wrong number of entries in file: (position %d) %s",
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$ftell(fileid), line);
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$finish;
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end
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end
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endtask // getnext
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initial begin
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fileid = $fopen("../../test_estream.dat", "r");
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if(fileid == 0) begin
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$display("Unable to open file!");
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$finish;
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end
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getnext();
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end
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// Test transmitter
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always @ (posedge txo_lclk) begin
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if(reset) begin
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pc <= 16'd1;
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txstate <= 5'd0;
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delaycnt <= 16'd0;
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isstream <= 1'b0;
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writecount <= 0;
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readcount <= 0;
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end else begin
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// default is to advance to next state
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txstate <= txstate + 1;
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case(txstate)
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5'd0: begin // Start new transaction or delay
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delaycnt <= delay - 16'd2;
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isstream <= 1'b0;
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if(done) begin
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txstate <= 5'd31;
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$display("<-- Transmission complete!");
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end else if(delay == 16'd1) begin
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txstate <= 5'd0;
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pc <= pc + 16'd1;
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getnext();
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$display("<-- Waiting 1 cycle");
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end else if(|delay) begin
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txstate <= 5'd16;
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$display("<-- Waiting %d cycles", delay);
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// end else if(RX_wr_wait_p | RX_rd_wait_p) begin
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// txstate <= 5'd0;
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end else begin
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if(write) begin
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$write("<-- %d Writing ", writecount);
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writecount <= writecount + 1;
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end else begin
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$write("<-- %d Reading ", readcount);
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readcount <= readcount + 1;
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end
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case(datamode)
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2'd0: $write("BYTE ");
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2'd1: $write("HWORD ");
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2'd2: $write("WORD ");
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2'd3: $write("DWORD ");
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endcase // case (datamode)
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if(write && datamode == 3'd3)
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$display("0x%H:0x%H to address 0x%H", srcaddr, data, dstaddr);
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else if(write)
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$display("0x%H to address 0x%H", data, dstaddr);
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else
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$display("from address 0x%H, return to 0x%H", dstaddr, srcaddr);
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pc <= pc + 16'd1;
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getnext();
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txstate <=5'd0;
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end
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end
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5'd16: begin // delay, hold eLink idle
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delaycnt <= delaycnt - 1;
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if(~|delaycnt) begin
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pc <= pc + 1;
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getnext();
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txstate <= 5'd0;
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end else begin
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txstate <= txstate; // override default
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end
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end
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5'd31: txstate <= txstate; // All done
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endcase // case (txstate)
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end // else: !if(reset)
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end // always @ (TX_lclk_p)
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integer wrcount, rdcount;
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// RXI Decoder
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always @ (posedge rxi_lclk) begin
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if(reset) begin
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wrcount <= 0;
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rdcount <= 0;
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end else begin
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if(rx_access) begin
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if(rx_write) begin
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$write("--> %d Write ", wrcount);
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wrcount <= wrcount + 1;
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case(rx_datamode)
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2'd0: $write("BYTE 0x%02X ", rx_data[7:0]);
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2'd1: $write("HWORD 0x%04X ", rx_data[15:0]);
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2'd2: $write("WORD 0x%08X ", rx_data[31:0]);
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2'd3: $write("DWORD 0x%08X:%08X ", rx_srcaddr, rx_data);
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endcase // case (rx_datamode)
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$display("to address 0x%08X", rx_dstaddr);
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end else begin
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$display("--> %d Read ", rdcount);
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rdcount <= rdcount + 1;
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case(rx_datamode)
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2'd0: $write("BYTE ");
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2'd1: $write("HWORD ");
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2'd2: $write("WORD ");
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2'd3: $write("DWORD ");
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endcase // case (rx_datamode)
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$display("from address 0x%08X, return address 0x%08X",
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rx_dstaddr, rx_srcaddr);
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end
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end
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end // else: !if(reset)
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end // always @ (posedge rxi_lclk)
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/* ewrapper_link_txo AUTO_TEMPLATE (
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.txo_emesh_wait (txo_wait),
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.txo_emesh_\(.*\) (\1[]),
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);
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*/
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ewrapper_link_txo txo
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(/*AUTOINST*/
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// Outputs
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.txo_emesh_wait (txo_wait), // Templated
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.tx_in (tx_in[71:0]),
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// Inputs
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.reset (reset),
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.txo_lclk (txo_lclk),
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.txo_emesh_access (access), // Templated
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.txo_emesh_write (write), // Templated
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.txo_emesh_datamode (datamode[1:0]), // Templated
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.txo_emesh_ctrlmode (ctrlmode[3:0]), // Templated
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.txo_emesh_dstaddr (dstaddr[31:0]), // Templated
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.txo_emesh_srcaddr (srcaddr[31:0]), // Templated
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.txo_emesh_data (data[31:0]), // Templated
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.burst_en (burst_en));
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/* ewrapper_link_rxi AUTO_TEMPLATE (
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.emesh_\(.*\)_inb (rx_\1[]),
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.emesh_\(.*\)_outb (rx_\1[]),
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)
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*/
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ewrapper_link_rxi rxi
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(/*AUTOINST*/
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// Outputs
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.rxo_wait (rxo_wait),
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.emesh_access_inb (rx_access), // Templated
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.emesh_write_inb (rx_write), // Templated
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.emesh_datamode_inb (rx_datamode[1:0]), // Templated
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.emesh_ctrlmode_inb (rx_ctrlmode[3:0]), // Templated
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.emesh_dstaddr_inb (rx_dstaddr[31:0]), // Templated
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.emesh_srcaddr_inb (rx_srcaddr[31:0]), // Templated
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.emesh_data_inb (rx_data[31:0]), // Templated
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// Inputs
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.reset (reset),
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.rxi_data (rxi_data[63:0]),
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.rxi_lclk (rxi_lclk),
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.rxi_frame (rxi_frame[7:0]),
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.emesh_wait_outb (rx_wait), // Templated
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.rxi_rd (rxi_rd));
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endmodule // estream_tb
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// Local Variables:
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// verilog-library-directories:("." "../../hdl/elink-gold")
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// End:
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