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205 lines
8.1 KiB
Verilog
205 lines
8.1 KiB
Verilog
/*
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Copyright (C) 2014 Adapteva, Inc.
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Contributed by Fred Huettig <fred@adapteva.com>
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This program is free software: you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation, either version 3 of the License, or
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(at your option) any later version.This program is distributed in the hope
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that it will be useful,but WITHOUT ANY WARRANTY; without even the implied
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warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details. You should have received a copy
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of the GNU General Public License along with this program (see the file
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COPYING). If not, see <http://www.gnu.org/licenses/>.
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*/
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`timescale 1ns/10ps
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module maxi_test (/*AUTOARG*/
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// Outputs
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ERROR, DONE, m_axi_awid, m_axi_awaddr, m_axi_awlen, m_axi_awsize,
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m_axi_awburst, m_axi_awlock, m_axi_awcache, m_axi_awprot,
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m_axi_awvalid, m_axi_awqos, m_axi_wid, m_axi_wdata, m_axi_wstrb,
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m_axi_wlast, m_axi_wvalid, m_axi_bready, m_axi_arid, m_axi_araddr,
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m_axi_arlen, m_axi_arsize, m_axi_arburst, m_axi_arlock,
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m_axi_arcache, m_axi_arprot, m_axi_arvalid, m_axi_arqos,
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m_axi_rready,
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// Inputs
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m_axi_aclk, m_axi_aresetn, m_axi_awready, m_axi_wready, m_axi_bid,
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m_axi_bresp, m_axi_bvalid, m_axi_arready, m_axi_rid, m_axi_rdata,
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m_axi_rresp, m_axi_rlast, m_axi_rvalid
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);
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// Parameters (connect to DUT slave)
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parameter SIDW = 12; //ID Width
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parameter SAW = 32; //Address Bus Width
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parameter SDW = 32; //Data Bus Width
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parameter SSTW = 8; //Number of strobes
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localparam DELAYSTART_W = 100;
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localparam DELAYSTART_R = 200;
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/*****************************/
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/*TESTBENCH SIGNALS */
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/*****************************/
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output ERROR;
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output DONE;
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/*****************************/
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/*AXI MASTER I/F */
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/*****************************/
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//Global signals
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input m_axi_aclk; //clock source for axi master/slave interfaces
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input m_axi_aresetn; //asynchronous reset signal, active low
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//Write address channel
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output [SIDW-1:0] m_axi_awid; //write address ID
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output [SAW-1:0] m_axi_awaddr; //write address
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output [3:0] m_axi_awlen; //burst length (number of data transfers)
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output [2:0] m_axi_awsize; //burst size (size of each transfer)
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output [1:0] m_axi_awburst; //burst type
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output [1:0] m_axi_awlock; //lock type (atomic characteristics)
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output [3:0] m_axi_awcache; //memory type
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output [2:0] m_axi_awprot; //protection type
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output m_axi_awvalid; //write address valid
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output [3:0] m_axi_awqos; //quality of service default 4'b0000
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input m_axi_awready; //write address ready
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//Write data channel
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output [SIDW-1:0] m_axi_wid; //write ID tag (supported only in AXI3)
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output [SDW-1:0] m_axi_wdata; //write data
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output [SSTW-1:0] m_axi_wstrb; //write strobes
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output m_axi_wlast; //indicates last write transfer in burst
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output m_axi_wvalid; //write valid
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input m_axi_wready; //write ready
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//Bufered write response channel
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input [SIDW-1:0] m_axi_bid; //response ID tag
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input [1:0] m_axi_bresp; //write response
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input m_axi_bvalid; //write response valid
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output m_axi_bready; //write ready
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//Read address channel
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output [SIDW-1:0] m_axi_arid; //read address ID
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output [SAW-1:0] m_axi_araddr; //read address
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output [3:0] m_axi_arlen; //burst length (number of data transfers)
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output [2:0] m_axi_arsize; //burst size (size of each transfer)
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output [1:0] m_axi_arburst; //burst type
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output [1:0] m_axi_arlock; //lock type (atomic characteristics)
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output [3:0] m_axi_arcache; //memory type
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output [2:0] m_axi_arprot; //protection type
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output m_axi_arvalid; //read address valid
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output [3:0] m_axi_arqos; //quality of service default 4'b0000
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input m_axi_arready; //read address ready
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//Read data channel
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input [SIDW-1:0] m_axi_rid; //read ID tag
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input [SDW-1:0] m_axi_rdata; //read data
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input [1:0] m_axi_rresp; //read response
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input m_axi_rlast; //indicates last read transfer in burst
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input m_axi_rvalid; //read valid
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output m_axi_rready; //read ready
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/***************************************/
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/* Extend local resets by delay values */
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/***************************************/
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reg resetn_w;
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reg resetn_r;
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integer count;
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always @ (posedge m_axi_aclk or negedge m_axi_aresetn) begin
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if(~m_axi_aresetn) begin
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resetn_w <= 1'b0;
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resetn_r <= 1'b0;
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count <= 0;
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end else begin
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count <= count + 1;
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if(count == DELAYSTART_W)
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resetn_w <= 1'b1;
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if(count == DELAYSTART_R)
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resetn_r <= 1'b1;
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end
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end
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/******************************/
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/* Write sequential addresses */
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/******************************/
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wire [SIDW-1:0] m_axi_awid = {SIDW{1'b0}}; // Fixed ID
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reg [SAW-1:0] m_axi_awaddr; // Incrementing Address
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wire [3:0] m_axi_awlen = 4'd0; // Single beat (no burst for now)
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wire [2:0] m_axi_awsize = 3'd2; // 4 Bytes / beat
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wire [1:0] m_axi_awburst = 2'd1; // Incrementing Burst Type
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wire [1:0] m_axi_awlock = 2'b00; // Normal access (AXI4 uses only 1 bit?)
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wire [3:0] m_axi_awcache = 4'b0011; // Modifiable, Bufferable, but not cacheable
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wire [2:0] m_axi_awprot = 3'b010; // Data, Non-secure, Unprivileged
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reg m_axi_awvalid; // Valid
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wire [3:0] m_axi_awqos = 4'd0; // Default QoS
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always @ (posedge m_axi_aclk or negedge resetn_w) begin
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if(~resetn_w) begin
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m_axi_awaddr <= {SAW{1'b0}};
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m_axi_awvalid <= 1'b0;
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end else begin
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m_axi_awvalid <= 1'b1;
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if(m_axi_awready)
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m_axi_awaddr <= m_axi_awaddr + 4;
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end
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end // TODO: Add optional gaps between 'valid's
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//Write data channel
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wire [SIDW-1:0] m_axi_wid = {SIDW{1'b0}}; // Fixed ID
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reg [SDW-1:0] m_axi_wdata; // Decrementing Data
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wire [SSTW-1:0] m_axi_wstrb = {SSTW{1'b1}}; // Byte Lanes
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wire m_axi_wlast = 1'b1; // Single beat per transfer, always last
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reg m_axi_wvalid;
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always @ (posedge m_axi_aclk or negedge resetn_w) begin
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if(~resetn_w) begin
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m_axi_wdata <= {SDW{1'b1}};
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m_axi_wvalid <= 1'b0;
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end else begin
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m_axi_wvalid <= 1'b1;
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if(m_axi_wready)
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m_axi_wdata <= m_axi_wdata - 1;
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end
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end
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//Buffered write response channel
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wire m_axi_bready = 1'b1; // always ready for now
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//Read address channel
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wire [SIDW-1:0] m_axi_arid = {SIDW{1'b0}}; // ID unused
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reg [SAW-1:0] m_axi_araddr;
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wire [3:0] m_axi_arlen = 4'd0; // Single beat per transfer
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wire [2:0] m_axi_arsize = 3'd2; // 4 bytes / beat
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wire [1:0] m_axi_arburst = 2'd1; // Incrementing Burst Type
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wire [1:0] m_axi_arlock = 2'b00; // Normal access (AXI4 uses only 1 bit?)
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wire [3:0] m_axi_arcache = 4'b0011; // Modifiable, Bufferable, but not cacheable
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wire [2:0] m_axi_arprot = 3'b010; // Data, Non-secure, Unprivileged
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reg m_axi_arvalid; //read address valid
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wire [3:0] m_axi_arqos = 4'd0; // Default QoS
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always @ (posedge m_axi_aclk or negedge resetn_r) begin
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if(~resetn_r) begin
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m_axi_araddr <= {SAW{1'b0}};
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m_axi_arvalid <= 1'b0;
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end else begin
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m_axi_arvalid <= 1'b1;
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if(m_axi_arready)
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m_axi_araddr <= m_axi_araddr + 8;
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end
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end // TODO: Add optional gaps between 'valid's
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//Read data channel
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wire m_axi_rready = 1'b1; // Always Ready for now
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endmodule // maxi_test
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// Local Variables:
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// verilog-library-directories:("." "../elink" "../axi")
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// End:
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