mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-24 11:35:00 +00:00
314 lines
19 KiB
XML
314 lines
19 KiB
XML
<?xml version="1.0" encoding="UTF-8"?>
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<!-- Product Version: Vivado v2014.3.1 (64-bit) -->
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<!-- -->
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<!-- Copyright 1986-2014 Xilinx, Inc. All Rights Reserved. -->
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<Project Version="7" Minor="2" Path="/home/aolofsson/Work_all/parallella-hw/fpga/vivado_projects/elink2new_testbench/elink2new_testbench.xpr">
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<DefaultLaunch Dir="$PRUNDIR"/>
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<Configuration>
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<Option Name="Id" Val="51f80e57f0364280a4f57fdaf16f1efa"/>
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<Option Name="Part" Val="xc7z020clg400-1"/>
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<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
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<Option Name="SimulatorLanguage" Val="Verilog"/>
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<Option Name="BoardPart" Val=""/>
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<Option Name="ActiveSimSet" Val="sim_3"/>
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<Option Name="DefaultLib" Val="xil_defaultlib"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../test/test_bench/ip_repo"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../hdl/elink-gold"/>
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<Option Name="IPRepoPath" Val="$PPRDIR/../../src"/>
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</Configuration>
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<FileSets Version="1" Minor="31">
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<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/elink2_top.bd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/hdl/elink2_top_wrapper.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/elink_testbench.bd">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../elink_testbench/elink_testbench.srcs/sources_1/bd/elink_testbench/elink_testbench.bd"/>
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<Attr Name="ImportTime" Val="1415202020"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_axi_protocol_converter_0_2/elink_testbench_axi_protocol_converter_0_2.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_axi_traffic_controller_0_1/elink_testbench_axi_traffic_controller_0_1.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_axi_bram_ctrl_0_1/elink_testbench_axi_bram_ctrl_0_1.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_elink_gold_0_0/elink_testbench_elink_gold_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_axi_protocol_converter_0_1/elink_testbench_axi_protocol_converter_0_1.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_axi_protocol_converter_0_0/elink_testbench_axi_protocol_converter_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_axi_traffic_controller_0_0/elink_testbench_axi_traffic_controller_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_axi_bram_ctrl_0_0/elink_testbench_axi_bram_ctrl_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_blk_mem_gen_0_0/elink_testbench_blk_mem_gen_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_emaxi_0_0/elink_testbench_emaxi_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_esaxi_0_0/elink_testbench_esaxi_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_fifo_103x32_0_2/elink_testbench_fifo_103x32_0_2.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_fifo_103x32_0_1/elink_testbench_fifo_103x32_0_1.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_eproto_rx_0_0/elink_testbench_eproto_rx_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_fifo_103x16_0_1/elink_testbench_fifo_103x16_0_1.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_fifo_103x16_0_0/elink_testbench_fifo_103x16_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_emesh_split_0_0/elink_testbench_emesh_split_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_eproto_tx_0_0/elink_testbench_eproto_tx_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_edistrib_0_0/elink_testbench_edistrib_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_earb_0_0/elink_testbench_earb_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_fifo_103x32_0_0/elink_testbench_fifo_103x32_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_fifo_generator_0_0/elink_testbench_fifo_generator_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_ecfg_split_0_0/elink_testbench_ecfg_split_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_eCfg_0_0/elink_testbench_eCfg_0_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_axi_traffic_controller_1_0/elink_testbench_axi_traffic_controller_1_0.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_eio_rx_0_2/elink_testbench_eio_rx_0_2.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_eio_tx_0_2/elink_testbench_eio_tx_0_2.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_eclock_0_2/elink_testbench_eclock_0_2.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_axi_bram_ctrl_2_2/elink_testbench_axi_bram_ctrl_2_2.xci"/>
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<CompFileExtendedInfo CompFileName="elink_testbench.bd" FileRelPathName="ip/elink_testbench_blk_mem_gen_0_1/elink_testbench_blk_mem_gen_0_1.xci"/>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_axi_bram_ctrl_0_0/elink_testbench_axi_bram_ctrl_0_0.upgrade_log">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../elink_testbench/elink_testbench.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_axi_bram_ctrl_0_0/elink_testbench_axi_bram_ctrl_0_0.upgrade_log"/>
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<Attr Name="ImportTime" Val="1414530388"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_blk_mem_gen_0_0/elink_testbench_blk_mem_gen_0_0.upgrade_log">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../elink_testbench/elink_testbench.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_blk_mem_gen_0_0/elink_testbench_blk_mem_gen_0_0.upgrade_log"/>
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<Attr Name="ImportTime" Val="1414530390"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_elink_gold_0_1/elink_testbench_elink_gold_0_1.upgrade_log">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../elink_testbench/elink_testbench.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_elink_gold_0_1/elink_testbench_elink_gold_0_1.upgrade_log"/>
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<Attr Name="ImportTime" Val="1415202180"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_elink_gold_0_0/elink_testbench_elink_gold_0_0.upgrade_log">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../elink_testbench/elink_testbench.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_elink_gold_0_0/elink_testbench_elink_gold_0_0.upgrade_log"/>
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<Attr Name="ImportTime" Val="1415137984"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_eio_tx_0_0/elink_testbench_eio_tx_0_0.upgrade_log">
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<FileInfo>
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<Attr Name="ImportPath" Val="$PPRDIR/../elink2_testbench/elink2_testbench.srcs/sources_1/bd/elink_testbench/ip/elink_testbench_eio_tx_0_0/elink_testbench_eio_tx_0_0.upgrade_log"/>
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<Attr Name="ImportTime" Val="1415358314"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_eCfg_0_2/elink_testbench_eCfg_0_2.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_eio_tx_0_2/elink_testbench_eio_tx_0_2.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_eclock_0_2/elink_testbench_eclock_0_2.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_eio_rx_0_2/elink_testbench_eio_rx_0_2.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_ecfg_split_0_0/elink_testbench_ecfg_split_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_eCfg_0_0/elink_testbench_eCfg_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_edistrib_0_0/elink_testbench_edistrib_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_eproto_rx_0_0/elink_testbench_eproto_rx_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_earb_0_0/elink_testbench_earb_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_eproto_tx_0_0/elink_testbench_eproto_tx_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_emaxi_0_0/elink_testbench_emaxi_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_esaxi_0_0/elink_testbench_esaxi_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink_testbench/ip/elink_testbench_emesh_split_0_0/elink_testbench_emesh_split_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_eproto_tx_0_0/elink2_top_eproto_tx_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_eio_rx_0_0/elink2_top_eio_rx_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_eio_tx_0_0/elink2_top_eio_tx_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_eclock_0_0/elink2_top_eclock_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_edistrib_0_0/elink2_top_edistrib_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_esaxi_0_0/elink2_top_esaxi_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_eproto_rx_0_0/elink2_top_eproto_rx_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_emaxi_0_0/elink2_top_emaxi_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_eCfg_0_0/elink2_top_eCfg_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_parallella_gpio_emio_0_0/elink2_top_parallella_gpio_emio_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sources_1/bd/elink2_top/ip/elink2_top_parallella_i2c_0_0/elink2_top_parallella_i2c_0_0.upgrade_log"/>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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</Config>
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</FileSet>
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<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
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<Filter Type="Constrs"/>
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<File Path="$PPRDIR/../../../boards/parallella-I/constraints/parallella_timing.xdc">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../../boards/parallella-I/constraints/parallella_z70x0_loc.xdc">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../../boards/parallella-I/constraints/parallella_z7020_loc.xdc">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="TargetConstrsFile" Val="$PPRDIR/../../../boards/parallella-I/constraints/parallella_timing.xdc"/>
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<Option Name="ConstrsType" Val="XDC"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../../test/elink_test/elink2new_tb.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="elink2_tb"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="SrcSet" Val="sources_1"/>
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<Option Name="XSimWcfgFile" Val="$PPRDIR/elink_tb_behav.wcfg"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_2" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_2">
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<Filter Type="Srcs"/>
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<File Path="$PSRCDIR/sim_2/bd/elink2_stream/elink2_stream.bd">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../test/elink_test/elink2stream_tb.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PSRCDIR/sim_2/bd/elink2_stream/ip/elink2_stream_eproto_rx_0_0/elink2_stream_eproto_rx_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sim_2/bd/elink2_stream/ip/elink2_stream_emaxi_0_0/elink2_stream_emaxi_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sim_2/bd/elink2_stream/ip/elink2_stream_esaxi_0_0/elink2_stream_esaxi_0_0.upgrade_log"/>
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<File Path="$PSRCDIR/sim_2/bd/elink2_stream/ip/elink2_stream_eCfg_0_0/elink2_stream_eCfg_0_0.upgrade_log"/>
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<Config>
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<Option Name="DesignMode" Val="RTL"/>
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<Option Name="TopModule" Val="elink2stream_tb"/>
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<Option Name="TopLib" Val="xil_defaultlib"/>
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<Option Name="TopAutoSet" Val="TRUE"/>
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<Option Name="SrcSet" Val="sources_1"/>
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</Config>
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</FileSet>
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<FileSet Name="sim_3" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_3">
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<Filter Type="Srcs"/>
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<File Path="$PPRDIR/../../test/elink_test/estream_tb.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../hdl/elink-gold/fifo_mem.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../hdl/elink-gold/fifo_full_block.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../hdl/elink-gold/fifo_empty_block.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../hdl/elink-gold/synchronizer.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../hdl/elink-gold/fifo.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../hdl/elink-gold/ewrapper_link_txo.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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<Attr Name="UsedIn" Val="implementation"/>
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<Attr Name="UsedIn" Val="simulation"/>
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</FileInfo>
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</File>
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<File Path="$PPRDIR/../../hdl/elink-gold/ewrapper_link_rxi.v">
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<FileInfo>
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<Attr Name="UsedIn" Val="synthesis"/>
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|
<Attr Name="UsedIn" Val="implementation"/>
|
|
<Attr Name="UsedIn" Val="simulation"/>
|
|
</FileInfo>
|
|
</File>
|
|
<Config>
|
|
<Option Name="DesignMode" Val="RTL"/>
|
|
<Option Name="TopModule" Val="estream_tb"/>
|
|
<Option Name="TopLib" Val="xil_defaultlib"/>
|
|
<Option Name="SrcSet" Val="sources_1"/>
|
|
</Config>
|
|
</FileSet>
|
|
</FileSets>
|
|
<Simulators>
|
|
<Simulator Name="XSim">
|
|
<Option Name="Description" Val="Vivado Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="ModelSim">
|
|
<Option Name="Description" Val="QuestaSim/ModelSim Simulator"/>
|
|
</Simulator>
|
|
<Simulator Name="IES">
|
|
<Option Name="Description" Val="Incisive Enterprise Simulator (IES)"/>
|
|
</Simulator>
|
|
<Simulator Name="VCS">
|
|
<Option Name="Description" Val="Verilog Compiler Simulator (VCS)"/>
|
|
</Simulator>
|
|
</Simulators>
|
|
<Runs Version="1" Minor="9">
|
|
<Run Id="synth_1" Type="Ft3:Synth" SrcSet="sources_1" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Synthesis Defaults" State="current">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Synthesis Defaults" Flow="Vivado Synthesis 2014"/>
|
|
<Step Id="synth_design"/>
|
|
</Strategy>
|
|
</Run>
|
|
<Run Id="impl_1" Type="Ft2:EntireDesign" Part="xc7z020clg400-1" ConstrsSet="constrs_1" Description="Vivado Implementation Defaults" State="current" SynthRun="synth_1">
|
|
<Strategy Version="1" Minor="2">
|
|
<StratHandle Name="Vivado Implementation Defaults" Flow="Vivado Implementation 2014"/>
|
|
<Step Id="init_design"/>
|
|
<Step Id="opt_design"/>
|
|
<Step Id="power_opt_design"/>
|
|
<Step Id="place_design"/>
|
|
<Step Id="post_place_power_opt_design"/>
|
|
<Step Id="phys_opt_design"/>
|
|
<Step Id="route_design"/>
|
|
<Step Id="post_route_phys_opt_design"/>
|
|
<Step Id="write_bitstream"/>
|
|
</Strategy>
|
|
</Run>
|
|
</Runs>
|
|
<HWSession Dir="hw_1" File="hw.xml"/>
|
|
<MsgRule>
|
|
<MsgAttr Name="RuleType" Val="0"/>
|
|
<MsgAttr Name="Limit" Val="-1"/>
|
|
<MsgAttr Name="NewSeverity" Val="ANY"/>
|
|
<MsgAttr Name="Id" Val=""/>
|
|
<MsgAttr Name="Severity" Val="INFO"/>
|
|
<MsgAttr Name="ShowRule" Val="1"/>
|
|
<MsgAttr Name="RuleSource" Val="16"/>
|
|
<MsgAttr Name="StringIsRegExp" Val="0"/>
|
|
</MsgRule>
|
|
</Project>
|