mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-21 19:08:55 +00:00
106 lines
3.7 KiB
INI
106 lines
3.7 KiB
INI
<?xml version="1.0"?>
|
|
<VDRC>
|
|
<FlowType Name="Netlist"/>
|
|
<GUI>
|
|
<Settings/>
|
|
<Rules>
|
|
<Group Name="Migration">
|
|
<Check Name="PropertyUnsupported"/>
|
|
<Check Name="NetNameInvalid"/>
|
|
<Check Name="PropertyValueInvalid"/>
|
|
<Check Name="CompNameInvalid"/>
|
|
<Check Name="PropertyNameTooLong"/>
|
|
<Check Name="PropertyValueTooLong"/>
|
|
<Check Name="NetNameTooLong"/>
|
|
<Check Name="CompNameTooLong"/>
|
|
</Group>
|
|
<Group Name="Connectivity">
|
|
<Check Name="ConOUTBI"/>
|
|
<Check Name="ConOUTTRI"/>
|
|
<Check Name="FanIn"/>
|
|
<Check Name="FanOut"/>
|
|
<Check Name="Undriven"/>
|
|
<Check Name="MultDriv"/>
|
|
<Check Name="UnconnectedPins"/>
|
|
<Check Name="ZeroPin"/>
|
|
<Check Name="UnrippedNet"/>
|
|
<Check Name="NetOverlap"/>
|
|
<Check Name="UndrivenCompPins"/>
|
|
<Check Name="InputsConnectedToConnector"/>
|
|
<Check Name="InputsConnectedToInputs"/>
|
|
<Check Name="DipoleToInput"/>
|
|
<Check Name="DipoleToBidirectional"/>
|
|
<Check Name="OutputDirectlyPG"/>
|
|
<Check Name="OutputSameComp"/>
|
|
<Check Name="InputSameComp"/>
|
|
<Check Name="DipolePinsShorted"/>
|
|
<Check Name="DipoleRangeMismatch"/>
|
|
<Check Name="ConnectivityChecks"/>
|
|
<Check Name="OnePinNet"/>
|
|
<Check Name="WidePin"/>
|
|
<Check Name="NetClass"/>
|
|
<Check Name="WidePinWidth"/>
|
|
</Group>
|
|
<Group Name="Electrical">
|
|
<Check Name="OclVDD"/>
|
|
<Check Name="OemGND"/>
|
|
<Check Name="VoltageDropCheck"/>
|
|
<Check Name="VoltageValueCheck"/>
|
|
<Check Name="PowerValueCheck"/>
|
|
<Check Name="TristatePinConnect"/>
|
|
</Group>
|
|
<Group Name="Hierarchy">
|
|
<Check Name="PinMatch"/>
|
|
<Check Name="NoNetSpn"/>
|
|
<Check Name="CompositeMissingSchematic"/>
|
|
<Check Name="DifferentHierarchicalConnected"/>
|
|
</Group>
|
|
<Group Name="Integrity">
|
|
<Check Name="SymMissingAttr"/>
|
|
<Check Name="SymPinMissingAttr"/>
|
|
<Check Name="BlockMissingAttr"/>
|
|
<Check Name="BlockPinMissingAttr"/>
|
|
<Check Name="PinSymHasNoPin"/>
|
|
<Check Name="PinSymHasTooManyPins"/>
|
|
<Check Name="OddNumber"/>
|
|
</Group>
|
|
<Group Name="Power&Ground">
|
|
<Check Name="DriveGlobal"/>
|
|
<Check Name="InvalidGlobal"/>
|
|
<Check Name="InvalidLocal"/>
|
|
<Check Name="GlobalSignals"/>
|
|
<Check Name="SupNegConnected"/>
|
|
<Check Name="SupNotConnected"/>
|
|
<Check Name="SupWrongConnected"/>
|
|
<Check Name="ImplicitPowerConnected"/>
|
|
<Check Name="BlockPinConnectedGlobal"/>
|
|
<Check Name="NumberConnDevice"/>
|
|
<Check Name="PowerGroundPinConnection"/>
|
|
</Group>
|
|
<Group Name="Device Specific">
|
|
<Check Name="ICDevice"/>
|
|
<Check Name="BusTranscPin"/>
|
|
<Check Name="OpAmpConnPower"/>
|
|
<Check Name="MultiPinCapacitor"/>
|
|
<Check Name="BufferOutputHardwired"/>
|
|
</Group>
|
|
<Group Name="HDL Checks">
|
|
<Check Name="VhdlReservedKeyword"/>
|
|
<Check Name="VerilogReservedKeyword"/>
|
|
<Check Name="VhdlDataTypeMismatch"/>
|
|
<Check Name="VhdlReadinOutput"/>
|
|
<Check Name="VhdlModelAvailability"/>
|
|
<Check Name="HierarchicalPortTypeMismatch"/>
|
|
<Check Name="HierarchicalPortNetMismatch"/>
|
|
<Check Name="HierarchicalModelPortModeMismatch"/>
|
|
</Group>
|
|
<Group Name="Links">
|
|
<Check Name="SheetLinksPointsNowhere"/>
|
|
<Check Name="UnnamedSheetLinks"/>
|
|
<Check Name="SheetLinksPointMultipleLocations"/>
|
|
<Check Name="LinkConnNetConsistency"/>
|
|
</Group>
|
|
</Rules>
|
|
</GUI>
|
|
</VDRC>
|