mirror of
https://github.com/parallella/parallella-hw.git
synced 2024-11-21 19:08:55 +00:00
62 lines
1.7 KiB
Plaintext
62 lines
1.7 KiB
Plaintext
SECTION DesignInfo
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LIST IndependentLibraries
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VALUE "DIR [W] . (parallella_rf)"
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VALUE "DIR [W] ..\wvlibs\alib_adi (alib_adi)"
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VALUE "DIR [W] ..\wvlibs\alib_analog (alib_analog)"
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VALUE "DIR [W] ..\wvlibs\alib_rlc (alib_rlc)"
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VALUE "DIR [W] ..\wvlibs\alib_conn (alib_conn)"
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VALUE "DIR [W] ..\wvlibs\alib_rf (alib_rf)"
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VALUE "DIR [W] ..\wvlibs\adapteva (adapteva)"
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VALUE "DIR [W] ..\wvlibs\alib_misc (alib_misc)"
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VALUE "DIR [W] ..\wvlibs\alib_power (alib_power)"
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VALUE "DIR [W] ..\wvlibs\special (special)"
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ENDLIST
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KEY BorderSymbols "./borders.ini"
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KEY Bus_Contents "./busconts.ini"
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KEY CentralLibrary ""
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KEY CnsFileName ""
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KEY FrontEndSnapshot "DxD"
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KEY LayoutID "PADS95"
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KEY PcbCfgFileName ""
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KEY PinComponents "./speccomp.ini"
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KEY SheetsEditMode "1"
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KEY DxD_Version "7.9.4"
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KEY NumberingType "VERTICAL"
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KEY OrderFileName ".\"
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KEY PropertyDefinitions "%SDD_HOME%\standard\netlist.prp"
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KEY PartListerCfg "C:\Starboard\Adapteva\adapteva-boards\parallella-rf\PartLister.ipl"
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ENDSECTION
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SECTION FlowSettings
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KEY FlowType "NETLIST"
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ENDSECTION
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SECTION ICXProInfo
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KEY ICXProDir "ICXPro"
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ENDSECTION
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SECTION ProjectBackup
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KEY ConfigFile ".\ProjectBackup\ProjectBackup.cfg"
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ENDSECTION
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SECTION Template_Design
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KEY CADBackAnno "0"
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KEY ConfigType "PCB"
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KEY SchematicConflict "FE"
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KEY SchematicDesignBackAnno "0"
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KEY SchematicDesignStatus "0"
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KEY SearchPathScheme "(Default)"
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ENDSECTION
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SECTION iCDB
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LIST Designs
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VALUE "Board1"
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ENDLIST
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KEY DedicatedServerName ""
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KEY iCDBDir ".\database"
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ENDSECTION
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SECTION Board1
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KEY CADBackAnno "0"
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KEY ConfigType "PCB"
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KEY SchematicConflict "FE"
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KEY SchematicDesignBackAnno "0"
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KEY SchematicDesignStatus "0"
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KEY SearchPathScheme "(Default)"
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KEY RootBlock "parallella-rf"
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ENDSECTION
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