mirror of
https://github.com/parallella/parallella-hw.git
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422 lines
10 KiB
Plaintext
422 lines
10 KiB
Plaintext
EESchema Schematic File Version 2
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LIBS:power
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LIBS:device
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LIBS:transistors
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LIBS:conn
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LIBS:linear
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LIBS:regul
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LIBS:74xx
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LIBS:cmos4000
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LIBS:adc-dac
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LIBS:memory
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LIBS:xilinx
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LIBS:special
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LIBS:microcontrollers
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LIBS:dsp
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LIBS:microchip
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LIBS:analog_switches
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LIBS:motorola
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LIBS:texas
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LIBS:intel
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LIBS:audio
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LIBS:interface
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LIBS:digital-audio
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LIBS:philips
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LIBS:display
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LIBS:cypress
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LIBS:siliconi
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LIBS:opto
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LIBS:atmel
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LIBS:contrib
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LIBS:valves
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LIBS:adapteva_kicad
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LIBS:paracard-template-cache
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EELAYER 24 0
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EELAYER END
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$Descr B 17000 11000
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encoding utf-8
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Sheet 1 6
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Title "Parallella Daughtercard"
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Date "09 May 2014"
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Rev "*"
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Comp "Adapteva, Inc., 1666 Massachusetts Ave., Lexington, MA, 02420"
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Comment1 "Top Level"
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Comment2 ""
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Comment3 ""
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Comment4 ""
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$EndDescr
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Wire Notes Line
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15100 3100 12200 3100
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Wire Notes Line
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12200 3100 12200 1550
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Wire Notes Line
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12200 1550 15100 1550
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Wire Notes Line
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15100 1550 15100 3100
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Wire Notes Line
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15100 5150 12200 5150
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Wire Notes Line
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12200 5150 12200 3600
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Wire Notes Line
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12200 3600 15100 3600
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Wire Notes Line
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15100 3600 15100 5150
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Text Notes 13150 2400 0 60 ~ 0
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Parallella Back Side\n(Connector Side)\n
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Wire Notes Line
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12500 1600 12500 1700
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Wire Notes Line
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12500 1700 12550 1750
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Wire Notes Line
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12550 1750 12900 1750
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Wire Notes Line
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12900 1750 12950 1700
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Wire Notes Line
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12950 1700 12950 1600
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Wire Notes Line
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12950 1600 12500 1600
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Wire Notes Line
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14350 1600 14350 1700
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Wire Notes Line
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14350 1700 14400 1750
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Wire Notes Line
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14400 1750 14750 1750
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Wire Notes Line
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14750 1750 14800 1700
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Wire Notes Line
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14800 1700 14800 1600
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Wire Notes Line
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14800 1600 14350 1600
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Wire Notes Line
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12500 2900 12500 3000
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Wire Notes Line
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12500 3000 12550 3050
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Wire Notes Line
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12550 3050 12900 3050
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Wire Notes Line
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12900 3050 12950 3000
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Wire Notes Line
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12950 3000 12950 2900
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Wire Notes Line
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12950 2900 12500 2900
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Wire Notes Line
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14350 2900 14350 3000
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Wire Notes Line
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14350 3000 14400 3050
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Wire Notes Line
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14400 3050 14750 3050
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Wire Notes Line
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14750 3050 14800 3000
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Wire Notes Line
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14800 3000 14800 2900
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Wire Notes Line
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14800 2900 14350 2900
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Text Notes 14450 1700 0 50 ~ 0
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NORTH
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Text Notes 14450 3000 0 50 ~ 0
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SOUTH
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Text Notes 12650 1700 0 50 ~ 0
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GPIO
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Text Notes 12600 3000 0 50 ~ 0
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POWER
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Text Notes 13000 2950 0 50 ~ 0
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1
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Text Notes 13000 3050 0 50 ~ 0
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2
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Text Notes 13000 1650 0 50 ~ 0
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1
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Text Notes 13000 1750 0 50 ~ 0
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2
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Text Notes 14850 1650 0 50 ~ 0
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1
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Text Notes 14850 1750 0 50 ~ 0
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2
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Text Notes 14850 2950 0 50 ~ 0
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1
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Text Notes 14850 3050 0 50 ~ 0
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2
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Text Notes 12350 1650 0 50 ~ 0
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59
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Text Notes 12350 1750 0 50 ~ 0
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60
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Text Notes 12350 2950 0 50 ~ 0
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59
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Text Notes 12350 3050 0 50 ~ 0
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60
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Text Notes 14200 1650 0 50 ~ 0
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59
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Text Notes 14200 1750 0 50 ~ 0
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60
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Text Notes 14200 2950 0 50 ~ 0
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59
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Text Notes 14200 3050 0 50 ~ 0
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60
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Wire Notes Line
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15100 1800 14750 1800
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Wire Notes Line
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14750 1800 14750 2100
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Wire Notes Line
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14750 2100 15100 2100
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Text Notes 15000 1650 0 50 ~ 0
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O
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Text Notes 12250 1650 0 50 ~ 0
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O
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Text Notes 12250 3050 0 50 ~ 0
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O
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Text Notes 15000 3050 0 50 ~ 0
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O
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Wire Notes Line
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12200 2900 12150 2900
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Wire Notes Line
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12150 2900 12150 2350
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Wire Notes Line
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12150 2350 12200 2350
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Wire Notes Line
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12200 1700 12150 1700
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Wire Notes Line
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12150 1700 12150 1900
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Wire Notes Line
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12150 1900 12200 1900
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Text Notes 14800 2000 0 50 ~ 0
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SDCARD
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Text Notes 12100 2800 1 50 ~ 0
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ETHERNET
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Text Notes 12100 1850 1 50 ~ 0
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DC
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Text Notes 13250 4500 0 60 ~ 0
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Daughtercard\nTop Side\n(Connectors on Back)
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Wire Notes Line
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12500 3650 12500 3750
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Wire Notes Line
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12500 3750 12550 3800
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Wire Notes Line
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12550 3800 12900 3800
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Wire Notes Line
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12900 3800 12950 3750
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Wire Notes Line
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12950 3750 12950 3650
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Wire Notes Line
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12950 3650 12500 3650
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Wire Notes Line
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14350 3650 14350 3750
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Wire Notes Line
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14350 3750 14400 3800
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Wire Notes Line
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14400 3800 14750 3800
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Wire Notes Line
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14750 3800 14800 3750
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Wire Notes Line
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14800 3750 14800 3650
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Wire Notes Line
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14800 3650 14350 3650
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Wire Notes Line
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12500 4950 12500 5050
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Wire Notes Line
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12500 5050 12550 5100
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Wire Notes Line
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12550 5100 12900 5100
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Wire Notes Line
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12900 5100 12950 5050
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Wire Notes Line
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12950 5050 12950 4950
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Wire Notes Line
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12950 4950 12500 4950
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Wire Notes Line
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14350 4950 14350 5050
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Wire Notes Line
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14350 5050 14400 5100
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Wire Notes Line
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14400 5100 14750 5100
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Wire Notes Line
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14750 5100 14800 5050
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Wire Notes Line
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14800 5050 14800 4950
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Wire Notes Line
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14800 4950 14350 4950
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Text Notes 14450 3750 0 50 ~ 0
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NORTH
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Text Notes 14450 5050 0 50 ~ 0
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SOUTH
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Text Notes 12650 3750 0 50 ~ 0
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GPIO
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Text Notes 12600 5050 0 50 ~ 0
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POWER
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Text Notes 13000 5000 0 50 ~ 0
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1
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Text Notes 13000 5100 0 50 ~ 0
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2
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Text Notes 13000 3700 0 50 ~ 0
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1
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Text Notes 13000 3800 0 50 ~ 0
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2
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Text Notes 14850 3700 0 50 ~ 0
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1
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Text Notes 14850 3800 0 50 ~ 0
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2
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Text Notes 14850 5000 0 50 ~ 0
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1
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Text Notes 14850 5100 0 50 ~ 0
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2
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Text Notes 12350 3700 0 50 ~ 0
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59
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Text Notes 12350 3800 0 50 ~ 0
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60
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Text Notes 12350 5000 0 50 ~ 0
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59
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Text Notes 12350 5100 0 50 ~ 0
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60
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Text Notes 14200 3700 0 50 ~ 0
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59
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Text Notes 14200 3800 0 50 ~ 0
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60
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Text Notes 14200 5000 0 50 ~ 0
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59
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Text Notes 14200 5100 0 50 ~ 0
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60
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Text Notes 15000 3700 0 50 ~ 0
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O
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Text Notes 12250 3700 0 50 ~ 0
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O
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Text Notes 12250 5100 0 50 ~ 0
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O
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Text Notes 15000 5100 0 50 ~ 0
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O
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Text Notes 13400 1500 0 60 ~ 0
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3.40"
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Text Notes 15250 2500 1 60 ~ 0
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2.15"
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Wire Notes Line
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12200 1500 12200 1400
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Wire Notes Line
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15100 1500 15100 1400
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Wire Notes Line
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12200 1450 13350 1450
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Wire Notes Line
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13700 1450 15100 1450
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Wire Notes Line
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15150 1550 15250 1550
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Wire Notes Line
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15150 3100 15250 3100
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Wire Notes Line
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15200 3100 15200 2550
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Wire Notes Line
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15200 2200 15200 1550
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Text Notes 11000 8750 0 80 ~ 0
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"Paracard" Daughtercard template for\nAdapteva Parallella-I.\nThis schematic and associated PCB\ndesign may be used as a starting point\nfor Parallella-I daughtercard design.\n\nThis work is licensed under Creative Commons Attribution-Share Alike 3.0\nUnprotected License. To view a copy of this license, visit \nhttp://creativecommons.org/licenses/by-sa/3.0/ or send a letter to \nCreative Commons, 171 Second Street, Suite 300, San Francisco, California,\n94105, USA.\n\nThis schematic is *NOT SUPPORTED* and DOES NOT constitute a reference design.\nOnly *community* support is allowed via resources at forums.parallella.org.\nTHERE IS NO WARRANTY FOR THIS DESIGN, TO THE EXTENT PERMITTED\nBY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE\nCOPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE DESIGN *AS IS*\nWITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING,\nBUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND\nFITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY\nOF PERFORMANCE OF THE DESIGN IS WITH YOU. SHOULD THE DESIGN PROVE\nDEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING,\nREPAIR OR CORRECTION.
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$Sheet
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S 3600 3050 1900 900
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U 53860B1E
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F0 "GPIO" 100
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F1 "paracard-gpio.sch" 60
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F2 "VGPIO" O L 3600 3250 60
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F3 "GPIO_N[0..23]" B R 5500 3250 60
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F4 "GPIO_P[0..23]" B R 5500 3350 60
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F5 "GPIO[0..47]" B R 5500 3650 60
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$EndSheet
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$Sheet
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S 8050 3050 1900 1500
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U 5386858E
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F0 "NORTH" 100
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F1 "paracard-elink.sch" 60
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F2 "VDDIO" O L 8050 3150 60
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F3 "RXI_FRAME_N" I L 8050 3650 60
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F4 "RXI_FRAME_P" I L 8050 3550 60
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F5 "RXO_WR_WAIT_N" O L 8050 4050 60
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F6 "RXO_WR_WAIT_P" O L 8050 3950 60
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F7 "TXI_WR_WAIT_N" I R 9950 4050 60
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F8 "TXI_WR_WAIT_P" I R 9950 3950 60
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F9 "TXI_RD_WAIT_N" I R 9950 3850 60
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F10 "TXI_RD_WAIT_P" I R 9950 3750 60
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F11 "RXI_LCLK_N" I L 8050 3450 60
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F12 "RXI_LCLK_P" I L 8050 3350 60
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F13 "RXO_RD_WAIT_N" O L 8050 3850 60
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F14 "RXO_RD_WAIT_P" O L 8050 3750 60
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F15 "TXO_FRAME_N" O R 9950 3650 60
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F16 "TXO_FRAME_P" O R 9950 3550 60
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F17 "TXO_LCLK_N" O R 9950 3450 60
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F18 "TXO_LCLK_P" O R 9950 3350 60
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F19 "RXI_DATA_N[0..7]" I L 8050 4350 60
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F20 "RXI_DATA_P[0..7]" I L 8050 4250 60
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F21 "TXO_DATA_P[0..7]" O R 9950 4250 60
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F22 "TXO_DATA_N[0..7]" O R 9950 4350 60
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$EndSheet
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$Sheet
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S 3600 4450 1900 2200
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U 538682E8
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F0 "POWER" 100
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F1 "paracard-power.sch" 60
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F2 "I2C_SDA" B R 5500 4600 60
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F3 "I2C_SCL" B R 5500 4700 60
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F4 "PROG_IO" B R 5500 4900 60
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F5 "UART_RX" I R 5500 5300 60
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F6 "UART_TX" O R 5500 5400 60
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F7 "USER_LED" O R 5500 5000 60
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F8 "RESET_N" B R 5500 5600 60
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F9 "VADC_P" I R 5500 5800 60
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F10 "JTAG_TDI" I L 3600 6200 60
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F11 "JTAG_TDO" O L 3600 6300 60
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F12 "DSP_FLAG" O R 5500 5100 60
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F13 "TURBO_MODE" O R 5500 6300 60
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F14 "SPDIF" O R 5500 6100 60
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F15 "JTAG_BOOT_EN" I L 3600 6100 60
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F16 "VADC_N" I R 5500 5900 60
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F17 "JTAG_TMS" I L 3600 6400 60
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F18 "JTAG_TCK" I L 3600 6500 60
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F19 "1P0V" I L 3600 5200 60
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F20 "VDD_DSP" I L 3600 5300 60
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F21 "1P35V" I L 3600 5400 60
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F22 "1P8V" I L 3600 5500 60
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F23 "VDD_ADJ" I L 3600 5600 60
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F24 "VDD_GPIO" I L 3600 5700 60
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F25 "2P5V" I L 3600 5800 60
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F26 "3P3V" I L 3600 5900 60
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F27 "SYS_5P0V" O L 3600 4600 60
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F28 "REG_EN[1..4]" I L 3600 5100 60
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F29 "DSP_YID[0..3]" I L 3600 4800 60
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F30 "DSP_XID[0..3]" I L 3600 4900 60
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F31 "SPARE" B R 5500 6400 60
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$EndSheet
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$Sheet
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S 3600 7450 1950 700
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U 5387F901
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F0 "MountingHoles" 100
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F1 "paracard-mtg.sch" 60
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F2 "SYS_5P0V" O L 3600 7600 60
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$EndSheet
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Text Notes 11950 3500 0 60 ~ 0
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POWER PAD
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Wire Notes Line
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12050 3500 12150 3600
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Wire Notes Line
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12150 3600 12150 3550
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Wire Notes Line
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12150 3600 12100 3600
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$Sheet
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S 8050 5150 1900 1500
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U 538E9511
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F0 "SOUTH" 100
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F1 "paracard-elink.sch" 60
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F2 "VDDIO" O L 8050 5250 60
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F3 "RXI_FRAME_N" I L 8050 5750 60
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F4 "RXI_FRAME_P" I L 8050 5650 60
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F5 "RXO_WR_WAIT_N" O L 8050 6150 60
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F6 "RXO_WR_WAIT_P" O L 8050 6050 60
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F7 "TXI_WR_WAIT_N" I R 9950 6150 60
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F8 "TXI_WR_WAIT_P" I R 9950 6050 60
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F9 "TXI_RD_WAIT_N" I R 9950 5950 60
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F10 "TXI_RD_WAIT_P" I R 9950 5850 60
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F11 "RXI_LCLK_N" I L 8050 5550 60
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F12 "RXI_LCLK_P" I L 8050 5450 60
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F13 "RXO_RD_WAIT_N" O L 8050 5950 60
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F14 "RXO_RD_WAIT_P" O L 8050 5850 60
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F15 "TXO_FRAME_N" O R 9950 5750 60
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F16 "TXO_FRAME_P" O R 9950 5650 60
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F17 "TXO_LCLK_N" O R 9950 5550 60
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F18 "TXO_LCLK_P" O R 9950 5450 60
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F19 "RXI_DATA_N[0..7]" I L 8050 6450 60
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F20 "RXI_DATA_P[0..7]" I L 8050 6350 60
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F21 "TXO_DATA_P[0..7]" O R 9950 6350 60
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F22 "TXO_DATA_N[0..7]" O R 9950 6450 60
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$EndSheet
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$EndSCHEMATC
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