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Parallella board design files
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Fred Huettig cf954a9169 Added external repo fpgahdl_xilinx from analog devices. 
Added helper scripts for external repo fetch & sparse checkout.
2014-05-16 14:54:00 -04:00
boards Added cclk gating on reset, added tx-disable bit. 2014-05-14 17:23:23 -04:00
fpga Added external repo fpgahdl_xilinx from analog devices. 2014-05-16 14:54:00 -04:00
.gitignore Added ability to change elink and gpio iostandards. 2014-04-18 16:06:42 -04:00
.gitmodules Added external repo fpgahdl_xilinx from analog devices. 2014-05-16 14:54:00 -04:00
COPYING Initial repository creation 2013-06-29 15:05:36 -04:00
README.md Minor update to readme. 2014-04-27 23:41:23 -04:00

README.md

parallella-hw

This repository contains the board design sources and FPGA HDL sources for the Parallella board and various accessories.

Directory Structure

boards/         -  Board design files, all projects
    archive/        - Older boards no longer supported,
        proto/          - Zedboard based prototype (Jan 2013)
        gen0/           - First Parallella board, too hot (Apr 2013)
        gen1.0/         - Solid board, but hdmi wiring bug (Oct 2013)
        gen1.1/         - Fully working board (Dec 2013)
    libraries/      - Shared schematic and PCB tools libraries
    parallella-I/   - Current Parallella-I board schematic and PCB source
        constraints/    - Constraints files for board-specific pin locations
        docs/           - Docs specific to each board
        firmware/       - Low-level firmware (fsbl, u-boot, etc.)
        mfg/            - Manufacturing files: Fab Gerbers, Assembly docs

fpga/           -  FPGA design files and projects
    bitstreams/     - Latest generated bitstreams
    edk/            - EDK sources
        parallella_7010_headless/ - EDK for headless 7010-based Parallella
        parallella_7020_headless/ - EDK for headless 7020-based Parallella
    externals/      - Container for external repositories used by our projects
    hdl/            - Verilog source files
        axi/            - General AXI interface modules
        clocks/         - Clock generation
        common/         - General-purpose synchronizers/muxs/debouncers/etc.
        elink/          - eLink modules
        fifos/          - technology-independent FIFO modules
        gpio/           - modules for GPIO pins
        parallella-I/   - Modules specific to the Parallella
    ip/             - Tool-specific IP generation (CoreGen) sources
    projects/       - One folder for each project
        parallella_7020_headless/
        parallella_7010_headless/
        parallella_64_7020_headless/

FPGA Project Build instructions

See README files in the individual project directories.

License

COPYING - GNU GENERAL PUBLIC LICENSE file