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So I mentioned that the pedal startup had gotten less reliable, and possibly blamed the DMA code. But let's start with the really obvious suspect: the 230.4MHz overclock and the resulting games we play with the flash frequency at bootloader startup. Yes, yes, overclocking is nice for CPU headroom when enabling lots of effects, but if it causes startup issues it's just a bad idea. So this changes the PLL feedback divider from 96 to 64. We keep the same post-dividers (5 and 1), so now instead of running at 12 MHz * 96 / 5 / 1 = 230.4 MHz we run at 12 MHz * 64 / 5 / 1 = 153.6 MHz which is basically not an overclock at all (ok, so it's technically 2.4% over the 150MHz standard clock frequency - sue me). [ Small aside: we could also do 12 MHz * 128 / 5 / 2 = 153.6 MHz which also would keep the VCO in the required range (1536MHz instead of 768MHz - the documented valid VCO range is 750-1600MHz). The RP2350 datasheet says that it would result in using more power for the VCO but less jitter. Less jitter would certainly be good, but I'm pretty sure we don't care: the only jitter we care about is really the BCLK one, and with the integer divisors everywhere it should be entirely unmeasurable. It's certainly not measurable by me. ] And we obviously keep the same BCLK frequency of 3.072MHz, which is now SYSCLK divided by 50 instead of divided by 75. And since we do the "two PIO cycles per BCLK" thing, the PIO divider is now 25 instead of 37.5. Which also then means that now the BCLK really should be a perfect 50:50 duty cycle. Does this fix the pedal bootup instability? Only time will tell, because it wasn't like it was a very common thing to begin with. But it's certainly the much safer thing to do, and it avoids the whole voodoo magic with PICO_EMBED_XIP_SETUP etc. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>