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The important one is the i2s decoding and encoding to do the audio interfacing with the TAC5112. But I'm also doing button debouncing and the rotary encoder quadrature decoding in PIO programs. There's also a PIO program for the WS2812 smart LED that I was using at one point. The current board doesn't actually use that, because it didn't fit the form factor, but I should probably go back to it at some point when I do a separate board for the stomp switch and associated LEDs. So right now I'm just doing plain PWM on flat-top 5mm single-color LEDs, but I think the WS2812 might make a comeback some day, so the PIO program for dealing with it remains. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
104 lines
2.6 KiB
Plaintext
104 lines
2.6 KiB
Plaintext
;
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; We want a target sample frequency of 48kHz, which
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; with 24-bit i2s data means a dot clock of 2.304MHz.
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;
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; We overclock the rp2354 slightly to 172.8MHz, which
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; is exactly 75x that dot clock frequency.
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;
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; We then use a PIO divider of 25, and make the PIO
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; program do 3 cycles per clock.
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;
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; This means that all dividers are nice integers and
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; there is no clock jitter due to any fractional cycles.
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;
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; i2s: FSYNC and each data bit is transmitted on the
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; falling edge of BCLK, so we set those bits the cycle
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; when BCLK goes low ("side 0") so that they are stable
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; on the rising edge ("side 1").
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;
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; The actual data is transmitted one cycle after FSYNC
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; goes low
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;
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.pio_version 1
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.program i2s_tx
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.fifo tx
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.clock_div 25
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.side_set 2
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.out 1 left
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.wrap_target
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pull noblock [1] side 0b00 ; cycle 0: FSYNC goes LOW
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set x,22 side 0b01
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loop_low:
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out pins,1 [1] side 0b00 ; cycles 1..23: DOUT wiggles
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jmp x-- loop_low side 0b01
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out pins,1 [1] side 0b10 ; cycle 24: FSYNC goes HIGH
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set x,22 side 0b11
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loop_high:
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nop [1] side 0b10 ; cycles 25-47
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jmp x-- loop_high side 0b11
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.wrap
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% c-sdk {
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//
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// 'pin' is BCLK (MCU output)
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// 'pin+1' is FSYNC (MCU output)
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// 'pin+2' is DIN (MCU output! It's DIN from the CODEC standpoint!)
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// 'pin+3' is DOUT (MCU input! It's DOUT from the CODEC standpoint!)
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//
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static inline void i2s_tx_program_init(PIO pio, uint sm, uint offset, uint pin)
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{
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pio_sm_config c = i2s_tx_program_get_default_config(offset);
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pio_gpio_init(pio, pin);
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pio_gpio_init(pio, pin+1);
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pio_gpio_init(pio, pin+2);
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pio_gpio_init(pio, pin+3);
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// three output pins, one input
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pio_sm_set_pindirs_with_mask(pio, sm, 0b0111 << pin, 0b1111 << pin);
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// BCLK and FSYNC using sideset
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sm_config_set_sideset_pin_base(&c, pin);
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// DOUT using 'OUT' instruction
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sm_config_set_out_pins(&c, pin+2, 1);
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// Load and run the program
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pio_sm_init(pio, sm, offset, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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.program i2s_rx
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.fifo rx
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.clock_div 25
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.in 1 left
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.wrap_target
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set x,23
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wait 0 jmppin [3] ; wait for FSYNC going low
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; then delay to sample in the middle of valid window
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loop_in:
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in pins,1 [1] ; read DIN and delay to make loop exactly 3 cycles
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jmp x-- loop_in
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push noblock [14] ; write result and delay before looping
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.wrap
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% c-sdk {
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static inline void i2s_rx_program_init(PIO pio, uint sm, uint offset, uint pin)
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{
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pio_sm_config c = i2s_rx_program_get_default_config(offset);
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sm_config_set_jmp_pin(&c, pin+1); // FSYNC
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sm_config_set_in_pins(&c, pin+3); // DOUT
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// Load and run the program
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pio_sm_init(pio, sm, offset, &c);
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pio_sm_set_enabled(pio, sm, true);
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}
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%}
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