147 lines
2.5 KiB
Markdown
147 lines
2.5 KiB
Markdown
# EEPROM definition
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This is the EEPROM definition. Please pay attention to the "Seeed update".
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## Fixed header
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```
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#magic number
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i2c mw 0x50 0x00.1 aa;
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i2c mw 0x50 0x01.1 55;
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i2c mw 0x50 0x02.1 33;
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i2c mw 0x50 0x03.1 ee;
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#type
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i2c mw 0x50 0x04.1 01;
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#payload size
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i2c mw 0x50 0x05.1 37;
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i2c mw 0x50 0x06.1 00;
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#BRD_INFO - fixed 10
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i2c mw 0x50 0x07.1 10;
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#fixed
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i2c mw 0x50 0x08.1 2e;
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i2c mw 0x50 0x09.1 00;
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#Board_Name - BEAGLEPLAY-A0-\0\0
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i2c mw 0x50 0x0a.1 42;
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i2c mw 0x50 0x0b.1 45;
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i2c mw 0x50 0x0c.1 41;
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i2c mw 0x50 0x0d.1 47;
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i2c mw 0x50 0x0e.1 4C;
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i2c mw 0x50 0x0f.1 45;
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i2c mw 0x50 0x10.1 50;
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i2c mw 0x50 0x11.1 4C;
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i2c mw 0x50 0x12.1 41;
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i2c mw 0x50 0x13.1 59;
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i2c mw 0x50 0x14.1 2D;
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i2c mw 0x50 0x15.1 41;
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i2c mw 0x50 0x16.1 30;
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i2c mw 0x50 0x17.1 2D;
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i2c mw 0x50 0x18.1 00;
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i2c mw 0x50 0x19.1 00;
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```
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## Major design revision
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It has been known that Linux and u-boot developers might use this in their boot process without forward compatibility. Only update this when
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there is a compatibility issue that must be handled in software.
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```
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#Design_Rev - 02
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i2c mw 0x50 0x1a.1 30;
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i2c mw 0x50 0x1b.1 32;
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```
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## Fixed
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```
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#PROC_Nbr - 0078 (SK)
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i2c mw 0x50 0x1c.1 30;
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i2c mw 0x50 0x1d.1 30;
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i2c mw 0x50 0x1e.1 37;
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i2c mw 0x50 0x1f.1 38;
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```
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## Minor design revision
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Please update this any time there is a hardware change, including PCB, mechanical, or BOM changes. This gives users the ability to search
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the documentation for what changed.
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Rev A1 (pilot): 01.02.00.01
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Rev A2 (production): 01.03.01.01
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```
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#Variant - 01
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i2c mw 0x50 0x20.1 30;
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i2c mw 0x50 0x21.1 31;
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#PCB_Rev - 03
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i2c mw 0x50 0x22.1 30;
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i2c mw 0x50 0x23.1 33;
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#SCHBOM_Rev - 01
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i2c mw 0x50 0x24.1 30;
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i2c mw 0x50 0x25.1 31;
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#SWR_Rev - 01
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i2c mw 0x50 0x26.1 30;
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i2c mw 0x50 0x27.1 31;
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```
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## BeagleBoard's vendor ID
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```
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#VendorID - 64
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i2c mw 0x50 0x28.1 36;
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i2c mw 0x50 0x29.1 34;
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```
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## Seeed to update regularly
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Be sure to update this on a for every single board
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```
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#Build_Week - 'WW - seeed update...
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i2c mw 0x50 0x2a.1 57;
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i2c mw 0x50 0x2b.1 57;
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#Build_Year - 23
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i2c mw 0x50 0x2c.1 32;
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i2c mw 0x50 0x2d.1 33;
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#BoardID - BBBBBB - Seeed update
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i2c mw 0x50 0x2e.1 42;
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i2c mw 0x50 0x2f.1 42;
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i2c mw 0x50 0x30.1 42;
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i2c mw 0x50 0x31.1 42;
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i2c mw 0x50 0x32.1 42;
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i2c mw 0x50 0x33.1 42;
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#Serial_Nbr - SSSS
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i2c mw 0x50 0x34.1 53;
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i2c mw 0x50 0x35.1 53;
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i2c mw 0x50 0x36.1 53;
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i2c mw 0x50 0x37.1 53;
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```
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# DDR
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```
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Type -
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i2c mw 0x50 0x38.1 11;
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Length -
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i2c mw 0x50 0x39.1 02;
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i2c mw 0x50 0x3a.1 00;
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DDR Contrl -
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i2c mw 0x50 0x3b.1 60;
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i2c mw 0x50 0x3c.1 7d;
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End frame -
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i2c mw 0x50 0x3d.1 fe;
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```
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