Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cninterface/sy58608u/entity/vhdl.vhd
2025-01-07 19:29:47 -08:00

17 lines
435 B
VHDL

-- generated by newgenasym Tue Jul 10 10:19:34 2012
library ieee;
use ieee.std_logic_1164.all;
use work.all;
entity SY58608U is
port (
\in\: IN STD_LOGIC;
\in*\: IN STD_LOGIC;
Q0: OUT STD_LOGIC;
\q0*\: OUT STD_LOGIC;
Q1: OUT STD_LOGIC;
\q1*\: OUT STD_LOGIC;
\vref-ac\: OUT STD_LOGIC;
VT: IN STD_LOGIC);
end SY58608U;