Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/oxflib/sf#2d0603fp015f#2d2/entity/verilog.v
2025-01-07 19:29:47 -08:00

14 lines
173 B
Verilog

// generated by newgenasym Fri Jun 21 09:22:43 2024
module \sf-0603fp015f-2 (\1 , \2 );
inout \1 ;
inout \2 ;
initial
begin
end
endmodule