32 lines
654 B
Verilog
32 lines
654 B
Verilog
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// generated by NetAssembler Version 16.5-S048 (v16-5-13DK) 9/23/2013
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// on Fri Jan 22 17:08:23 2016
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`timescale 1ns/1ns
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`define scale_fs * 0.000001000000000
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`define scale_ps * 0.001000000000000
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`define scale_ns * 1.000000000000000
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`define scale_us * 1000.000000000000000
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`define scale_ms * 1000000.000000000000000
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`define scale_sec * 1000000000.000000000000000
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`define scale_min * 60000000000.000000000000000
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`define scale_hr * 3600000000000.000000000000000
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module alias_vector (a, a);
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parameter size = 1;
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inout [size-1:0] a;
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endmodule
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module alias_bit (a, a);
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inout a;
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endmodule
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module glbl ();
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// Verilog global signals module
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endmodule
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