USB2SPDIF/board/hdl/worklib/sch/cfg_verilog/expand.cfg

7 lines
541 B
INI

config sch;
design usb2iterface_lib.sch:sim_sch_1;
liblist usb2iterface_lib, standard, connector, crystal_osc, diode, discrete, disp, itead_standard_lib, logic, mcu, misc_ic, \module , motor, mtg, opamp, others, ram_flash, regulator, relay, sensor, socket, sonic_socket, std, switch, transformer, transistor;
viewlist vlog_map, hw_map, swift_map, vlog_model, hw_model, swift_model, vlog_structural, vlog_rtl, vlog_behavioral, vlog_system, mcvlog, pic_1, picopt_1, tbl_1, sim_sch_1, sch_1, entity;
stoplist vlog_model, swift_model;
endconfig