USB2SPDIF/board/hdl/worklib/sch/sch_1/page1.csv

12 KiB

1FILE_TYPE = CONNECTIVITY;
2{Allegro Design Entry HDL 16.5-S056 (v16-5-13EB) 5/26/2014}
3;
4;
5ADVREF
6AD12BVREF
7DFSDP
8DFSDM
9DHSDM
10DHSDP
11XIN
12XOUT
13NRST
14TCK/SWCLK
15TMS/SWDIO
16TDO/TRACESWO
17TDI
18XIN32
19XOUT32
20JTAGSEL
21NRSTB
22TST
23ERASE
24FWUP
25;
26GNDUTMI
27GNDPLL
28GNDBU
29GNDANA
30GND3
31GND2
32GND1
33VDDUTMI
34VDDPLL
35VDDOUT
36VDDIO4
37VDDIO3
38VDDIO2
39VDDIO1
40VDDIN
41VDDCORE5
42VDDCORE4
43VDDCORE3
44VDDCORE2
45VDDCORE1
46VDDBU
47VDDANA
48VBG
49;
50PB24
51PB23
52PB22
53PB21
54PB20
55PB19
56PB18
57PB17
58PB16
59PB15
60PB14
61PB13
62PB12
63PB11
64PB10
65PB9
66PB8
67PB7
68PB6
69PB5
70PB4
71PB3
72PB2
73PB1
74PB0
75PA31
76PA30
77PA29
78PA28
79PA27
80PA26
81PA25
82PA24
83PA23/PGMD15
84PA22/PGMD14
85PA21/PGMD13
86PA20/PGMD12
87PA19/PGMD11
88PA18/PGMD10
89PA17/PGMD9
90PA16/PGMD8
91PA15/PGMD7
92PA14/PGMD6
93PA13/PGMD5
94PA12/PGMD4
95PA11/PGMD3
96PA10/PGMD2
97PA9/PGMD1
98PA8/PGMD0
99PA7/PGMM3
100PA6/PGMM2
101PA5/PGMM1
102PA4/PGMM0
103PA3/PGMNVALID
104PA2/PGMNOE
105PA1/PGMRDY
106PA0/PGMNCMD
107;
108;
109;
110;
111;
112;
113;
114;
115;
116;
117;
118;
119;
120;
121;
122;
123;
124;
125;
126;
127;
128;
129;
130;
131;
132;
133GND
134ID
135D+
136D-
137VBUS
138;
139;
140;
141;
142;
143;
144;
145;
146;
147;
148;
149;
150;
151;
1522
1531
154;
155;
1562
1571
158END.