14 KiB
14 KiB
| 1 | EVENTROUTER_HILO | 0 | 1 | WAKEUP0_L | Level detect mode for WAKEUP0 event | 0 | rw |
|---|---|---|---|---|---|---|---|
| 2 | EVENTROUTER_HILO | 1 | 1 | WAKEUP1_L | Level detect mode for WAKEUP1 event | 0 | rw |
| 3 | EVENTROUTER_HILO | 2 | 1 | WAKEUP2_L | Level detect mode for WAKEUP2 event | 0 | rw |
| 4 | EVENTROUTER_HILO | 3 | 1 | WAKEUP3_L | Level detect mode for WAKEUP3 event | 0 | rw |
| 5 | EVENTROUTER_HILO | 4 | 1 | ATIMER_L | Level detect mode for alarm timer event | 0 | rw |
| 6 | EVENTROUTER_HILO | 5 | 1 | RTC_L | Level detect mode for RTC event | 0 | rw |
| 7 | EVENTROUTER_HILO | 6 | 1 | BOD_L | Level detect mode for BOD event | 0 | rw |
| 8 | EVENTROUTER_HILO | 7 | 1 | WWDT_L | Level detect mode for WWDT event | 0 | rw |
| 9 | EVENTROUTER_HILO | 8 | 1 | ETH_L | Level detect mode for Ethernet event | 0 | rw |
| 10 | EVENTROUTER_HILO | 9 | 1 | USB0_L | Level detect mode for USB0 event | 0 | rw |
| 11 | EVENTROUTER_HILO | 10 | 1 | USB1_L | Level detect mode for USB1 event | 0 | rw |
| 12 | EVENTROUTER_HILO | 11 | 1 | SDMMC_L | Level detect mode for SD/MMC event | 0 | rw |
| 13 | EVENTROUTER_HILO | 12 | 1 | CAN_L | Level detect mode for C_CAN event | 0 | rw |
| 14 | EVENTROUTER_HILO | 13 | 1 | TIM2_L | Level detect mode for combined timer output 2 event | 0 | rw |
| 15 | EVENTROUTER_HILO | 14 | 1 | TIM6_L | Level detect mode for combined timer output 6 event | 0 | rw |
| 16 | EVENTROUTER_HILO | 15 | 1 | QEI_L | Level detect mode for QEI event | 0 | rw |
| 17 | EVENTROUTER_HILO | 16 | 1 | TIM14_L | Level detect mode for combined timer output 14 event | 0 | rw |
| 18 | EVENTROUTER_HILO | 19 | 1 | RESET_L | Level detect mode for Reset | 0 | rw |
| 19 | EVENTROUTER_EDGE | 0 | 1 | WAKEUP0_E | Edge/Level detect mode for WAKEUP0 event | 0 | rw |
| 20 | EVENTROUTER_EDGE | 1 | 1 | WAKEUP1_E | Edge/Level detect mode for WAKEUP1 event | 0 | rw |
| 21 | EVENTROUTER_EDGE | 2 | 1 | WAKEUP2_E | Edge/Level detect mode for WAKEUP2 event | 0 | rw |
| 22 | EVENTROUTER_EDGE | 3 | 1 | WAKEUP3_E | Edge/Level detect mode for WAKEUP3 event | 0 | rw |
| 23 | EVENTROUTER_EDGE | 4 | 1 | ATIMER_E | Edge/Level detect mode for alarm timer event | 0 | rw |
| 24 | EVENTROUTER_EDGE | 5 | 1 | RTC_E | Edge/Level detect mode for RTC event | 0 | rw |
| 25 | EVENTROUTER_EDGE | 6 | 1 | BOD_E | Edge/Level detect mode for BOD event | 0 | rw |
| 26 | EVENTROUTER_EDGE | 7 | 1 | WWDT_E | Edge/Level detect mode for WWDT event | 0 | rw |
| 27 | EVENTROUTER_EDGE | 8 | 1 | ETH_E | Edge/Level detect mode for Ethernet event | 0 | rw |
| 28 | EVENTROUTER_EDGE | 9 | 1 | USB0_E | Edge/Level detect mode for USB0 event | 0 | rw |
| 29 | EVENTROUTER_EDGE | 10 | 1 | USB1_E | Edge/Level detect mode for USB1 event | 0 | rw |
| 30 | EVENTROUTER_EDGE | 11 | 1 | SDMMC_E | Edge/Level detect mode for SD/MMC event | 0 | rw |
| 31 | EVENTROUTER_EDGE | 12 | 1 | CAN_E | Edge/Level detect mode for C_CAN event | 0 | rw |
| 32 | EVENTROUTER_EDGE | 13 | 1 | TIM2_E | Edge/Level detect mode for combined timer output 2 event | 0 | rw |
| 33 | EVENTROUTER_EDGE | 14 | 1 | TIM6_E | Edge/Level detect mode for combined timer output 6 event | 0 | rw |
| 34 | EVENTROUTER_EDGE | 15 | 1 | QEI_E | Edge/Level detect mode for QEI event | 0 | rw |
| 35 | EVENTROUTER_EDGE | 16 | 1 | TIM14_E | Edge/Level detect mode for combined timer output 14 event | 0 | rw |
| 36 | EVENTROUTER_EDGE | 19 | 1 | RESET_E | Edge/Level detect mode for Reset | 0 | rw |
| 37 | EVENTROUTER_CLR_EN | 0 | 1 | WAKEUP0_CLREN | Writing a 1 to this bit clears the event enable bit 0 in the ENABLE register | 0 | w |
| 38 | EVENTROUTER_CLR_EN | 1 | 1 | WAKEUP1_CLREN | Writing a 1 to this bit clears the event enable bit 1 in the ENABLE register | 0 | w |
| 39 | EVENTROUTER_CLR_EN | 2 | 1 | WAKEUP2_CLREN | Writing a 1 to this bit clears the event enable bit 2 in the ENABLE register | 0 | w |
| 40 | EVENTROUTER_CLR_EN | 3 | 1 | WAKEUP3_CLREN | Writing a 1 to this bit clears the event enable bit 3 in the ENABLE register | 0 | w |
| 41 | EVENTROUTER_CLR_EN | 4 | 1 | ATIMER_CLREN | Writing a 1 to this bit clears the event enable bit 4 in the ENABLE register | 0 | w |
| 42 | EVENTROUTER_CLR_EN | 5 | 1 | RTC_CLREN | Writing a 1 to this bit clears the event enable bit 5 in the ENABLE register | 0 | w |
| 43 | EVENTROUTER_CLR_EN | 6 | 1 | BOD_CLREN | Writing a 1 to this bit clears the event enable bit 6 in the ENABLE register | 0 | w |
| 44 | EVENTROUTER_CLR_EN | 7 | 1 | WWDT_CLREN | Writing a 1 to this bit clears the event enable bit 7 in the ENABLE register | 0 | w |
| 45 | EVENTROUTER_CLR_EN | 8 | 1 | ETH_CLREN | Writing a 1 to this bit clears the event enable bit 8 in the ENABLE register | 0 | w |
| 46 | EVENTROUTER_CLR_EN | 9 | 1 | USB0_CLREN | Writing a 1 to this bit clears the event enable bit 9 in the ENABLE register | 0 | w |
| 47 | EVENTROUTER_CLR_EN | 10 | 1 | USB1_CLREN | Writing a 1 to this bit clears the event enable bit 10 in the ENABLE register | 0 | w |
| 48 | EVENTROUTER_CLR_EN | 11 | 1 | SDMCC_CLREN | Writing a 1 to this bit clears the event enable bit 11 in the ENABLE register | 0 | w |
| 49 | EVENTROUTER_CLR_EN | 12 | 1 | CAN_CLREN | Writing a 1 to this bit clears the event enable bit 12 in the ENABLE register | 0 | w |
| 50 | EVENTROUTER_CLR_EN | 13 | 1 | TIM2_CLREN | Writing a 1 to this bit clears the event enable bit 13 in the ENABLE register | 0 | w |
| 51 | EVENTROUTER_CLR_EN | 14 | 1 | TIM6_CLREN | Writing a 1 to this bit clears the event enable bit 14 in the ENABLE register | 0 | w |
| 52 | EVENTROUTER_CLR_EN | 15 | 1 | QEI_CLREN | Writing a 1 to this bit clears the event enable bit 15 in the ENABLE register | 0 | w |
| 53 | EVENTROUTER_CLR_EN | 16 | 1 | TIM14_CLREN | Writing a 1 to this bit clears the event enable bit 16 in the ENABLE register | 0 | w |
| 54 | EVENTROUTER_CLR_EN | 19 | 1 | RESET_CLREN | Writing a 1 to this bit clears the event enable bit 19 in the ENABLE register | 0 | w |
| 55 | EVENTROUTER_SET_EN | 0 | 1 | WAKEUP0_SETEN | Writing a 1 to this bit sets the event enable bit 0 in the ENABLE register | 0 | w |
| 56 | EVENTROUTER_SET_EN | 1 | 1 | WAKEUP1_SETEN | Writing a 1 to this bit sets the event enable bit 1 in the ENABLE register | 0 | w |
| 57 | EVENTROUTER_SET_EN | 2 | 1 | WAKEUP2_SETEN | Writing a 1 to this bit sets the event enable bit 2 in the ENABLE register | 0 | w |
| 58 | EVENTROUTER_SET_EN | 3 | 1 | WAKEUP3_SETEN | Writing a 1 to this bit sets the event enable bit 3 in the ENABLE register | 0 | w |
| 59 | EVENTROUTER_SET_EN | 4 | 1 | ATIMER_SETEN | Writing a 1 to this bit sets the event enable bit 4 in the ENABLE register | 0 | w |
| 60 | EVENTROUTER_SET_EN | 5 | 1 | RTC_SETEN | Writing a 1 to this bit sets the event enable bit 5 in the ENABLE register | 0 | w |
| 61 | EVENTROUTER_SET_EN | 6 | 1 | BOD_SETEN | Writing a 1 to this bit sets the event enable bit 6 in the ENABLE register | 0 | w |
| 62 | EVENTROUTER_SET_EN | 7 | 1 | WWDT_SETEN | Writing a 1 to this bit sets the event enable bit 7 in the ENABLE register | 0 | w |
| 63 | EVENTROUTER_SET_EN | 8 | 1 | ETH_SETEN | Writing a 1 to this bit sets the event enable bit 8 in the ENABLE register | 0 | w |
| 64 | EVENTROUTER_SET_EN | 9 | 1 | USB0_SETEN | Writing a 1 to this bit sets the event enable bit 9 in the ENABLE register | 0 | w |
| 65 | EVENTROUTER_SET_EN | 10 | 1 | USB1_SETEN | Writing a 1 to this bit sets the event enable bit 10 in the ENABLE register | 0 | w |
| 66 | EVENTROUTER_SET_EN | 11 | 1 | SDMCC_SETEN | Writing a 1 to this bit sets the event enable bit 11 in the ENABLE register | 0 | w |
| 67 | EVENTROUTER_SET_EN | 12 | 1 | CAN_SETEN | Writing a 1 to this bit sets the event enable bit 12 in the ENABLE register | 0 | w |
| 68 | EVENTROUTER_SET_EN | 13 | 1 | TIM2_SETEN | Writing a 1 to this bit sets the event enable bit 13 in the ENABLE register | 0 | w |
| 69 | EVENTROUTER_SET_EN | 14 | 1 | TIM6_SETEN | Writing a 1 to this bit sets the event enable bit 14 in the ENABLE register | 0 | w |
| 70 | EVENTROUTER_SET_EN | 15 | 1 | QEI_SETEN | Writing a 1 to this bit sets the event enable bit 15 in the ENABLE register | 0 | w |
| 71 | EVENTROUTER_SET_EN | 16 | 1 | TIM14_SETEN | Writing a 1 to this bit sets the event enable bit 16 in the ENABLE register | 0 | w |
| 72 | EVENTROUTER_SET_EN | 19 | 1 | RESET_SETEN | Writing a 1 to this bit sets the event enable bit 19 in the ENABLE register | 0 | w |
| 73 | EVENTROUTER_STATUS | 0 | 1 | WAKEUP0_ST | A 1 in this bit shows that the WAKEUP0 event has been raised | 1 | r |
| 74 | EVENTROUTER_STATUS | 1 | 1 | WAKEUP1_ST | A 1 in this bit shows that the WAKEUP1 event has been raised | 1 | r |
| 75 | EVENTROUTER_STATUS | 2 | 1 | WAKEUP2_ST | A 1 in this bit shows that the WAKEUP2 event has been raised | 1 | r |
| 76 | EVENTROUTER_STATUS | 3 | 1 | WAKEUP3_ST | A 1 in this bit shows that the WAKEUP3 event has been raised | 1 | r |
| 77 | EVENTROUTER_STATUS | 4 | 1 | ATIMER_ST | A 1 in this bit shows that the ATIMER event has been raised | 1 | r |
| 78 | EVENTROUTER_STATUS | 5 | 1 | RTC_ST | A 1 in this bit shows that the RTC event has been raised | 1 | r |
| 79 | EVENTROUTER_STATUS | 6 | 1 | BOD_ST | A 1 in this bit shows that the BOD event has been raised | 1 | r |
| 80 | EVENTROUTER_STATUS | 7 | 1 | WWDT_ST | A 1 in this bit shows that the WWDT event has been raised | 1 | r |
| 81 | EVENTROUTER_STATUS | 8 | 1 | ETH_ST | A 1 in this bit shows that the ETH event has been raised | 1 | r |
| 82 | EVENTROUTER_STATUS | 9 | 1 | USB0_ST | A 1 in this bit shows that the USB0 event has been raised | 1 | r |
| 83 | EVENTROUTER_STATUS | 10 | 1 | USB1_ST | A 1 in this bit shows that the USB1 event has been raised | 1 | r |
| 84 | EVENTROUTER_STATUS | 11 | 1 | SDMMC_ST | A 1 in this bit shows that the SDMMC event has been raised | 1 | r |
| 85 | EVENTROUTER_STATUS | 12 | 1 | CAN_ST | A 1 in this bit shows that the CAN event has been raised | 1 | r |
| 86 | EVENTROUTER_STATUS | 13 | 1 | TIM2_ST | A 1 in this bit shows that the combined timer 2 output event has been raised | 1 | r |
| 87 | EVENTROUTER_STATUS | 14 | 1 | TIM6_ST | A 1 in this bit shows that the combined timer 6 output event has been raised | 1 | r |
| 88 | EVENTROUTER_STATUS | 15 | 1 | QEI_ST | A 1 in this bit shows that the QEI event has been raised | 1 | r |
| 89 | EVENTROUTER_STATUS | 16 | 1 | TIM14_ST | A 1 in this bit shows that the combined timer 14 output event has been raised | 1 | r |
| 90 | EVENTROUTER_STATUS | 19 | 1 | RESET_ST | A 1 in this bit shows that the reset event has been raised | 1 | r |
| 91 | EVENTROUTER_ENABLE | 0 | 1 | WAKEUP0_EN | A 1 in this bit shows that the WAKEUP0 event has been enabled | 0 | r |
| 92 | EVENTROUTER_ENABLE | 1 | 1 | WAKEUP1_EN | A 1 in this bit shows that the WAKEUP1 event has been enabled | 0 | r |
| 93 | EVENTROUTER_ENABLE | 2 | 1 | WAKEUP2_EN | A 1 in this bit shows that the WAKEUP2 event has been enabled | 0 | r |
| 94 | EVENTROUTER_ENABLE | 3 | 1 | WAKEUP3_EN | A 1 in this bit shows that the WAKEUP3 event has been enabled | 0 | r |
| 95 | EVENTROUTER_ENABLE | 4 | 1 | ATIMER_EN | A 1 in this bit shows that the ATIMER event has been enabled | 0 | r |
| 96 | EVENTROUTER_ENABLE | 5 | 1 | RTC_EN | A 1 in this bit shows that the RTC event has been enabled | 0 | r |
| 97 | EVENTROUTER_ENABLE | 6 | 1 | BOD_EN | A 1 in this bit shows that the BOD event has been enabled | 0 | r |
| 98 | EVENTROUTER_ENABLE | 7 | 1 | WWDT_EN | A 1 in this bit shows that the WWDT event has been enabled | 0 | r |
| 99 | EVENTROUTER_ENABLE | 8 | 1 | ETH_EN | A 1 in this bit shows that the ETH event has been enabled | 0 | r |
| 100 | EVENTROUTER_ENABLE | 9 | 1 | USB0_EN | A 1 in this bit shows that the USB0 event has been enabled | 0 | r |
| 101 | EVENTROUTER_ENABLE | 10 | 1 | USB1_EN | A 1 in this bit shows that the USB1 event has been enabled | 0 | r |
| 102 | EVENTROUTER_ENABLE | 11 | 1 | SDMMC_EN | A 1 in this bit shows that the SDMMC event has been enabled | 0 | r |
| 103 | EVENTROUTER_ENABLE | 12 | 1 | CAN_EN | A 1 in this bit shows that the CAN event has been enabled | 0 | r |
| 104 | EVENTROUTER_ENABLE | 13 | 1 | TIM2_EN | A 1 in this bit shows that the combined timer 2 output event has been enabled | 0 | r |
| 105 | EVENTROUTER_ENABLE | 14 | 1 | TIM6_EN | A 1 in this bit shows that the combined timer 6 output event has been enabled | 0 | r |
| 106 | EVENTROUTER_ENABLE | 15 | 1 | QEI_EN | A 1 in this bit shows that the QEI event has been enabled | 0 | r |
| 107 | EVENTROUTER_ENABLE | 16 | 1 | TIM14_EN | A 1 in this bit shows that the combined timer 14 output event has been enabled | 0 | r |
| 108 | EVENTROUTER_ENABLE | 19 | 1 | RESET_EN | A 1 in this bit shows that the reset event has been enabled | 0 | r |
| 109 | EVENTROUTER_CLR_STAT | 0 | 1 | WAKEUP0_CLRST | Writing a 1 to this bit clears the STATUS event bit 0 in the STATUS register | 0 | w |
| 110 | EVENTROUTER_CLR_STAT | 1 | 1 | WAKEUP1_CLRST | Writing a 1 to this bit clears the STATUS event bit 1 in the STATUS register | 0 | w |
| 111 | EVENTROUTER_CLR_STAT | 2 | 1 | WAKEUP2_CLRST | Writing a 1 to this bit clears the STATUS event bit 2 in the STATUS register | 0 | w |
| 112 | EVENTROUTER_CLR_STAT | 3 | 1 | WAKEUP3_CLRST | Writing a 1 to this bit clears the STATUS event bit 3 in the STATUS register | 0 | w |
| 113 | EVENTROUTER_CLR_STAT | 4 | 1 | ATIMER_CLRST | Writing a 1 to this bit clears the STATUS event bit 4 in the STATUS register | 0 | w |
| 114 | EVENTROUTER_CLR_STAT | 5 | 1 | RTC_CLRST | Writing a 1 to this bit clears the STATUS event bit 5 in the STATUS register | 0 | w |
| 115 | EVENTROUTER_CLR_STAT | 6 | 1 | BOD_CLRST | Writing a 1 to this bit clears the STATUS event bit 6 in the STATUS register | 0 | w |
| 116 | EVENTROUTER_CLR_STAT | 7 | 1 | WWDT_CLRST | Writing a 1 to this bit clears the STATUS event bit 7 in the STATUS register | 0 | w |
| 117 | EVENTROUTER_CLR_STAT | 8 | 1 | ETH_CLRST | Writing a 1 to this bit clears the STATUS event bit 8 in the STATUS register | 0 | w |
| 118 | EVENTROUTER_CLR_STAT | 9 | 1 | USB0_CLRST | Writing a 1 to this bit clears the STATUS event bit 9 in the STATUS register | 0 | w |
| 119 | EVENTROUTER_CLR_STAT | 10 | 1 | USB1_CLRST | Writing a 1 to this bit clears the STATUS event bit 10 in the STATUS register | 0 | w |
| 120 | EVENTROUTER_CLR_STAT | 11 | 1 | SDMCC_CLRST | Writing a 1 to this bit clears the STATUS event bit 11 in the STATUS register | 0 | w |
| 121 | EVENTROUTER_CLR_STAT | 12 | 1 | CAN_CLRST | Writing a 1 to this bit clears the STATUS event bit 12 in the STATUS register | 0 | w |
| 122 | EVENTROUTER_CLR_STAT | 13 | 1 | TIM2_CLRST | Writing a 1 to this bit clears the STATUS event bit 13 in the STATUS register | 0 | w |
| 123 | EVENTROUTER_CLR_STAT | 14 | 1 | TIM6_CLRST | Writing a 1 to this bit clears the STATUS event bit 14 in the STATUS register | 0 | w |
| 124 | EVENTROUTER_CLR_STAT | 15 | 1 | QEI_CLRST | Writing a 1 to this bit clears the STATUS event bit 15 in the STATUS register | 0 | w |
| 125 | EVENTROUTER_CLR_STAT | 16 | 1 | TIM14_CLRST | Writing a 1 to this bit clears the STATUS event bit 16 in the STATUS register | 0 | w |
| 126 | EVENTROUTER_CLR_STAT | 19 | 1 | RESET_CLRST | Writing a 1 to this bit clears the STATUS event bit 19 in the STATUS register | 0 | w |
| 127 | EVENTROUTER_SET_STAT | 0 | 1 | WAKEUP0_SETST | Writing a 1 to this bit sets the STATUS event bit 0 in the STATUS register | 0 | w |
| 128 | EVENTROUTER_SET_STAT | 1 | 1 | WAKEUP1_SETST | Writing a 1 to this bit sets the STATUS event bit 1 in the STATUS register | 0 | w |
| 129 | EVENTROUTER_SET_STAT | 2 | 1 | WAKEUP2_SETST | Writing a 1 to this bit sets the STATUS event bit 2 in the STATUS register | 0 | w |
| 130 | EVENTROUTER_SET_STAT | 3 | 1 | WAKEUP3_SETST | Writing a 1 to this bit sets the STATUS event bit 3 in the STATUS register | 0 | w |
| 131 | EVENTROUTER_SET_STAT | 4 | 1 | ATIMER_SETST | Writing a 1 to this bit sets the STATUS event bit 4 in the STATUS register | 0 | w |
| 132 | EVENTROUTER_SET_STAT | 5 | 1 | RTC_SETST | Writing a 1 to this bit sets the STATUS event bit 5 in the STATUS register | 0 | w |
| 133 | EVENTROUTER_SET_STAT | 6 | 1 | BOD_SETST | Writing a 1 to this bit sets the STATUS event bit 6 in the STATUS register | 0 | w |
| 134 | EVENTROUTER_SET_STAT | 7 | 1 | WWDT_SETST | Writing a 1 to this bit sets the STATUS event bit 7 in the STATUS register | 0 | w |
| 135 | EVENTROUTER_SET_STAT | 8 | 1 | ETH_SETST | Writing a 1 to this bit sets the STATUS event bit 8 in the STATUS register | 0 | w |
| 136 | EVENTROUTER_SET_STAT | 9 | 1 | USB0_SETST | Writing a 1 to this bit sets the STATUS event bit 9 in the STATUS register | 0 | w |
| 137 | EVENTROUTER_SET_STAT | 10 | 1 | USB1_SETST | Writing a 1 to this bit sets the STATUS event bit 10 in the STATUS register | 0 | w |
| 138 | EVENTROUTER_SET_STAT | 11 | 1 | SDMCC_SETST | Writing a 1 to this bit sets the STATUS event bit 11 in the STATUS register | 0 | w |
| 139 | EVENTROUTER_SET_STAT | 12 | 1 | CAN_SETST | Writing a 1 to this bit sets the STATUS event bit 12 in the STATUS register | 0 | w |
| 140 | EVENTROUTER_SET_STAT | 13 | 1 | TIM2_SETST | Writing a 1 to this bit sets the STATUS event bit 13 in the STATUS register | 0 | w |
| 141 | EVENTROUTER_SET_STAT | 14 | 1 | TIM6_SETST | Writing a 1 to this bit sets the STATUS event bit 14 in the STATUS register | 0 | w |
| 142 | EVENTROUTER_SET_STAT | 15 | 1 | QEI_SETST | Writing a 1 to this bit sets the STATUS event bit 15 in the STATUS register | 0 | w |
| 143 | EVENTROUTER_SET_STAT | 16 | 1 | TIM14_SETST | Writing a 1 to this bit sets the STATUS event bit 16 in the STATUS register | 0 | w |
| 144 | EVENTROUTER_SET_STAT | 19 | 1 | RESET_SETST | Writing a 1 to this bit sets the STATUS event bit 19 in the STATUS register | 0 | w |