Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cndiscrete/trans#20mosfet/entity/vhdl.vhd

-- generated by newgenasym Mon Oct 10 17:27:26 2016

library ieee;
use     ieee.std_logic_1164.all;
use     work.all;
entity \trans mosfet\ is
    port (    
	D:         INOUT  STD_LOGIC;    
	G:         INOUT  STD_LOGIC;    
	S:         INOUT  STD_LOGIC);
end \trans mosfet\;