Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cnpassive/capcersmdcl2/entity/verilog.v

// generated by newgenasym  Fri Apr 03 18:41:58 2015


module capcersmdcl2 (a, b);
    parameter    size = 1;
    inout [size-1:0] a;
    inout [size-1:0] b;


    initial
        begin
        end

endmodule