Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cnpassive/elcaptan/entity/verilog.v

// generated by newgenasym  Mon Jun 25 09:50:36 2012


module elcaptan (a, b);
    parameter    size = 1;
    inout [size-1:0] a;
    inout [size-1:0] b;


    initial
        begin
        end

endmodule