Cadence-DeHDL-Demo/hardware/Cadence/top/archive_libs/cnpower/p2v5/entity/verilog.v

// generated by newgenasym  Mon Dec 10 11:16:54 2001


module p2v5 (a);
    parameter    size = 1;
    inout [size-1:0] a;


    initial
        begin
        end

endmodule