20 lines
615 B
VHDL
20 lines
615 B
VHDL
-- generated by newgenasym Wed Jul 31 16:44:59 2019
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library ieee;
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use ieee.std_logic_1164.all;
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use work.all;
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entity mpm3632 is
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port (
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AGND: IN STD_LOGIC_VECTOR (1 DOWNTO 0);
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BST: INOUT STD_LOGIC;
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EN: INOUT STD_LOGIC;
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FB: INOUT STD_LOGIC;
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\out\: OUT STD_LOGIC;
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OUT_SENSE: OUT STD_LOGIC;
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PG: OUT STD_LOGIC;
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PGND: IN STD_LOGIC_VECTOR (3 DOWNTO 0);
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SW: OUT STD_LOGIC_VECTOR (2 DOWNTO 0);
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VCC: OUT STD_LOGIC;
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VIN: IN STD_LOGIC_VECTOR (1 DOWNTO 0));
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end mpm3632;
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