2025-03-13 16:54:52 -07:00

18 lines
240 B
Verilog

// generated by newgenasym Mon Sep 02 09:35:56 2019
module mpm3804 (en, fb, gnd, out, sw, vin);
inout en;
output fb;
input gnd;
output out;
output sw;
input vin;
initial
begin
end
endmodule