E2E @ 8c499679 - release v0.4.6 #179

Closed

shrikanthup wants to merge 2 commits from refs/pull/179/head into main

shrikanthup commented

2026-05-12 21:02:45 +00:00

(Migrated from staging.allspice.dev)

Source: release v0.4.6
PR: https://github.com/AllSpiceIO/connections-checker/pull/342
Ref: 8c499679acb7b022d84868cec76594459afa33d8
Mode: e2e
Cache: disabled
Cleanup: auto-closed after 7 days

Resolved config

{
  "dump_analysis_dir": "debug_dump",
  "libraries": [
    {
      "ipn_column": "IPN",
      "mpn_column": "MPN",
      "path": ".allspice/library.csv",
      "type": "csv"
    },
    {
      "digikey_client_id_env": "DIGIKEY_CLIENT_ID",
      "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET",
      "type": "digikey"
    }
  ]
}

Triggered at 2026-05-12T21:02:43.156519Z. Branch 752c00bd will be deleted on cleanup.

**Source:** release v0.4.6 **PR:** https://github.com/AllSpiceIO/connections-checker/pull/342 **Ref:** [`8c499679acb7b022d84868cec76594459afa33d8`](https://github.com/AllSpiceIO/connections-checker/tree/8c499679acb7b022d84868cec76594459afa33d8) **Mode:** e2e **Cache:** disabled **Cleanup:** auto-closed after 7 days <details> <summary>Resolved config</summary> ```json { "dump_analysis_dir": "debug_dump", "libraries": [ { "ipn_column": "IPN", "mpn_column": "MPN", "path": ".allspice/library.csv", "type": "csv" }, { "digikey_client_id_env": "DIGIKEY_CLIENT_ID", "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET", "type": "digikey" } ] } ``` </details> Triggered at 2026-05-12T21:02:43.156519Z. Branch `752c00bd` will be deleted on cleanup.

AllSpiceAlice commented

2026-05-12 21:36:27 +00:00

(Migrated from staging.allspice.dev)

DRCY has reviewed this Design Review, and there should be a review posted below.

AllSpiceAlice (Migrated from staging.allspice.dev) reviewed 2026-05-13 00:10:08 +00:00

AllSpiceAlice (Migrated from staging.allspice.dev) left a comment

DRCY Connections Checker Review

DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 374 component(s) to review, and found 12 potential issue(s) in 14 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

CPU1 - INTEL_ATOM_E3825_SOC ❌

DRCY flagged 2 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
BC1	VGA_DDCCLK	CRT_CLK	❌	VGA_DDCCLK and VGA_DDCDATA pins incorrectly connected through 150-ohm resistors to GND. DDC uses I2C protocol which requires pull-up resistors, not pull-downs. Pin BC1 is named VGA_DDCCLK and connects to net CRT_CLK (from schematic) Pin BC2 is named VGA_DDCDATA and connects to net CRT_DAT (from schematic) R39 (150 ohm) connects CRT_CLK pin 1 to GND pin 2 (from schematic) R38 (150 ohm) connects CRT_DAT pin 1 to GND pin 2 (from schematic) DDC (Display Data Channel) is an I2C-based protocol used for monitor communication and identification (reasoning) I2C protocol requires pull-up resistors on both SDA and SCL lines because they are open-drain signals (reasoning) Typical I2C pull-up resistor values range from 2.2K to 10K ohms connected to a positive voltage rail (typically 3.3V or 5V) (reasoning) Pull-down resistors on I2C lines prevent proper communication by holding the lines low, making it impossible for devices to drive the lines high (reasoning) The 150-ohm value is too low for I2C pull-ups and would draw excessive current even if connected to the correct rail (reasoning) These resistors should be changed to pull-up resistors connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) with values in the 2.2K-10K range (reasoning)
BC2	VGA_DDCDATA	CRT_DAT	❌	VGA_DDCCLK and VGA_DDCDATA pins incorrectly connected through 150-ohm resistors to GND. DDC uses I2C protocol which requires pull-up resistors, not pull-downs. Pin BC1 is named VGA_DDCCLK and connects to net CRT_CLK (from schematic) Pin BC2 is named VGA_DDCDATA and connects to net CRT_DAT (from schematic) R39 (150 ohm) connects CRT_CLK pin 1 to GND pin 2 (from schematic) R38 (150 ohm) connects CRT_DAT pin 1 to GND pin 2 (from schematic) DDC (Display Data Channel) is an I2C-based protocol used for monitor communication and identification (reasoning) I2C protocol requires pull-up resistors on both SDA and SCL lines because they are open-drain signals (reasoning) Typical I2C pull-up resistor values range from 2.2K to 10K ohms connected to a positive voltage rail (typically 3.3V or 5V) (reasoning) Pull-down resistors on I2C lines prevent proper communication by holding the lines low, making it impossible for devices to drive the lines high (reasoning) The 150-ohm value is too low for I2C pull-ups and would draw excessive current even if connected to the correct rail (reasoning) These resistors should be changed to pull-up resistors connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) with values in the 2.2K-10K range (reasoning)
AK12	DDI0_RCOMP_P	DDI_RCOMP_N	❌	DDI RCOMP pins appear to be swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative) connects to DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P) connects to DDI_RCOMP_N. The pin naming convention suggests these connections are reversed. Pin AK13 is named D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating active-low or negative signal (from datasheet 140-0004628) Pin AK12 is named DDI0_RCOMP_P with _P suffix indicating positive signal (from datasheet 140-0004628) In the schematic, pin AK13 connects to net DDI_RCOMP_P (from schematic) In the schematic, pin AK12 connects to net DDI_RCOMP_N (from schematic) The overline notation in pin names typically indicates the complement or negative signal in differential pairs (reasoning) The _P suffix typically indicates the positive signal in differential pairs (reasoning) Based on naming convention, AK13 should connect to the negative net and AK12 to the positive net (reasoning) R217 (402 ohm) is connected between DDI_RCOMP_N and DDI_RCOMP_P as a compensation resistor (from schematic) The connections should be corrected: AK13 to DDI_RCOMP_N and AK12 to DDI_RCOMP_P (reasoning)
AK13	~DDI0_RCOMP	DDI_RCOMP_P	❌	DDI RCOMP pins appear to be swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative) connects to DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P) connects to DDI_RCOMP_N. The pin naming convention suggests these connections are reversed. Pin AK13 is named D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating active-low or negative signal (from datasheet 140-0004628) Pin AK12 is named DDI0_RCOMP_P with _P suffix indicating positive signal (from datasheet 140-0004628) In the schematic, pin AK13 connects to net DDI_RCOMP_P (from schematic) In the schematic, pin AK12 connects to net DDI_RCOMP_N (from schematic) The overline notation in pin names typically indicates the complement or negative signal in differential pairs (reasoning) The _P suffix typically indicates the positive signal in differential pairs (reasoning) Based on naming convention, AK13 should connect to the negative net and AK12 to the positive net (reasoning) R217 (402 ohm) is connected between DDI_RCOMP_N and DDI_RCOMP_P as a compensation resistor (from schematic) The connections should be corrected: AK13 to DDI_RCOMP_N and AK12 to DDI_RCOMP_P (reasoning)
A29	RESERVED_A29	GPIO_NC13	✅	RESERVED_A29 pin connected to GPIO_NC13 net with 10K pull-down resistor R102 to ground. This configuration is appropriate for an unused or reserved GPIO pin.
B26	DDI0_BKLTCTL		✅	DDI0_BKLTCTL (backlight control) pin is unconnected. For HDMI output, backlight control is not needed.
B28	DDI0_VDDEN		✅	DDI0_VDDEN (VDD enable) pin is unconnected. For HDMI output, this control signal is not needed.
B30	GPIO_S0_NC12	$3N566	✅	GPIO_S0_NC12 pin connected to test point TP15 (marked DNI). This provides a test point for this GPIO signal.
C26	DDI0_DDCDATA	HDMI_DDCDAT	✅	DDI0_DDCDATA (HDMI DDC data) correctly connected to HDMI_DDCDAT net for HDMI monitor communication.
C27	DDI0_BKLTEN		✅	DDI0_BKLTEN (backlight enable) pin is unconnected. For HDMI output, backlight enable is not needed.
C28	DDI0_DDCCLK	HDMI_DDCCLK	✅	DDI0_DDCCLK (HDMI DDC clock) correctly connected to HDMI_DDCCLK net for HDMI monitor communication.
D27	DDI0_HPD	HDMI_HPD_B	✅	DDI0_HPD (HDMI hot plug detect) correctly connected to HDMI_HPD_B through inverter U39.
D28	RESERVED_D28		✅	MIPI CSI GPIO pins with no connections shown. Appropriate if camera interface is not used in this design.
F28	RESERVED_F28		✅	MIPI CSI GPIO pins with no connections shown. Appropriate if camera interface is not used in this design.
F32	RESERVED_F32		✅	MIPI CSI GPIO pins with no connections shown. Appropriate if camera interface is not used in this design.
F34	RESERVED_F34		✅	MIPI CSI GPIO pins with no connections shown. Appropriate if camera interface is not used in this design.
G30	DDI1_DDCCLK	GND	✅	DDI1_DDCCLK pin connected to GND. This is intentional as DDI1 port is disabled per the 'Bay Trail-M Remove eDP Port' note.
J30	DDI1_BKLTEN		✅	DDI1_BKLTEN pin is unconnected, consistent with disabled DDI1 port.
K30	DDI1_HPD	GND	✅	DDI1_HPD pin connected to GND. This is intentional as DDI1 port is disabled.
M30	DDI1_BKLTCTL		✅	DDI1_BKLTCTL pin is unconnected, consistent with disabled DDI1 port.
N30	DDI1_VDDEN		✅	DDI1_VDDEN pin is unconnected, consistent with disabled DDI1 port.
P14	RESERVED_P14	MCSI_RCOMP	✅	RESERVED_P14 pin connected to MCSI_RCOMP with 150 ohm resistor R213 to GND. This provides compensation for the MIPI CSI interface.
P30	DDI1_DDCDATA	DDI1_DDCDAT	✅	DDI1_DDCDATA pin connected through 2.2K resistor R257 to GND. This provides pull-down for the unused DDI1 DDC data line.
BA1	VGA_GREEN		✅	VGA_GREEN pin is unconnected. If VGA output is not used, this is acceptable.
AB2	RESERVED_AB2		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AB3	RESERVED_AB3		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AB7	RESERVED_AB7		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AB9	RESERVED_AB9		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AB12	RESERVED_AB12		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AB13	RESERVED_AB13		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AB14	RESERVED_AB14		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AD4	RESERVED_AD4		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AD6	RESERVED_AD6		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AF13	RESERVED_AF13		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AF14	RESERVED_AF14		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AH13	RESERVED_AH13		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AH14	RESERVED_AH14		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AM13	RESERVED_AM13		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
AM14	RESERVED_AM14		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
C29	RESERVED_C29		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
C30	RESERVED_C30		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
D32	RESERVED_D32		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
D34	RESERVED_D34		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
J28	RESERVED_J28		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
J34	RESERVED_J34		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
K28	RESERVED_K28		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
K34	RESERVED_K34		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
M32	RESERVED_M32		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
N32	RESERVED_N32		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
R1	RESERVED_R1		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
R3	RESERVED_R3		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
T2	RESERVED_T2		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
T3	RESERVED_T3		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
T4	RESERVED_T4		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
T6	RESERVED_T6		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
T7	RESERVED_T7		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
T9	RESERVED_T9		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
T10	RESERVED_T10		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
T12	RESERVED_T12		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
T13	RESERVED_T13		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
T14	RESERVED_T14		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
V2	RESERVED_V2		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
V3	RESERVED_V3		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
V4	RESERVED_V4		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
V6	RESERVED_V6		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
V9	RESERVED_V9		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
V10	RESERVED_V10		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
V13	RESERVED_V13		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
V14	RESERVED_V14		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
W1	RESERVED_W1		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
W3	RESERVED_W3		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
Y2	RESERVED_Y2		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
Y3	RESERVED_Y3		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
Y4	RESERVED_Y4		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
Y6	RESERVED_Y6		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
Y12	RESERVED_Y12		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
Y13	RESERVED_Y13		✅	Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise.
BA3	VGA_RED		✅	VGA_RED pin is unconnected. If VGA output is not used, this is acceptable.
AC1	DDI1_TXN_3		✅	DDI1_TXN_3 pin is unconnected. This is consistent with DDI1 port being disabled as indicated by the 'Bay Trail-M Remove eDP Port' note.
AC3	DDI1_TXP_3		✅	DDI1_TXP_3 pin is unconnected. This is consistent with DDI1 port being disabled.
AD2	DDI1_TXN_2		✅	DDI1_TXN_2 pin is unconnected, consistent with disabled DDI1 port.
AD3	DDI1_TXP_2		✅	DDI1_TXP_2 pin is unconnected, consistent with disabled DDI1 port.
BD2	VGA_HSYNC		✅	VGA_HSYNC pin is unconnected. If VGA output is not used, this is acceptable.
AF2	DDI1_TXN_1		✅	DDI1_TXN_1 pin is unconnected, consistent with disabled DDI1 port.
AF3	DDI1_TXP_1		✅	DDI1_TXP_1 pin is unconnected, consistent with disabled DDI1 port.
AG1	DDI1_TXN_0		✅	DDI1_TXN_0 pin is unconnected, consistent with disabled DDI1 port.
BF2	VGA_VSYNC		✅	VGA_VSYNC pin is unconnected. If VGA output is not used, this is acceptable.
AG3	DDI1_TXP_0		✅	DDI1_TXP_0 pin is unconnected, consistent with disabled DDI1 port.
AH2	RESERVED_VSS3	$3N554	✅	RESERVED_VSS3 pin connected through 0-ohm resistor R43 to GND. This is appropriate for a reserved ground pin.
AH3	RESERVED_VSS2	$3N552	✅	RESERVED_VSS2 pin connected through 0-ohm resistor R46 to GND. This is appropriate for a reserved ground pin.
AK2	DDI1_AUXN		✅	DDI1_AUXN pin is unconnected, consistent with disabled DDI1 port.
AK3	DDI1_AUXP		✅	DDI1_AUXP pin is unconnected, consistent with disabled DDI1 port.
AL1	DDI0_AUXN		✅	DDI0_AUXN pin is unconnected. For HDMI operation, the AUX channel is not required, so this is acceptable.
AL3	DDI0_AUXP		✅	DDI0_AUXP pin is unconnected. For HDMI operation, the AUX channel is not required, so this is acceptable.
AM2	RESERVED_VSS1	$3N589	✅	RESERVED_VSS1 pin connected through 0-ohm resistor R41 to GND. This is appropriate for a reserved ground pin.
AM3	RESERVED_VSS0	$3N579	✅	RESERVED_VSS0 pin connected through 0-ohm resistor R42 to GND. This is appropriate for a reserved ground pin.
AP2	DDI0_TXN_3	HDMI_CLK_DN	✅	DDI0_TXN_3 (HDMI clock negative) correctly connected to HDMI_CLK_DN net for HDMI output.
AP3	DDI0_TXP_3	HDMI_CLK_DP	✅	DDI0_TXP_3 (HDMI clock positive) correctly connected to HDMI_CLK_DP net for HDMI output.
AR1	DDI0_TXN_2	HDMI_TX0_DN	✅	DDI0_TXN_2 (HDMI data lane 0 negative) correctly connected to HDMI_TX0_DN net.
AR3	DDI0_TXP_2	HDMI_TX0_DP	✅	DDI0_TXP_2 (HDMI data lane 0 positive) correctly connected to HDMI_TX0_DP net.
AT2	DDI0_TXP_1	HDMI_TX1_DP	✅	DDI0_TXP_1 (HDMI data lane 1 positive) correctly connected to HDMI_TX1_DP net.
AT3	DDI0_TXN_1	HDMI_TX1_DN	✅	DDI0_TXN_1 (HDMI data lane 1 negative) correctly connected to HDMI_TX1_DN net.
AV2	DDI0_TXN_0	HDMI_TX2_DN	✅	DDI0_TXN_0 (HDMI data lane 2 negative) correctly connected to HDMI_TX2_DN net.
AV3	DDI0_TXP_0	HDMI_TX2_DP	✅	DDI0_TXP_0 (HDMI data lane 2 positive) correctly connected to HDMI_TX2_DP net.
AW1	VGA_IREF	$3N548	✅	VGA_IREF pin correctly connected through 357 ohm resistor R40 to GND to set the VGA DAC reference current.
AY2	VGA_BLUE		✅	VGA_BLUE pin is unconnected. If VGA output is not used, this is acceptable.
AY3	VGA_IRTN	GND	✅	VGA_IRTN (VGA current return) correctly connected to GND.

U39 - SN74LVC1G14DCKR ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	NC pin is left unconnected, which is acceptable per datasheet.
2	A	HDMI_HPD	✅	Input pin A receives HDMI_HPD signal for Schmitt-trigger inversion and noise immunity.
3	GND	GND	✅	Ground pin is correctly connected to the GND net.
4	Y	HDMI_HPD_B	✅	Output pin Y drives HDMI_HPD_B signal (inverted hot plug detect) to CPU1 DDI0_HPD input.
5	VCC	+V1P8S	✅	VCC pin is correctly powered from +V1P8S (1.8V) with nearby decoupling capacitor C375.

R38 - 110-0002631 ❌

DRCY flagged 1 potential issues in this component.

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CRT_DAT	❌	Pull-down resistor on VGA DDC data line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation. Pin 1 is connected to net CRT_DAT (from schematic) Pin 2 is connected to GND (from schematic) Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) (from schematic) This resistor acts as a pull-down on the VGA DDC data line (reasoning) DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning) I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning) Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning) If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning) If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning) The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)
2	2	GND	❌	Pull-down resistor on VGA DDC data line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation. Pin 1 is connected to net CRT_DAT (from schematic) Pin 2 is connected to GND (from schematic) Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) (from schematic) This resistor acts as a pull-down on the VGA DDC data line (reasoning) DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning) I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning) Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning) If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning) If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning) The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)

R39 - 110-0002631 ❌

DRCY flagged 1 potential issues in this component.

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CRT_CLK	❌	Pull-down resistor on VGA DDC clock line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation. Pin 1 is connected to net CRT_CLK (from schematic) Pin 2 is connected to GND (from schematic) Net CRT_CLK connects to CPU1 pin BC1 (VGA_DDCCLK) (from schematic) This resistor acts as a pull-down on the VGA DDC clock line (reasoning) DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning) I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning) Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning) If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning) If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning) The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)
2	2	GND	❌	Pull-down resistor on VGA DDC clock line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation. Pin 1 is connected to net CRT_CLK (from schematic) Pin 2 is connected to GND (from schematic) Net CRT_CLK connects to CPU1 pin BC1 (VGA_DDCCLK) (from schematic) This resistor acts as a pull-down on the VGA DDC clock line (reasoning) DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning) I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning) Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning) If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning) If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning) The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)

R213 - 150 ohm 1% 1/16W 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	MCSI_RCOMP	✅	150 ohm resistor connected between CPU1 pin P14 (RESERVED_P14/MCSI_RCOMP) and GND, providing compensation for MIPI CSI interface.
2	2	GND	✅	150 ohm resistor connected between CPU1 pin P14 (RESERVED_P14/MCSI_RCOMP) and GND, providing compensation for MIPI CSI interface.

R41 - RES_0Ohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0-ohm resistor connecting CPU1 RESERVED_VSS1 pin to ground, providing a separate ground connection for debugging and measurement.
2	2	$3N589	✅	0-ohm resistor connecting CPU1 RESERVED_VSS1 pin to ground, providing a separate ground connection for debugging and measurement.

R42 - RES_0Ohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0-ohm resistor connecting CPU1 RESERVED_VSS0 pin to ground, providing a separate ground connection for debugging and measurement.
2	2	$3N579	✅	0-ohm resistor connecting CPU1 RESERVED_VSS0 pin to ground, providing a separate ground connection for debugging and measurement.

R43 - RES_0Ohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$3N554	✅	0-ohm resistor connecting CPU1 RESERVED_VSS3 pin to ground, providing a separate ground connection for debugging and measurement.
2	2	GND	✅	0-ohm resistor connecting CPU1 RESERVED_VSS3 pin to ground, providing a separate ground connection for debugging and measurement.

R46 - RES_0Ohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$3N552	✅	0-ohm resistor connecting CPU1 RESERVED_VSS2 pin to ground, providing a separate ground connection for debugging and measurement.
2	2	GND	✅	0-ohm resistor connecting CPU1 RESERVED_VSS2 pin to ground, providing a separate ground connection for debugging and measurement.

R257 - 2.2K ohm 1% 1/10W 0402 ❌

DRCY flagged 1 potential issues in this component.

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDI1_DDCDAT	❌	Connected to DDI1_DDCDATA (CPU1 pin P30) with pull-down to ground. This implements an incorrect method for disabling the DDI1 interface - I2C data lines should not have pull-down resistors. Pin 1 is connected to net DDI1_DDCDAT (from schematic) Net DDI1_DDCDAT connects to CPU1 pin P30 (DDI1_DDCDATA) (from schematic) R257 pin 2 connects to GND, making this a pull-down resistor (from schematic) DDI1_DDCDATA is the Display Data Channel data line for Display Port 1, which uses I2C protocol (from datasheet 140-0004628) Other DDI1 pins are grounded: G30 (DDI1_DDCCLK) and K30 (DDI1_HPD) connect directly to GND (from schematic) Schematic note 'Bay Trail-M Remove eDP Port' indicates DDI1 is intentionally disabled (from schematic) I2C interfaces require pull-up resistors on clock and data lines for proper operation, not pull-down resistors (reasoning) A pull-down resistor on an I2C data line prevents proper I2C communication (reasoning) The datasheet recommends that unused I/O signals should be tri-stated (output driver disabled) and input receiver disabled through software configuration (from datasheet 140-0004628) Using external pull-down resistors is not the recommended method for disabling unused display ports per the datasheet (reasoning) If the port is properly disabled in software with tri-stated pins, external resistors are unnecessary (reasoning) The correct approach is to configure the pins as tri-stated in software and leave them unconnected or with appropriate termination per datasheet recommendations (reasoning)
2	2	GND	✅	Correctly connected to ground.

R102 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Resistor pin 1 correctly connected to GND to provide pull-down function.
2	2	GPIO_NC13	✅	Resistor pin 2 correctly connected to GPIO_NC13 net, providing 10K pull-down for CPU1 pin A29.

CPU1 - INTEL_ATOM_E3825_SOC ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
C24	~PROCHOT	VR_HOT_L	✅	PROCHOT thermal alert signal with 73.2Ω series resistor to 1.0V supply, configured for bidirectional operation.
N34	RESERVED_N34		✅	Reserved pin with no connection shown on this schematic page.
P34	RESERVED_P34		✅	Reserved pin with no connection shown on this schematic page.
BA12	SATA_GP0	SATA_GP0	✅	SATA general purpose I/O 0, correctly pulled down with 10KΩ resistor.
BA16	SATA_RXN_1	SATA1_RXN	✅	SATA port 1 receive negative signal, correctly AC-coupled for mSATA interface.
BA18	SD2_CLK		✅	SD2 interface clock signal, no connection shown on this page.
BA20	SD2_D2		✅	SD2 interface data bit 2, no connection shown on this page.
BA24	~MMC1_RST		✅	eMMC reset signal, no connection shown on this page.
BA26	SD3_D3	SD3_D3	✅	SD card data bit 3, no connection shown on this page.
BA30	LPE_I2S2_FRM	LPE_I2S_FRM	✅	LPE I2S frame sync signal with 10KΩ pullup, used for audio interface.
BB3	RESERVED_BB3		✅	Reserved pin with no connection shown on this schematic page.
BB4	RESERVED_BB4		✅	Reserved pin with no connection shown on this schematic page.
BB5	RESERVED_VSS6	RESERVED_VSS6	✅	Reserved VSS pin connected to ground through 0Ω resistor, platform-specific configuration.
BB7	RESERVED_VSS7	RESERVED_VSS7	✅	Reserved VSS pin connected to ground through 0Ω resistor, platform-specific configuration.
BB10	RESERVED_VSS4	ICLK_SATA_TERMP	✅	Reserved VSS pin connected to ground through 0Ω resistor via ICLK_SATA_TERMP net, Bay Trail-I specific configuration.
BC10	RESERVED_VSS5	ICLK_SATA_TERMN	✅	Reserved VSS pin connected to ground through 0Ω resistor via ICLK_SATA_TERMN net, Bay Trail-I specific configuration.
BC18	SD2_CMD		✅	SD2 interface command signal, no connection shown on this page.
BC24	SD3_CD#	SD3_CD#	✅	SD card detect signal connected to write protect pin via 0Ω resistor, platform-specific configuration.
BC30	LPE_I2S2_DATAOUT	LPE_I2S_DATOUT	✅	LPE I2S data output signal with optional pulldown and strap resistor, used for hardware configuration.
BD5	SD3_WP_BD5	SD3_WP	✅	SD card write protect signal connected to card detect via 0Ω resistor, Bay Trail-I specific configuration.
BD7	~PCIE_CLKREQ_1	CLKREQ1_B	✅	PCIe clock request 1 signal with 10KΩ pullup to 1.8V, correctly configured.
BD10	SATA_TXP1	SATA1_TXP	✅	SATA port 1 transmit positive signal, correctly AC-coupled for mSATA interface.
BD18	~SD2_D3_CD		✅	SD2 interface data bit 3 / card detect signal, no connection shown on this page.
BD20	SD2_D1		✅	SD2 interface data bit 1, no connection shown on this page.
BD22	~SD3_PWREN	/SD3+PWREN	✅	SD card power enable signal connected to test point, no active connection shown.
BD26	SD3_D1	SD3_D1	✅	SD card data bit 1, no connection shown on this page.
BD28	LPE_I2S2_DATAIN	LPE_I2S_DATIN	✅	LPE I2S data input signal, no connection shown on this page.
BE3	~PCIE_CLKREQ_3	mPCIe_CLKREQ3_B	✅	PCIe clock request 3 signal with 10KΩ pullup to 1.8V for mPCIe slot, correctly configured.
BF6	SATA_TXP_0	SATA0_TXP	✅	SATA port 0 transmit positive signal, correctly AC-coupled to SATA connector.
BF10	SATA_TXN_1	SATA1_TXN	✅	SATA port 1 transmit negative signal, correctly AC-coupled for mSATA interface.
BF20	HDA_LPE_RCOMP	HDA_RCOMP	✅	HD Audio / LPE compensation resistor, correctly connected to 49.9Ω resistor to ground.
BF22	SD3_1P8EN	SD3_1P8EN	✅	SD card 1.8V enable signal connected to test point, no active connection shown.
BF26	SD3_RCOMP	SD3_RCOMP	✅	SD card compensation resistor, correctly connected to 49.9Ω resistor to ground.
BF28	LPE_I2S2_CLK	LPE_I2S_CLK	✅	LPE I2S clock signal with 10KΩ pullup, used for audio interface.
BG3	~PCIE_CLKREQ_0	CLKREQ0_B	✅	PCIe clock request 0 signal with 10KΩ pullup to 1.8V, correctly configured.
BG5	~PCIE_CLKREQ_2	LAN_CLKREQ2_B	✅	PCIe clock request 2 signal with 10KΩ pullup to 1.8V for LAN controller, correctly configured.
BG7	SATA_TXN_0	SATA0_TXN	✅	SATA port 0 transmit negative signal, correctly AC-coupled to SATA connector.
BG18	GPIO_S0_SC_15		✅	General purpose I/O pin, no connection shown on this page.
BG19	HDA_SDI0		✅	HD Audio serial data input 0, no connection shown on this page.
BG20	HDA_SDO		✅	HD Audio serial data output, no connection shown on this page.
BG21	HDA_SDI1		✅	HD Audio serial data input 1, no connection shown on this page.
BG22	~HDA_RST		✅	HD Audio reset signal, no connection shown on this page.
BH18	GPIO_S0_SC_14		✅	General purpose I/O pin, no connection shown on this page.
BH20	HDA_SYNC		✅	HD Audio sync signal, no connection shown on this page.
AK7	RESERVED_AK7		✅	Reserved pin with no connection shown on this schematic page.
AK9	RESERVED_AK9		✅	Reserved pin with no connection shown on this schematic page.
BJ21	HDA_CLK		✅	HD Audio clock signal, no connection shown on this page.
AP4	PCIE_TXN_3	mPCIE_TX_N	✅	PCIe lane 3 transmit negative signal for mPCIe slot, no connection shown on this page.
AP6	PCIE_TXP_3	mPCIE_TX_P	✅	PCIe lane 3 transmit positive signal for mPCIe slot, no connection shown on this page.
AP7	PCIE_RXN_3	mPCIE_RX_N	✅	PCIe lane 3 receive negative signal for mPCIe slot, no connection shown on this page.
AP9	PCIE_RXP_3	mPCIE_RX_P	✅	PCIe lane 3 receive positive signal for mPCIe slot, no connection shown on this page.
AP10	PCIE_RXN_2	PCIE_RXN2	✅	PCIe lane 2 receive negative signal for LAN controller, no connection shown on this page.
AP12	PCIE_RXP_2	PCIE_RXP2	✅	PCIe lane 2 receive positive signal for LAN controller, no connection shown on this page.
AP13	PCIE_RCOMP_N_AP13_AP13	PCIE_RCOMP_N	✅	PCIe compensation resistor negative terminal, correctly connected to 402Ω resistor.
AP14	PCIE_RCOMP_P_AP14_AP14	PCIE_RCOMP_P	✅	PCIe compensation resistor positive terminal, correctly connected to 402Ω resistor.
AT6	PCIE_TXN_2	PCIE_TXN2	✅	PCIe lane 2 transmit negative signal for LAN controller, no connection shown on this page.
AT7	PCIE_TXP_2	PCIE_TXP2	✅	PCIe lane 2 transmit positive signal for LAN controller, no connection shown on this page.
AT9	PCIE_RXN_1		✅	PCIe lane 1 receive negative signal, no connection shown on this page.
AT10	PCIE_RXP_1		✅	PCIe lane 1 receive positive signal, no connection shown on this page.
AT13	PCIE_RXN_0		✅	PCIe lane 0 receive negative signal, no connection shown on this page.
AT14	PCIE_RXP_0		✅	PCIe lane 0 receive positive signal, no connection shown on this page.
AT18	SATA_RCOMP_N_AT18	SATA_RCOMP_N	✅	SATA compensation resistor negative terminal, correctly connected to 402Ω resistor.
AT20	MMC1_D3		✅	eMMC data bit 3, no connection shown on this page.
AT22	MMC1_CLK		✅	eMMC clock signal, no connection shown on this page.
AT26	MMC1_D6		✅	eMMC data bit 6, no connection shown on this page.
AT28	SD3_D0	SD3_D0	✅	SD card data bit 0, no connection shown on this page.
AU16	SATA_RXP_0	SATA0_RXP	✅	SATA port 0 receive positive signal, correctly AC-coupled to SATA connector.
AU18	SATA_RCOMP_P_AU18	SATA_RCOMP_P	✅	SATA compensation resistor positive terminal, correctly connected to 402Ω resistor.
AU20	MMC1_D7		✅	eMMC data bit 7, no connection shown on this page.
AU22	MMC1_D1		✅	eMMC data bit 1, no connection shown on this page.
AU26	MMC1_D5		✅	eMMC data bit 5, no connection shown on this page.
AU28	SD3_D2	SD3_D2	✅	SD card data bit 2, no connection shown on this page.
AV4	PCIE_TXN_1		✅	PCIe lane 1 transmit negative signal, no connection shown on this page.
AV6	PCIE_TXP_1		✅	PCIe lane 1 transmit positive signal, no connection shown on this page.
AV9	RESERVED_AV9		✅	Reserved pin with no connection shown on this schematic page.
AV10	RESERVED_AV10		✅	Reserved pin with no connection shown on this schematic page.
AV16	SATA_RXN_0	SATA0_RXN	✅	SATA port 0 receive negative signal, correctly AC-coupled to SATA connector.
AV20	MMC1_D0		✅	eMMC data bit 0, no connection shown on this page.
AV22	MMC1_D2		✅	eMMC data bit 2, no connection shown on this page.
AV26	MMC1_CMD		✅	eMMC command signal, no connection shown on this page.
AV28	SD3_CMD	SD3_CMD	✅	SD card command signal, no connection shown on this page.
AY6	PCIE_TXN_0		✅	PCIe lane 0 transmit negative signal, no connection shown on this page.
AY7	PCIE_TXP_0		✅	PCIe lane 0 transmit positive signal, no connection shown on this page.
AY12	~SATA_LED	SATA_LED_B	✅	SATA LED output signal, correctly connected through current-limiting resistor to LED jumper.
AY14	SATA_GP1	SATA_GP1	✅	SATA general purpose I/O 1, correctly pulled down with 10KΩ resistor.
AY16	SATA_RXP_1	SATA1_RXP	✅	SATA port 1 receive positive signal, correctly AC-coupled for mSATA interface.
AY18	MMC1_RCOMP	MMC1_RCOMP	✅	eMMC compensation resistor, correctly connected to 49.9Ω resistor to ground.
AY20	SD2_D0		✅	SD2 interface data bit 0, no connection shown on this page.
AY24	MMC1_D4		✅	eMMC data bit 4, no connection shown on this page.
AY26	SD3_CLK	SD3_CLK	✅	SD card clock signal, no connection shown on this page.

J3 - HDR_7POS_SER_GOLD_SATA_R/A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND net, providing signal return path for SATA differential pairs.
2	2	SATA0_TXP_C	✅	Transmit positive signal correctly connected through AC coupling capacitor C10 to CPU SATA0_TXP output.
3	3	SATA0_TXN_C	✅	Transmit negative signal correctly connected through AC coupling capacitor C11 to CPU SATA0_TXN output.
4	4	GND	✅	Ground pin correctly connected to GND net, providing isolation between TX and RX differential pairs.
5	5	SATA0_RXN_C	✅	Receive negative signal correctly connected through AC coupling capacitor C12 to CPU SATA0_RXN input.
6	6	SATA0_RXP_C	✅	Receive positive signal correctly connected through AC coupling capacitor C13 to CPU SATA0_RXP input.
7	7	GND	✅	Ground pin correctly connected to GND net, completing the ground structure for the SATA interface.
8	MH1	GND_EARTH	✅	Mounting hole correctly connected to GND_EARTH for chassis grounding and EMI shielding.
9	MH2	GND_EARTH	✅	Mounting hole correctly connected to GND_EARTH for chassis grounding and EMI shielding.

C10 - 0.01uF 10% 25V 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_TXP_C	✅	AC coupling capacitor correctly placed on SATA transmit positive line between CPU and connector.
2	2	SATA0_TXP	✅	AC coupling capacitor correctly placed on SATA transmit positive line between CPU and connector.

C11 - 0.01uF 10% 25V 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_TXN_C	✅	AC coupling capacitor correctly placed on SATA transmit negative line between CPU and connector.
2	2	SATA0_TXN	✅	AC coupling capacitor correctly placed on SATA transmit negative line between CPU and connector.

C12 - 0.01uF 10% 25V 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_RXN_C	✅	AC coupling capacitor correctly placed on SATA receive negative line between connector and CPU.
2	2	SATA0_RXN	✅	AC coupling capacitor correctly placed on SATA receive negative line between connector and CPU.

C13 - 0.01uF 10% 25V 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA0_RXP_C	✅	AC coupling capacitor correctly placed on SATA receive positive line between connector and CPU.
2	2	SATA0_RXP	✅	AC coupling capacitor correctly placed on SATA receive positive line between connector and CPU.

R239 - 402 ohm 1% 1/4W 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA_RCOMP_N	✅	RCOMP resistor correctly connected between SATA_RCOMP_P and SATA_RCOMP_N for PHY impedance calibration.
2	2	SATA_RCOMP_P	✅	RCOMP resistor correctly connected between SATA_RCOMP_P and SATA_RCOMP_N for PHY impedance calibration.

C148 - 8200pF 10% 1KV 1808 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND_EARTH	✅	NOVA safety capacitor marked DNI, providing optional isolation between chassis ground and signal ground for EMI/safety compliance.
2	2	GND	✅	NOVA safety capacitor marked DNI, providing optional isolation between chassis ground and signal ground for EMI/safety compliance.

C177 - 123-0001038 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_RX_N	✅	AC coupling capacitor for SATA1 receive negative differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component.
2	2	SATA1_RXN	✅	AC coupling capacitor for SATA1 receive negative differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component.

C179 - 123-0001038 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_TX_P	✅	AC coupling capacitor for SATA1 transmit positive differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component.
2	2	SATA1_TXP	✅	AC coupling capacitor for SATA1 transmit positive differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component.

C178 - 123-0001038 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_RX_P	✅	AC coupling capacitor for SATA1 receive positive differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component.
2	2	SATA1_RXP	✅	AC coupling capacitor for SATA1 receive positive differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component.

C180 - 123-0001038 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mSATA_TX_N	✅	AC coupling capacitor for SATA1 transmit negative differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component.
2	2	SATA1_TXN	✅	AC coupling capacitor for SATA1 transmit negative differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component.

R179 - 110-0001960 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SATA_LED_B	✅	Connected to SATA_LED_B net from CPU1 pin AY12, which is the active-low SATA LED output signal.
2	2	SATA_LED_R	✅	Connected to SATA_LED_R net, which routes to jumper J6 pin 2 for optional pull-up configuration.

J6 - HDR_2POS_DUAL_TIN ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Connected to +V1P8S supply rail, providing 1.8V pull-up voltage when jumper is installed.
2	2	SATA_LED_R	✅	Connected to SATA_LED_R net from R179, completing the jumper-selectable pull-up circuit.

R220 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing the ground reference for the pull-down resistor.
2	2	SATA_GP0	✅	Connected to SATA_GP0 net from CPU1 pin BA12, providing pull-down for SATA general purpose pin.

R221 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, providing the ground reference for the pull-down resistor.
2	2	SATA_GP1	✅	Connected to SATA_GP1 net from CPU1 pin AY14, providing pull-down for SATA general purpose pin.

R218 - 110-0004476 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PCIE_RCOMP_P	✅	402 ohm resistor connected between PCIE_RCOMP_P (pin 1) and PCIE_RCOMP_N (pin 2), serving as the PCIe compensation resistor for the CPU.
2	2	PCIE_RCOMP_N	✅	402 ohm resistor connected between PCIE_RCOMP_P (pin 1) and PCIE_RCOMP_N (pin 2), serving as the PCIe compensation resistor for the CPU.

R72 - 110-0001853 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESERVED_VSS6	✅	0 ohm resistor connecting RESERVED_VSS6 (pin 1) to GND (pin 2), providing a ground connection for a reserved VSS pin on the CPU.
2	2	GND	✅	0 ohm resistor connecting RESERVED_VSS6 (pin 1) to GND (pin 2), providing a ground connection for a reserved VSS pin on the CPU.

R192 - 110-0001853 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	RESERVED_VSS7	✅	0 ohm resistor connecting RESERVED_VSS7 (pin 1) to GND (pin 2), providing a ground connection for another reserved VSS pin on the CPU.
2	2	GND	✅	0 ohm resistor connecting RESERVED_VSS7 (pin 1) to GND (pin 2), providing a ground connection for another reserved VSS pin on the CPU.

R73 - 110-0001853 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0 ohm resistor connecting GND (pin 1) to ICLK_SATA_TERMP (pin 2), providing termination for the SATA interface on the CPU.
2	2	ICLK_SATA_TERMP	✅	0 ohm resistor connecting GND (pin 1) to ICLK_SATA_TERMP (pin 2), providing termination for the SATA interface on the CPU.

R74 - 110-0001853 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	0 ohm resistor connecting GND (pin 1) to ICLK_SATA_TERMN (pin 2), providing termination for the SATA interface on the CPU.
2	2	ICLK_SATA_TERMN	✅	0 ohm resistor connecting GND (pin 1) to ICLK_SATA_TERMN (pin 2), providing termination for the SATA interface on the CPU.

R190 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CLKREQ1_B	✅	Connected to CLKREQ1_B signal from CPU1 pin BD7. This is a pull-up resistor for the PCIe clock request signal.
2	2	+V1P8S	✅	Connected to +V1P8S supply rail, providing pull-up voltage for the CLKREQ1_B signal.

R2 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	mPCIe_CLKREQ3_B	✅	Connected to mPCIe_CLKREQ3_B signal from CPU1 pin BE3. This is a pull-up resistor for the PCIe clock request signal used by the mini-PCIe slot.
2	2	+V1P8S	✅	Connected to +V1P8S supply rail, providing pull-up voltage for the mPCIe_CLKREQ3_B signal.

R191 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	CLKREQ0_B	✅	Connected to CLKREQ0_B signal from CPU1 pin BG3. This is a pull-up resistor for the PCIe clock request signal.
2	2	+V1P8S	✅	Connected to +V1P8S supply rail, providing pull-up voltage for the CLKREQ0_B signal.

R71 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_CLKREQ2_B	✅	Connected to LAN_CLKREQ2_B signal from CPU1 pin BG5. This is a pull-up resistor for the PCIe clock request signal used by the LAN controller.
2	2	+V1P8S	✅	Connected to +V1P8S supply rail, providing pull-up voltage for the LAN_CLKREQ2_B signal.

R354 ❌

DRCY flagged 1 potential issues in this component.

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SD3_WP	❌	This 0-ohm resistor ties SD3_WP (write protect) to SD3_CD# (card detect), which is unusual and likely incorrect. These signals should typically be independent to allow separate detection of card presence and write protection status. Pin 1 is connected to net SD3_WP (from schematic) Pin 2 is connected to net SD3_CD# (from schematic) SD3_WP connects to CPU1 pin BD5 labeled SD3_WP_BD5 (from schematic) SD3_CD# connects to CPU1 pin BC24 labeled SD3_CD# (from schematic) R354 is a 0-ohm resistor that directly connects these two signals together (from schematic) SD3_WP is typically an input to detect if an SD card's write protect switch is enabled, with active-low polarity where low indicates write-protected (reasoning) SD3_CD# is typically an active-low input to detect if an SD card is physically present in the slot, where low indicates card present (reasoning) Tying these signals together forces them to always have the same logic level, preventing independent detection of card presence and write protection status (reasoning) With both signals tied together, when a card is present CD# goes low, which also forces WP low, indicating the card is write-protected regardless of the actual WP switch state (reasoning) In typical SD card interface designs, card detect and write protect are separate signals with independent functionality (reasoning) If write protect detection is not needed, the WP pin should typically be pulled to a fixed state such as high for write-enabled, rather than tied to card detect (reasoning) This connection could cause all inserted cards to appear write-protected, preventing write operations even when the card's WP switch is off (reasoning) Recommendation: Separate these signals and either connect WP to its own detection circuit or pull it to an appropriate fixed state if write protect detection is not required (reasoning)
2	2	SD3_CD#	❌	This 0-ohm resistor ties SD3_WP (write protect) to SD3_CD# (card detect), which is unusual and likely incorrect. These signals should typically be independent to allow separate detection of card presence and write protection status. Pin 1 is connected to net SD3_WP (from schematic) Pin 2 is connected to net SD3_CD# (from schematic) SD3_WP connects to CPU1 pin BD5 labeled SD3_WP_BD5 (from schematic) SD3_CD# connects to CPU1 pin BC24 labeled SD3_CD# (from schematic) R354 is a 0-ohm resistor that directly connects these two signals together (from schematic) SD3_WP is typically an input to detect if an SD card's write protect switch is enabled, with active-low polarity where low indicates write-protected (reasoning) SD3_CD# is typically an active-low input to detect if an SD card is physically present in the slot, where low indicates card present (reasoning) Tying these signals together forces them to always have the same logic level, preventing independent detection of card presence and write protection status (reasoning) With both signals tied together, when a card is present CD# goes low, which also forces WP low, indicating the card is write-protected regardless of the actual WP switch state (reasoning) In typical SD card interface designs, card detect and write protect are separate signals with independent functionality (reasoning) If write protect detection is not needed, the WP pin should typically be pulled to a fixed state such as high for write-enabled, rather than tied to card detect (reasoning) This connection could cause all inserted cards to appear write-protected, preventing write operations even when the card's WP switch is off (reasoning) Recommendation: Separate these signals and either connect WP to its own detection circuit or pull it to an appropriate fixed state if write protect detection is not required (reasoning)

R240 - 110-0003059 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is connected to GND, providing the ground reference for the RCOMP resistor.
2	2	MMC1_RCOMP	✅	Pin 2 is connected to MMC1_RCOMP on the CPU, providing impedance calibration reference for the MMC1 interface.

R242 - 110-0003059 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDA_RCOMP	✅	Connected to HDA_LPE_RCOMP pin (BF20) of CPU1. This provides impedance compensation for the High Definition Audio interface.
2	2	GND	✅	Connected to GND, providing the ground reference for the HDA RCOMP resistor.

R233 - 110-0001923 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP1	✅	DNI 1K pull-down resistor for BOM_OP1 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'.
2	2	GND	✅	DNI 1K pull-down resistor for BOM_OP1 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'.

R211 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	10K pull-up resistor for BOM_OP1 hardware identification bit. Pulls BOM_OP1 to logic HIGH as part of '1001' hardware ID pattern.
2	2	BOM_OP1	✅	10K pull-up resistor for BOM_OP1 hardware identification bit. Pulls BOM_OP1 to logic HIGH as part of '1001' hardware ID pattern.

R208 - 110-0001923 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP2	✅	1K pull-down resistor for BOM_OP2 hardware identification bit. Pulls BOM_OP2 to logic LOW as part of '1001' hardware ID pattern.
2	2	GND	✅	1K pull-down resistor for BOM_OP2 hardware identification bit. Pulls BOM_OP2 to logic LOW as part of '1001' hardware ID pattern.

R209 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	DNI 10K pull-up resistor for BOM_OP2 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'.
2	2	BOM_OP2	✅	DNI 10K pull-up resistor for BOM_OP2 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'.

R234 - 110-0001923 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP3	✅	1K pull-down resistor for BOM_OP3 hardware identification bit. Pulls BOM_OP3 to logic LOW as part of '1001' hardware ID pattern.
2	2	GND	✅	1K pull-down resistor for BOM_OP3 hardware identification bit. Pulls BOM_OP3 to logic LOW as part of '1001' hardware ID pattern.

R210 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	DNI 10K pull-up resistor for BOM_OP3 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'.
2	2	BOM_OP3	✅	DNI 10K pull-up resistor for BOM_OP3 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'.

R401 - 110-0001923 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BOM_OP4	✅	DNI 1K pull-down resistor for BOM_OP4 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'.
2	2	GND	✅	DNI 1K pull-down resistor for BOM_OP4 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'.

R400 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	10K pull-up resistor for BOM_OP4 hardware identification bit. Pulls BOM_OP4 to logic HIGH as part of '1001' hardware ID pattern.
2	2	BOM_OP4	✅	10K pull-up resistor for BOM_OP4 hardware identification bit. Pulls BOM_OP4 to logic HIGH as part of '1001' hardware ID pattern.

R259 - 110-0001923 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S5_10_UNLOCK	✅	Pin 1 connects to GPIO_S5_10_UNLOCK net. This pin is part of a series resistor used for hardware strap isolation.
2	2	LPE_I2S_DATOUT	✅	Pin 2 connects to LPE_I2S_DATOUT net, which connects to CPU1 pin BC30 (LPE_I2S2_DATAOUT). This is a hardware strap pin for Security Flash Descriptors configuration.

R268 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPE_I2S_FRM	✅	Pin 1 connects to LPE_I2S_FRM net, which connects to CPU1 pin BA30 (LPE_I2S2_FRM). This is a hardware strap pin for BIOS Boot Selection.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S (1.8V supply). This pull-up resistor sets the BIOS Boot Selection strap to SPI mode.

R260 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPE_I2S_DATOUT	✅	Pin 1 connects to LPE_I2S_DATOUT net. This is part of an optional pull-down resistor marked DNI.
2	2	GND	✅	Pin 2 connects to GND. This is part of an optional pull-down resistor marked DNI.

R255 - 110-0004474 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR_HOT_L	✅	Pin 1 connects to VR_HOT_L net, which is the PROCHOT (processor hot) signal from CPU1 pin C24. This is an active-low thermal management signal.
2	2	+V1P0S	✅	Pin 2 connects to +V1P0S (1.0V supply), providing a pull-up for the PROCHOT signal. The 73.2 ohm value is unusually low for a typical pull-up but appears intentional.

CPU1 - INTEL_ATOM_E3825_SOC ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A9	ILB_RTC_X2	BRTCX2	✅	ILB_RTC_X2 is correctly connected to the 32.768 kHz RTC crystal output with appropriate load capacitance and feedback resistor.
A13	GPIO_S5_9	SOC_USB_HOST_EN1	✅	GPIO_S5_9 is correctly connected to SOC_USB_HOST_EN1 for USB host port enable control.
A17	GPIO_S5_3	mPCIE_WAKEB	✅	GPIO_S5_3 is correctly connected to mPCIE_WAKEB with optional pull-up resistor for PCIe wake signaling.
A21	PCU_SPI_MOSI	SOC_SPI_MOSI	✅	PCU_SPI_MOSI is correctly connected through a 0-ohm series resistor to the SPI flash interface.
A25	SVID_DATA	SVID_DATA	✅	SVID_DATA is correctly connected through a 16.9 ohm series resistor for impedance matching in the IMVP7 voltage regulator interface.
B7	PMC_CORE_PWROK	PMC_CORE_PWROK	✅	PMC_CORE_PWROK is correctly connected through a 0-ohm resistor to SYS_PWRGD with optional decoupling capacitor.
B8	ILB_RTC_EXTPAD	BVCCRTC_EXTPAD	✅	ILB_RTC_EXTPAD is correctly connected with decoupling capacitor for RTC power supply.
B10	~PMC_RSMRST	PMC_RSMRST	✅	PMC_RSMRST# is correctly connected with an RC network for signal conditioning. The 10us timing requirement is met by the external power management controller, not by this local RC network.
B14	GPIO_S5_6	BOM_OP2	✅	GPIO_S5_6 is correctly connected to BOM_OP2 for board configuration options.
B16	GPIO_S5_1	SOC_GPIO_S5_1	✅	GPIO_S5_1 is correctly connected to SOC_GPIO_S5_1 for general purpose I/O.
B18	GPIO_S5_0	SOC_GPIO_S5_0	✅	GPIO_S5_0 is correctly connected to SOC_GPIO_S5_0 for general purpose I/O.
B22	PCU_SPI_MISO	SOC_SPI_MISO	✅	PCU_SPI_MISO is correctly connected through a 0-ohm series resistor to the SPI flash interface.
B24	~SVID_ALERT	SVID_ALERT	✅	SVID_ALERT is correctly connected through series resistor and pull-up for the IMVP7 voltage regulator alert signal.
C9	ILB_RTC_X1	BRTCX1	✅	ILB_RTC_X1 is correctly connected to the 32.768 kHz RTC crystal input with appropriate load capacitance and feedback resistor.
C11	~ILB_RTC_TEST	ILB_RTC_TESTB	✅	ILB_RTC_TEST is correctly connected to ILB_RTC_TESTB for RTC test mode control.
C12	~ILB_RTC_RST	RTCRST_L	✅	ILB_RTC_RST is correctly connected with pull-up resistor and decoupling capacitor for RTC reset functionality.
C13	GPIO_S5_8	SOC_USB_HOST_EN0	✅	GPIO_S5_8 is correctly connected to SOC_USB_HOST_EN0 for USB host port enable control.
C15	GPIO_S5_7	BOM_OP3	✅	GPIO_S5_7 is correctly connected to BOM_OP3 for board configuration options.
C16	GPIO_S5_5	BOM_OP1	✅	GPIO_S5_5 is correctly connected to BOM_OP1 for board configuration options.
C17	GPIO_S5_4	BOM_OP4	✅	GPIO_S5_4 is correctly connected to BOM_OP4 for board configuration options.
C18	GPIO_S5_2	SOC_GPIO_S5_2	✅	GPIO_S5_2 is correctly connected to SOC_GPIO_S5_2 for general purpose I/O.
C19	GPIO_S5_10	GPIO_S5_10_UNLOCK	✅	GPIO_S5_10 is correctly connected to GPIO_S5_10_UNLOCK for general purpose I/O.
C21	~PCU_SPI_CS_11	SOC_SPI_CS1B	✅	PCU_SPI_CS_11 is correctly connected through a DNI 0-ohm resistor, indicating SPI CS1 is not used in this design.
C22	PCU_SPI_CLK	SOC_SPI_CLK	✅	PCU_SPI_CLK is correctly connected through a 0-ohm series resistor to the SPI flash interface with optional filtering capacitor.
C23	~PCU_SPI_CS_00	SOC_SPI_CS0B	✅	PCU_SPI_CS_00 is correctly connected through a 0-ohm series resistor to the SPI flash interface.
C25	SVID_CLK	SVID_CLK-R	✅	SVID_CLK is correctly connected to provide 25 MHz clock for the IMVP7 voltage regulator interface.
D14	TAP_TCK	XDP_H_TCK	✅	TAP_TCK is correctly connected to the JTAG test clock with 51 ohm pull-down termination.
D18	~TAP_PRDY	XDP_H_PRDYB	✅	TAP_PRDY is correctly connected to the JTAG probe ready signal.
D20	PMC_ACPRESENT	PMC_ACPRESENT	✅	PMC_ACPRESENT is correctly connected with 2.2K pull-up resistor for AC power detection.
D22	~PMC_SLP_S3	PMC_SLP_S3_L	✅	PMC_SLP_S3 is correctly connected through level shifter U19 to translate from 1.8V to 3.3V domain.
D26	PMC_SUSPWRDNACK	SUSPWRDNACK	✅	PMC_SUSPWRDNACK is correctly connected with 10K pull-up resistor and test point.
F12	TAP_TDI	XDP_H_TDI	✅	TAP_TDI is correctly connected to the JTAG test data in with 51 ohm pull-up termination.
F14	TAP_TMS	XDP_H_TMS	✅	TAP_TMS is correctly connected to the JTAG test mode select with 51 ohm pull-up termination.
F16	~TAP_PREQ	XDP_H_PREQB	✅	TAP_PREQ is correctly connected to the JTAG probe request signal.
F18	~PMC_SLP_S0IX	PMC_SLP_S0IX	✅	PMC_SLP_S0IX is correctly connected with test point for monitoring S0ix sleep state.
F20	~PMC_PLTRST	PMC_PLTRST_R_V1P8	✅	PMC_PLTRST is correctly connected through level shifter U19 to translate from 1.8V to 3.3V domain.
F22	~PMC_SLP_S4	PMC_SLP_S4_L	✅	PMC_SLP_S4 is correctly connected through level shifter U19 to translate from 1.8V to 3.3V domain.
F26	~PMC_WAKE_PCIE_0	PMC_PCIE_WAKE_R	✅	PMC_WAKE_PCIE_0 is correctly connected through diode OR circuit with 1K pull-up for PCIe wake signaling.
G12	~TAP_TRST	XDP_H_TRSTB	✅	TAP_TRST is correctly connected to the JTAG test reset with 51 ohm pull-down termination.
G16	TAP_TDO	XDP_H_TDO	✅	TAP_TDO is correctly connected to the JTAG test data out.
G18	~PMC_SUS_STAT	LPCPD_L	✅	PMC_SUS_STAT is correctly connected with test point for monitoring suspend status.
G24	PMC_SUSCLK0_G24	PMC_SUSCLK0	✅	PMC_SUSCLK0_G24 is correctly connected through level shifter U19 with optional pull-up to translate suspend clock from 1.8V to 3.3V domain.
J18	GPIO_S5_25	XDP_H_OBSDATA_A2	✅	GPIO_S5_25 is correctly connected to XDP_H_OBSDATA_A2 for debug observation data.
J20	GPIO_S5_14	GPIO_S514_J20	✅	GPIO_S5_14 is correctly connected to GPIO_S514_J20 with 10K pull-up resistor.
J24	GPIO_S5_17	GPIO_S5_17	✅	GPIO_S5_17 is correctly connected with jumper to GND and 10K pull-up for configuration option.
J26	~PMC_PWRBTN	PMC_PWRBTN	✅	PMC_PWRBTN is correctly connected through dual diode OR circuit for power button functionality.
K18	GPIO_S5_27	EXP_GPIO1	✅	GPIO_S5_27 is correctly connected to EXP_GPIO1 for expansion bus GPIO.
K20	GPIO_S5_28	EXP_GPIO2	✅	GPIO_S5_28 is correctly connected to EXP_GPIO2 for expansion bus GPIO.
K24	GPIO_S5_22	GPIO_D2_LED_CTRL	✅	GPIO_S5_22 is correctly connected to GPIO_D2_LED_CTRL for LED control.
K26	~PMC_BATLOW	PMC_BATLOW	✅	PMC_BATLOW is correctly connected with 20K pull-up resistor for battery low detection.
M18	GPIO_S5_26	XDP_H_OBSDATA_A3	✅	GPIO_S5_26 is correctly connected to XDP_H_OBSDATA_A3 for debug observation data.
M20	GPIO_S5_24	XDP_H_OBSDATA_A1	✅	GPIO_S5_24 is correctly connected to XDP_H_OBSDATA_A1 for debug observation data.
M22	GPIO_S5_29	EXP_GPIO3	✅	GPIO_S5_29 is correctly connected to EXP_GPIO3 for expansion bus GPIO.
M24	GPIO_S5_30	EXP_GPIO4	✅	GPIO_S5_30 is correctly connected to EXP_GPIO4 for expansion bus GPIO.
N24	GPIO_S5_23	XDP_H_OBSDATA_A0	✅	GPIO_S5_23 is correctly connected to XDP_H_OBSDATA_A0 for debug observation data.
N26	GPIO_RCOMP	GPIO_RCOMP	✅	GPIO_RCOMP is correctly connected to a 49.9 ohm compensation resistor to ground.
BA28	SIO_SPI_MISO	SOC_SIO_SPI_MISO	✅	SIO_SPI_MISO is correctly connected to SOC_SIO_SPI_MISO for SPI master in slave out.
BA34	~SIO_UART1_RTS	SIO_UART1_RTSB	✅	SIO_UART1_RTS is correctly connected to SIO_UART1_RTSB for UART1 request to send flow control.
AD9	RESERVED_AD9		✅	Reserved pins are correctly left unconnected as specified by the datasheet.
AD10	RESERVED_AD10		✅	Reserved pins are correctly left unconnected as specified by the datasheet.
AD12	RESERVED_AD12		✅	Reserved pins are correctly left unconnected as specified by the datasheet.
AD13	ICLK_RCOMP	ICLK_RCOMP	✅	ICLK_RCOMP is correctly connected to a 47.5 ohm compensation resistor to ground for integrated clock operation.
AD14	ICLK_ICOMP	ICLK_ICOMP	✅	ICLK_ICOMP is correctly connected to a 4.02K ohm compensation resistor to ground for integrated clock operation.
BD32	~SIO_UART2_RTS		✅	SIO_UART2_RTS is correctly left unconnected as UART2 flow control is not used in this design.
BD34	SIO_UART2_TXD	SIO_UART2_TXD	✅	SIO_UART2_TXD is correctly connected for UART2 transmit data.
AF4	PCIE_CLKP_00		✅	PCIE_CLKP_00 and PCIE_CLKN_00 are correctly left unconnected as these PCIe clock outputs are not used in this design.
AF6	PCIE_CLKN_00		✅	PCIE_CLKP_00 and PCIE_CLKN_00 are correctly left unconnected as these PCIe clock outputs are not used in this design.
AF7	PCIE_CLKP_11		✅	PCIE_CLKP_11 and PCIE_CLKN_11 are correctly left unconnected as these PCIe clock outputs are not used in this design.
AF9	PCIE_CLKN_11		✅	PCIE_CLKP_11 and PCIE_CLKN_11 are correctly left unconnected as these PCIe clock outputs are not used in this design.
BF32	~SIO_UART2_CTS		✅	SIO_UART2_CTS is correctly left unconnected as UART2 flow control is not used in this design.
BF34	SIO_UART2_RXD	SIO_UART2_RXD	✅	SIO_UART2_RXD is correctly connected for UART2 receive data.
BG9	~PMC_RSTBTN	PMC_RSTBTN	✅	PMC_RSTBTN is correctly connected to the reset button input.
AH10	ICLK_OSCOUT	XTAL25_OUT	✅	ICLK_OSCOUT is correctly connected to the 25 MHz crystal output with appropriate load capacitance and feedback resistor.
AH12	ICLK_OSCIN	XTAL25_IN	✅	ICLK_OSCIN is correctly connected to the 25 MHz crystal input with appropriate load capacitance and feedback resistor.
BH4	PMC_PLT_CLK_22		✅	PMC_PLT_CLK_22 is correctly left unconnected as this platform clock output is not used in this design.
BH5	PMC_PLT_CLK_11		✅	PMC_PLT_CLK_11 is correctly left unconnected as this platform clock output is not used in this design.
BH6	PMC_PLT_CLK_44		✅	PMC_PLT_CLK_44 is correctly left unconnected as this platform clock output is not used in this design.
BH7	PMC_PLT_CLK_00		✅	PMC_PLT_CLK_00 is correctly left unconnected as this platform clock output is not used in this design.
BH8	PMC_PLT_CLK_33	I2S_MCLK	✅	PMC_PLT_CLK_33 is correctly connected to I2S_MCLK for audio master clock.
AK4	PCIE_CLKN_22	PCIE_CLK-N2	✅	PCIE_CLKN_22 and PCIE_CLKP_22 are correctly connected to provide 100 MHz differential clock for PCIe interface.
AK6	PCIE_CLKP_22	PCIE_CLK-P2	✅	PCIE_CLKN_22 and PCIE_CLKP_22 are correctly connected to provide 100 MHz differential clock for PCIe interface.
BJ9	PMC_PLT_CLK_55		✅	PMC_PLT_CLK_55 is correctly left unconnected as this platform clock output is not used in this design.
AM4	PCIE_CLKN_33	mPCIE_REFCLK_N	✅	PCIE_CLKN_33 and PCIE_CLKP_33 are correctly connected to provide 100 MHz differential clock for the mPCIE slot.
AM6	PCIE_CLKP_33	mPCIE_REFCLK_P	✅	PCIE_CLKN_33 and PCIE_CLKP_33 are correctly connected to provide 100 MHz differential clock for the mPCIE slot.
AM9	RESERVED_AM9		✅	Reserved pins are correctly left unconnected as specified by the datasheet.
AM10	RESERVED_AM10		✅	Reserved pins are correctly left unconnected as specified by the datasheet.
AT32	SIO_PWM_11	SOC_PWM1	✅	SIO_PWM_11 is correctly connected to SOC_PWM1 for PWM output functionality.
AT34	RESERVED		✅	Reserved pin is correctly left unconnected as specified by the datasheet.
AU32	SIO_PWM_00	SOC_PWM0	✅	SIO_PWM_00 is correctly connected to SOC_PWM0 for PWM output functionality.
AU34	SIO_UART1_RXD	SIO_UART1_RXD	✅	SIO_UART1_RXD is correctly connected for UART1 receive data.
AV32	~SIO_SPI_CS	SOC_SIO_SPI_CS1	✅	SIO_SPI_CS is correctly connected to SOC_SIO_SPI_CS1 for SPI chip select.
AV34	SIO_UART1_TXD	SIO_UART1_TXD	✅	SIO_UART1_TXD is correctly connected for UART1 transmit data.
AY28	SIO_SPI_MOSI	SOC_SIO_SPI_MOSI	✅	SIO_SPI_MOSI is correctly connected to SOC_SIO_SPI_MOSI for SPI master out slave in.
AY30	SIO_SPI_CLK	SOC_SIO_SPI_CLK	✅	SIO_SPI_CLK is correctly connected to SOC_SIO_SPI_CLK for SPI clock.
AY34	~SIO_UART1_CTS	SIO_UART1_CTSB	✅	SIO_UART1_CTS is correctly connected to SIO_UART1_CTSB for UART1 clear to send flow control.

U19 - NTS0104GU12 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA is correctly connected to +V1P8A, providing the 1.8V supply for the A-side of the level shifter.
2	A1	PMC_PLTRST_R_V1P8	✅	A1 is correctly connected to PMC_PLTRST_R_V1P8 from CPU1 pin F20, translating the platform reset signal to 3.3V on B1.
3	A2	PMC_SUSCLK0	✅	A2 is correctly connected to PMC_SUSCLK0 from CPU1 pin G24, translating the suspend clock signal to 3.3V on B2.
4	A3	PMC_SLP_S4_L	✅	A3 is correctly connected to PMC_SLP_S4_L from CPU1 pin F22, translating the S4 sleep state signal to 3.3V on B3.
5	A4	PMC_SLP_S3_L	✅	A4 is correctly connected to PMC_SLP_S3_L from CPU1 pin D22, translating the S3 sleep state signal to 3.3V on B4.
6	GND	GND	✅	GND is correctly connected to the ground net.
7	B4	SLP_S3_L	✅	B4 is correctly connected to SLP_S3_L, providing the 3.3V translated version of the S3 sleep state signal from A4.
8	B3	SLP_S4_L	✅	B3 is correctly connected to SLP_S4_L, providing the 3.3V translated version of the S4 sleep state signal from A3.
9	B2	SUSCLK_3P3	✅	B2 is correctly connected to SUSCLK_3P3, providing the 3.3V translated version of the suspend clock signal from A2.
10	B1	PMC_PLTRST_L	✅	B1 is correctly connected to PMC_PLTRST_L, providing the 3.3V translated version of the platform reset signal from A1.
11	VCCB	PWR_BUF1	✅	VCCB is correctly connected to PWR_BUF1 which provides 3.3V standby power through R26 from +3VSB.
12	OE	PMC_OE	✅	OE is correctly connected to PMC_OE with a 2.2K pull-up resistor to +V1P8A, enabling the level shifter by default.

D5 - BAT754C ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	+PS_3VSB	✅	Anode 1 connected to +PS_3VSB (3.3V standby rail), forming one input of the battery backup OR-ing circuit.
A2	A2	+VBAT_R	✅	Anode 2 connected to +VBAT_R (battery voltage through 1K resistor), forming the second input of the battery backup OR-ing circuit.
C	C	+RTCVCC	✅	Common cathode output connected to +RTCVCC, which powers the RTC section of the CPU from whichever source (standby or battery) has higher voltage.

BH1 - 353-0003073 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	P1	+VBAT	✅	Positive battery terminal connected to +VBAT net, which feeds through 1K resistor R278 to the battery backup OR-ing circuit.
2	P2	+VBAT	✅	Second positive battery terminal connected in parallel with pin 1 to +VBAT net for mechanical stability and redundant electrical connection.
3	N	GND	✅	Negative battery terminal connected to ground.

Y1 - 145-0004789 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BRTCX2	✅	Crystal pin connected to CPU1 RTC oscillator pin ILB_RTC_X2 (BRTCX2) with 18pF load capacitor C42 to ground and 10M feedback resistor R76 to pin 2.
2	2	BRTCX1	✅	Crystal pin connected to CPU1 RTC oscillator pin ILB_RTC_X1 (BRTCX1) with 18pF load capacitor C43 to ground and 10M feedback resistor R76 to pin 1.

Y2 - 145-0004792 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XTAL25_IN	✅	Crystal input terminal connected to CPU1 ICLK_OSCIN (pin AH12) with 27pF load capacitor C175 and 1M feedback resistor R188 to pin 3. This is a standard crystal oscillator input configuration.
2	2	GND	✅	Ground pin correctly connected to GND net. Standard configuration for 4-pin crystal packages.
3	3	XTAL25_OUT	✅	Crystal output terminal connected to CPU1 ICLK_OSCOUT (pin AH10) with 27pF load capacitor C176 and 1M feedback resistor R188 to pin 1. This is a standard crystal oscillator output configuration.
4	4	GND	✅	Ground pin correctly connected to GND net. Standard configuration for 4-pin crystal packages.

D3 - BAT54A-S ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_PCIE_WAKE	✅	Both pins are connected to PMC_PCIE_WAKE net, which is pulled up to +3VSB (3.3V) through R27 (2.2K). This configuration suggests both pins are anodes tied together, likely for a dual diode configuration.
2	2	PMC_PCIE_WAKE	✅	Both pins are connected to PMC_PCIE_WAKE net, which is pulled up to +3VSB (3.3V) through R27 (2.2K). This configuration suggests both pins are anodes tied together, likely for a dual diode configuration.
3	3	PMC_PCIE_WAKE_R	✅	Pin 3 is connected to PMC_PCIE_WAKE_R, which goes to CPU1 pin F26 and is pulled up to +V1P8A (1.8V) through R253 (1K). This appears to be the cathode of the diode, forming a level shifter from 3.3V to 1.8V logic.

D10 - BAT754C ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	3VSB_OK	✅	Pin A1 (Anode 1) is connected to 3VSB_OK, which is pulled up to +3VSB (3.3V) through R162 (1K). This is one input to the diode OR gate.
A2	A2	PMC_PWRBTN	✅	Pin A2 (Anode 2) is connected to PMC_PWRBTN, which goes to CPU1 pin J26 (active-low power button signal). This is the second input to the diode OR gate.
C	C	PS_OUT_L	✅	Pin C (Common Cathode) is connected to PS_OUT_L, which is the output of the diode OR gate. This output will be low if either 3VSB_OK or PMC_PWRBTN is low.

J7 - HDR_2POS_DUAL_TIN ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GPIO_S5_17	✅	Connected to GPIO_S5_17 from the SoC, allowing the jumper to control the GPIO state.
2	2	GND	✅	Connected to GND, providing the ground reference for pulling the GPIO low when the jumper is installed.

R183 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	Connected to +V1P8S to provide pull-up voltage for the GPIO.
2	2	GPIO_S5_17	✅	Connected to GPIO_S5_17, pulling the GPIO high through the 10K resistor when jumper J7 is not installed.

CPU1 - INTEL_ATOM_E3825_SOC ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A7	USB_HSIC_RCOMP	USB_HSIC0_RCOMP	✅	USB_HSIC_RCOMP is correctly connected to a 45.3 ohm resistor to ground for USB HSIC impedance compensation.
B4	USB_HSIC0_DATA		✅	USB_HSIC0_DATA is unconnected, indicating USB HSIC port 0 is not used in this design.
B5	USB_HSIC0_STROBE		✅	USB_HSIC0_STROBE is unconnected, indicating USB HSIC port 0 is not used in this design.
B12	GPIO_S5_43		✅	GPIO_S5_43 is unconnected. This pin can be muxed to USB_ULPI_REFCLK but is not used in this design.
B20	~USB_OC_11	SOC_USB_HOST_OC1	✅	USB_OC_11 (USB overcurrent detect 1) is correctly connected with a 10K pull-up resistor to +V1P8A for active-low operation.
C7	USB_RCOMPI	USB_RCOMP	✅	USB_RCOMPI and USB_RCOMPO are correctly connected together with a 45.3 ohm resistor to ground for USB 2.0 impedance compensation.
D6	USB_RCOMPO	USB_RCOMP	✅	USB_RCOMPI and USB_RCOMPO are correctly connected together with a 45.3 ohm resistor to ground for USB 2.0 impedance compensation.
C20	~USB_OC_00	SOC_USB_HOST_OC0	✅	USB_OC_00 (USB overcurrent detect 0) is correctly connected with a 10K pull-up resistor to +V1P8A for active-low operation.
D2	USB_HSIC1_STROBE		✅	USB_HSIC1_STROBE is unconnected, indicating USB HSIC port 1 is not used in this design.
D4	USB3_RXP0	USB3_RXP0	✅	USB3_RXP0 is connected for USB 3.0 receive positive differential signal.
D10	ICLK_USB_TERM_1	ICLK_USB_TERM_0	✅	ICLK_USB_TERM pins have swapped net names. Pin D10 (ICLK_USB_TERM[1]) connects to net ICLK_USB_TERM_0, and pin F10 (ICLK_USB_TERM[0]) connects to net ICLK_USB_TERM_1. Both are correctly terminated with 1K resistors to ground, so this is functionally correct but the net naming is confusing.
F10	ICLK_USB_TERMN	ICLK_USB_TERM_1	✅	ICLK_USB_TERM pins have swapped net names. Pin D10 (ICLK_USB_TERM[1]) connects to net ICLK_USB_TERM_0, and pin F10 (ICLK_USB_TERM[0]) connects to net ICLK_USB_TERM_1. Both are correctly terminated with 1K resistors to ground, so this is functionally correct but the net naming is confusing.
E2	USB_HSIC1_DATA		✅	USB_HSIC1_DATA is unconnected, indicating USB HSIC port 1 is not used in this design.
E3	USB3_RXN0	USB3_RXN0	✅	USB3_RXN0 is connected for USB 3.0 receive negative differential signal.
G2	GPIO_S5_31		✅	GPIO_S5_31 is unconnected. This pin can be muxed to USB_ULPI_CLK but is not used in this design.
G14	USB_DN1	USB_DN1	✅	USB_DN1 is connected for USB 2.0 port 1 data negative signal.
H3	GPIO_S5_42		✅	GPIO_S5_42 is unconnected. This pin can be muxed to USB_ULPI_STP but is not used in this design.
H4	RESERVED_H4		✅	RESERVED pins are unconnected as expected for reserved pins.
H5	RESERVED_H5		✅	RESERVED pins are unconnected as expected for reserved pins.
H7	RESERVED_H7		✅	RESERVED pins are unconnected as expected for reserved pins.
H8	RESERVED_H8		✅	RESERVED pins are unconnected as expected for reserved pins.
H10	USB_DN3		✅	USB_DN3 is unconnected, indicating USB port 3 is not used in this design.
J3	GPIO_S5_40		✅	GPIO_S5_40 is unconnected, indicating this GPIO is not used in this design.
J12	USB_DN2	USB_HOST_DN	✅	USB_DN2 is connected for USB 2.0 port 2 data negative signal to USB host interface.
J14	USB_DP1	USB_DP1	✅	USB_DP1 is connected for USB 2.0 port 1 data positive signal.
K2	GPIO_S5_34		✅	GPIO_S5_34 is unconnected, indicating this GPIO is not used in this design.
K3	GPIO_S5_35		✅	GPIO_S5_35 is unconnected, indicating this GPIO is not used in this design.
K6	USB3_TXP0	USB3_TXP0	✅	USB3_TXP0 is connected for USB 3.0 transmit positive differential signal.
K7	USB3_TXN0	USB3_TXN0	✅	USB3_TXN0 is connected for USB 3.0 transmit negative differential signal.
K10	USB_DP3		✅	USB_DP3 is unconnected, indicating USB port 3 is not used in this design.
K12	USB_DP2	USB_HOST_DP	✅	USB_DP2 is connected for USB 2.0 port 2 data positive signal to USB host interface.
K16	USB_DN0	USB_DN0	✅	USB_DN0 is connected for USB 2.0 port 0 data negative signal.
L1	GPIO_S5_33		✅	GPIO_S5_33 is unconnected, indicating this GPIO is not used in this design.
L3	GPIO_S5_39		✅	GPIO_S5_39 is unconnected, indicating this GPIO is not used in this design.
M2	GPIO_S5_36		✅	GPIO_S5_36 is unconnected, indicating this GPIO is not used in this design.
M3	GPIO_S5_32		✅	GPIO_S5_32 is unconnected, indicating this GPIO is not used in this design.
M4	RESERVED_M4		✅	RESERVED pins are unconnected as expected for reserved pins.
M6	RESERVED_M6		✅	RESERVED pins are unconnected as expected for reserved pins.
M7	RESERVED_M7		✅	RESERVED pins are unconnected as expected for reserved pins.
M9	RESERVED_M9		✅	RESERVED pins are unconnected as expected for reserved pins.
M10	RESERVED_M10		✅	RESERVED pins are unconnected as expected for reserved pins.
M12	USB3_REXT0	USB3_REXT0	✅	USB3_REXT0 is correctly connected to a 1.24K ohm resistor to ground for USB 3.0 external reference.
M13	USB_PLL_MON	USB_PLL_MON	✅	USB_PLL_MON is connected to a DNI test point for monitoring USB PLL operation.
M16	USB_DP0	USB_DP0	✅	USB_DP0 is connected for USB 2.0 port 0 data positive signal.
N3	GPIO_S5_37		✅	GPIO_S5_37 is unconnected, indicating this GPIO is not used in this design.
P2	GPIO_S5_38		✅	GPIO_S5_38 is unconnected, indicating this GPIO is not used in this design.
P3	GPIO_S5_41		✅	GPIO_S5_41 is unconnected, indicating this GPIO is not used in this design.
P6	RESERVED_P6		✅	RESERVED pins are unconnected as expected for reserved pins.
P7	RESERVED_P7		✅	RESERVED pins are unconnected as expected for reserved pins.
P10	RESERVED_P10		✅	RESERVED pins are unconnected as expected for reserved pins.
P12	RESERVED_P12		✅	RESERVED pins are unconnected as expected for reserved pins.
BC12	GPIO_S0_SC_56	GPIO_S0_SC_56	✅	GPIO_S0_SC_56 is connected to an unspecified net, likely used for a board-specific function.
BC14	GPIO_S0_SC_58	HDMI_CEC	✅	GPIO_S0_SC_58 is connected to HDMI_CEC signal for HDMI Consumer Electronics Control.
BC16	GPIO_S0_SC_61	PCU_UART3_RXD	✅	GPIO_S0_SC_61 is correctly configured as UART3 RX with level shifting from 1.8V to 3.3V through U6.
BD12	GPIO_S0_SC_55	GPIO_S0_SC_55	✅	GPIO_S0_SC_55 is connected to a DNI test point for debug access.
BD14	GPIO_S0_SC_57	PCU_UART3_TXD	✅	GPIO_S0_SC_57 is correctly configured as UART3 TX with level shifting from 1.8V to 3.3V through U6.
BD16	GPIO_S0_SC_60		✅	GPIO_S0_SC_60 is unconnected, indicating this GPIO is not used in this design.
BF14	GPIO_S0_SC_59		✅	GPIO_S0_SC_59 is unconnected, indicating this GPIO is not used in this design.
BF18	LPC_RCOMP	LPC_RCOMP	✅	LPC_RCOMP is correctly connected to a 49.9 ohm resistor to ground for LPC bus impedance compensation.
BF27	SIO_I2C4_DATA		✅	SIO_I2C4_DATA is unconnected, indicating I2C port 4 is not used in this design.
BG11	~PCU_SMB_ALERT	PCU_SMB_ALERT	✅	PCU_SMB_ALERT is correctly connected with a 10K pull-up to +V1P8S and routed to LAN-SMB-ALERT# through a 0 ohm jumper.
BG12	PCU_SMB_DATA	PCU_SMB_DATA	✅	PCU_SMB_DATA is correctly connected with a 2.2K pull-up to +V1P8S and level-shifted to DDR_SMB_DATA through U5.
BG13	ILB_LPC_SERIRQ		✅	ILB_LPC_SERIRQ is unconnected, indicating the LPC serial IRQ is not used in this design.
BG14	ILB_LPC_AD_33		✅	ILB_LPC_AD_33 is unconnected, indicating the LPC interface is not used in this design.
BG15	ILB_LPC_CLK_00		✅	ILB_LPC_CLK_00 is unconnected, indicating the LPC interface is not used in this design.
BG16	~ILB_LPC_CLKRUN		✅	ILB_LPC_CLKRUN is unconnected, indicating the LPC interface is not used in this design.
BG17	~ILB_LPC_FRAME		✅	ILB_LPC_FRAME is unconnected, indicating the LPC interface is not used in this design.
BG23	SIO_I2C0_CLK		✅	SIO_I2C0_CLK is unconnected, indicating I2C port 0 is not used in this design.
BG24	SIO_I2C1_DATA	SIO_I2C1_SDA	✅	SIO_I2C1_DATA is connected to a DNI test point for debug access to I2C1 data line.
BG25	SIO_I2C2_DATA		✅	SIO_I2C2_DATA is unconnected, indicating I2C port 2 is not used in this design.
BG26	SIO_I2C3_DATA		✅	SIO_I2C3_DATA is unconnected, indicating I2C port 3 is not used in this design.
BG27	SIO_I2C4_CLK		✅	SIO_I2C4_CLK is unconnected, indicating I2C port 4 is not used in this design.
BG28	SIO_I2C5_CLK	SI0_I2C5_SCL	✅	SIO_I2C5_CLK is correctly connected through a 22 ohm series resistor to I2C5_SCL for signal integrity.
BG29	SIO_I2C6_CLK	SI0_I2C6_SCL	✅	SIO_I2C6_CLK is correctly connected through a 22 ohm series resistor to I2C6_SCL for signal integrity.
BG30	GPIO_S0_SC_093	TP10_NET	✅	GPIO_S0_SC_093 is intentionally grounded through a 0 ohm resistor, likely to disable a specific function.
BH10	PCU_SMB_CLK	PCU_SMB_CLK	✅	PCU_SMB_CLK is correctly connected with a 2.2K pull-up to +V1P8S and level-shifted to DDR_SMB_CLK through U5.
BH12	ILB_8254_SPKR	ILB_8254_SPKR	✅	ILB_8254_SPKR is connected to a speaker output signal.
BH14	ILB_LPC_CLK_11		✅	ILB_LPC_CLK_11 is unconnected, indicating the LPC interface is not used in this design.
BH16	ILB_LPC_AD_00		✅	ILB_LPC_AD_00 is unconnected, indicating the LPC interface is not used in this design.
BH22	SIO_I2C0_DATA		✅	SIO_I2C0_DATA is unconnected, indicating I2C port 0 is not used in this design.
BH24	SIO_I2C1_CLK	SIO_I2C1_SCL	✅	SIO_I2C1_CLK is connected to a DNI test point for debug access to I2C1 clock line.
BH26	SIO_I2C3_CLK		✅	SIO_I2C3_CLK is unconnected, indicating I2C port 3 is not used in this design.
BH28	SIO_I2C5_DATA	SI0_I2C5_SDA	✅	SIO_I2C5_DATA is correctly connected through a 22 ohm series resistor to I2C5_SDA for signal integrity.
BH30	GPIO_S0_SC_092	TP9_NET	✅	GPIO_S0_SC_092 is intentionally grounded through a 0 ohm resistor, likely to disable a specific function.
BJ13	ILB_LPC_AD_22		✅	ILB_LPC_AD_22 is unconnected, indicating the LPC interface is not used in this design.
BJ17	ILB_LPC_AD_11		✅	ILB_LPC_AD_11 is unconnected, indicating the LPC interface is not used in this design.
BJ25	SIO_I2C2_CLK		✅	SIO_I2C2_CLK is unconnected, indicating I2C port 2 is not used in this design.
BJ29	SIO_I2C6_DATA	SI0_I2C6_SDA	✅	SIO_I2C6_DATA is correctly connected through a 22 ohm series resistor to I2C6_SDA for signal integrity.

J4 - SIP6_RA ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pin correctly connected to GND, providing the reference voltage for the UART serial communication.
2	2		✅	Pins 2, 3, and 6 are intentionally left unconnected as they are not required for this UART application.
3	3		✅	Pins 2, 3, and 6 are intentionally left unconnected as they are not required for this UART application.
6	6		✅	Pins 2, 3, and 6 are intentionally left unconnected as they are not required for this UART application.
4	4	DBG_UART3_RXD	✅	Pin 4 correctly connected to DBG_UART3_RXD, which receives data from the external cable (cable TX to CPU RX).
5	5	DBG_UART3_TXD_R	✅	Pin 5 correctly connected to DBG_UART3_TXD_R, which transmits data to the external cable (CPU TX to cable RX).

U6 - NTS0102GT ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	DBG_UART3_TXD	✅	B2 pin connects to DBG_UART3_TXD, translating the CPU's UART transmit signal from 1.8V to 3.3V for the debug connector.
2	GND	GND	✅	GND pin is correctly connected to the ground net, providing the reference for the level shifter.
3	VCCA	+V1P8S	✅	VCCA pin is correctly connected to +V1P8S (1.8V) with appropriate bypass capacitor C30 (0.1uF), providing power for the A-side of the level shifter.
4	A2	PCU_UART3_TXD	✅	A2 pin connects to PCU_UART3_TXD from the CPU, receiving the 1.8V UART transmit signal for level translation.
5	A1	PCU_UART3_RXD	✅	A1 pin connects to PCU_UART3_RXD, routing the received UART signal from the B-side to the CPU at 1.8V.
6	OE	LSENB	✅	OE pin is connected to LSENB, which is pulled high to +V1P8S through R52 (2.2K), keeping the level shifter permanently enabled.
7	VCCB	BUF3_PWR	✅	VCCB pin is correctly connected to BUF3_PWR, which supplies 3.3V from +3VSB through R51 (0 ohm), with bypass capacitor C31 (0.1uF).
8	B1	DBG_UART3_RXD	✅	B1 pin connects to DBG_UART3_RXD, receiving the 3.3V UART signal from the debug connector for translation to 1.8V.

U5 - NTS0102GT ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	DDR_SMB_CLK	✅	B2 pin connects to DDR_SMB_CLK, which is the high-voltage side (3.3V) of the SMBus clock channel 2. This signal routes through R841 to LAN-SMB-CLK.
2	GND	GND	✅	GND pin is correctly connected to the ground net, providing the common ground reference for the level translator.
3	VCCA	+V1P8S	✅	VCCA pin is connected to +V1P8S (1.8V supply), providing power for the low-voltage side of the level translator.
4	A2	PCU_SMB_CLK	✅	A2 pin connects to PCU_SMB_CLK, which is the low-voltage side (1.8V) of the SMBus clock channel 2 from the CPU.
5	A1	PCU_SMB_DATA	✅	A1 pin connects to PCU_SMB_DATA, which is the low-voltage side (1.8V) of the SMBus data channel 1 from the CPU.
6	OE	PCU_SMB_BUFF_ENB	✅	OE pin connects to PCU_SMB_BUFF_ENB with a 10K pull-up to +V1P8S, controlling the enable state of the level translator.
7	VCCB	BUF2_PWR	✅	VCCB pin is connected to BUF2_PWR, which is +VCC3 (3.3V) through R48 (0 ohm), providing power for the high-voltage side of the level translator.
8	B1	DDR_SMB_DATA	✅	B1 pin connects to DDR_SMB_DATA, which is the high-voltage side (3.3V) of the SMBus data channel 1. This signal routes through R840 to LAN-SMB-DATA.

R840 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_SMB_DATA	✅	Pin 1 connects to DDR_SMB_DATA from the level translator's high-voltage side.
2	2	LAN-SMB-DATA	✅	Pin 2 connects to LAN-SMB-DATA, routing the translated SMBus data signal to the LAN interface.

R841 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_SMB_CLK	✅	Pin 1 connects to DDR_SMB_CLK from the level translator's high-voltage side.
2	2	LAN-SMB-CLK	✅	Pin 2 connects to LAN-SMB-CLK, routing the translated SMBus clock signal to the LAN interface.

R842 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-SMB-ALERT#	✅	Pin 1 connects to LAN-SMB-ALERT#, the active-low alert signal from the LAN interface.
2	2	PCU_SMB_ALERT	✅	Pin 2 connects to PCU_SMB_ALERT, routing the alert signal directly to the CPU without level translation.

R77 - 45.3 ohm 1% 1/4W 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. This is the ground side of the USB HSIC RCOMP resistor.
2	2	USB_HSIC0_RCOMP	✅	Connected to USB_HSIC0_RCOMP (CPU1 pin A7). This provides the 45.3 ohm compensation resistance for the USB HSIC interface.

R212 - 1.24K ohm 1% 1/4W 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB3_REXT0	✅	Connected to USB3_REXT0 (CPU1 pin M12). This provides the 1.24K external reference resistance for the USB 3.0 interface.
2	2	GND	✅	Connected to GND. This is the ground side of the USB 3.0 REXT resistor.

R185 - 45.3 ohm 1% 1/4W 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. This is the ground side of the USB 2.0 RCOMP resistor.
2	2	USB_RCOMP	✅	Connected to USB_RCOMP (CPU1 pins D6 and C7). This provides the 45.3 ohm compensation resistance for the USB 2.0 interface.

R187 - RES_1Kohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. This is the ground side of the USB clock termination resistor.
2	2	ICLK_USB_TERM_0	✅	Connected to ICLK_USB_TERM_0 (CPU1 pin D10). This provides 1K pull-down termination for the USB clock signal.

R186 - RES_1Kohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. This is the ground side of the USB clock termination resistor.
2	2	ICLK_USB_TERM_1	✅	Connected to ICLK_USB_TERM_1 (CPU1 pin F10, ICLK_USB_TERMN). This provides 1K pull-down termination for the USB clock signal.

R241 - 49.9 ohm 1% 1/10W 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LPC_RCOMP	✅	Connected to CPU1 pin BF18 (LPC_RCOMP) for LPC interface impedance calibration. This connection is correct.
2	2	GND	✅	Connected to GND, providing the ground reference for the RCOMP calibration resistor. This connection is correct.

R48 - RES_0Ohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	BUF2_PWR	✅	Pin 1 connects to BUF2_PWR, which supplies power to the VCCB pin of level shifter U5. This 0-ohm resistor acts as a jumper to provide +VCC3 power to the high-voltage side of the level shifter.
2	2	+VCC3	✅	Pin 2 connects to +VCC3 power rail, sourcing 3.3V power through the 0-ohm resistor to BUF2_PWR. This provides the appropriate voltage level for the DDR_SMB interface side of the level shifter.

R243 - RES_0Ohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TP9_NET	✅	Pin 1 connects to TP9_NET, which is tied to CPU GPIO_S0_SC_092 (pin BH30). This 0-ohm resistor grounds the unused GPIO pin, as indicated by schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'.
2	2	GND	✅	Pin 2 connects to GND, providing the ground reference for the GPIO pin being terminated through this 0-ohm resistor.

R261 - RES_0Ohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	TP10_NET	✅	Pin 1 connects to TP10_NET, which is tied to CPU GPIO_S0_SC_093 (pin BG30). This 0-ohm resistor grounds the unused GPIO pin, as indicated by schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'.
2	2	GND	✅	Pin 2 connects to GND, providing the ground reference for the GPIO pin being terminated through this 0-ohm resistor.

CPU1 - INTEL_ATOM_E3825_SOC ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A48	DRAM_VDD_S4	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
AK38	DRAM_VDD_S4_AK38	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
AM38	DRAM_VDD_S4_AM38	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
AV41	DRAM_VDD_S4_AV41	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
AV42	DRAM_VDD_S4_AV42	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
BB46	DRAM_VDD_S4_BB46	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
BD49	DRAM_VDD_S4_BD49	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
BD52	DRAM_VDD_S4_BD52	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
BD53	DRAM_VDD_S4_BD53	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
BF44	DRAM_VDD_S4_BF44	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
BG51	DRAM_VDD_S4_BG51	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
BJ48	DRAM_VDD_S4_BJ48	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
C51	DRAM_VDD_S4_C51	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
D44	DRAM_VDD_S4_D44	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
F49	DRAM_VDD_S4_F49	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
F52	DRAM_VDD_S4_F52	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
F53	DRAM_VDD_S4_F53	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
H46	DRAM_VDD_S4_H46	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
M41	DRAM_VDD_S4_M41	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
M42	DRAM_VDD_S4_M42	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
V38	DRAM_VDD_S4_V38	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
Y38	DRAM_VDD_S4_Y38	+VDIMM	✅	DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states.
N28	CORE_VSS_SENSE_N28	VSS_SENSE	✅	Core ground sense pin for voltage regulator feedback. Connected to VSS_SENSE net for remote sensing of the ground reference.
P28	CORE_VCC_SENSE_P28	VCC_SENSE	✅	Core voltage sense pin for voltage regulator feedback. Connected to VCC_SENSE net for remote sensing of the VCC supply voltage.
AA22	TP2_CORE_VCC_S0IX	$9N615	✅	Test point pin for monitoring core VCC voltage in S0IX state. Connected to test point TP2 which is marked DNI (Do Not Install).
AA24	UNCORE_VNN_S3_AA24	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AC22	UNCORE_VNN_S3_AC22	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AC24	UNCORE_VNN_S3_AC24	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AD22	UNCORE_VNN_S3_AD22	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AD24	UNCORE_VNN_S3_AD24	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AF22	UNCORE_VNN_S3_AF22	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AF24	UNCORE_VNN_S3_AF24	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AG22	UNCORE_VNN_S3_AG22	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AG24	UNCORE_VNN_S3_AG24	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AJ22	UNCORE_VNN_S3_AJ22	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AJ24	UNCORE_VNN_S3_AJ24	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AK22	UNCORE_VNN_S3_AK22	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AK24	UNCORE_VNN_S3_AK24	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AK25	UNCORE_VNN_S3_AK25	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AK27	UNCORE_VNN_S3_AK27	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AK29	UNCORE_VNN_S3_AK29	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AK30	UNCORE_VNN_S3_AK30	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AK32	UNCORE_VNN_S3_AK32	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AM22	UNCORE_VNN_S3_AM22	+VGFX	✅	Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic.
AA27	CORE_VCC_S0IX_AA27	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AA29	CORE_VCC_S0IX_AA29	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AA30	CORE_VCC_S0IX_AA30	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AC27	CORE_VCC_S0IX_AC27	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AC29	CORE_VCC_S0IX_AC29	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AC30	CORE_VCC_S0IX_AC30	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AD27	CORE_VCC_S0IX_AD27	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AD29	CORE_VCC_S0IX_AD29	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AD30	CORE_VCC_S0IX_AD30	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AF27	CORE_VCC_S0IX_AF27	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AF29	CORE_VCC_S0IX_AF29	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AG27	CORE_VCC_S0IX_AG27	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AG29	CORE_VCC_S0IX_AG29	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
AG30	CORE_VCC_S0IX_AG30	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
P26	CORE_VCC_S0IX_P26	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
P27	CORE_VCC_S0IX_P27	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
U27	CORE_VCC_S0IX_U27	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
U29	CORE_VCC_S0IX_U29	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
V27	CORE_VCC_S0IX_V27	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
V29	CORE_VCC_S0IX_V29	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
V30	CORE_VCC_S0IX_V30	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
Y27	CORE_VCC_S0IX_Y27	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
Y29	CORE_VCC_S0IX_Y29	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
Y30	CORE_VCC_S0IX_Y30	+VCORE	✅	Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores.
BB8	UNCORE_VNN_SENSE	VCCGT_SENSE	✅	Uncore/graphics voltage sense pin for voltage regulator feedback. Connected to VCCGT_SENSE net for remote sensing of the VNN supply voltage.
AD38	DRAM_VDD_S4_AD38	DRAM_VDD_CLK	✅	DRAM clock power supply pins connected to DRAM_VDD_CLK rail. This rail is derived from +VDIMM through 0-ohm resistor R275 to provide filtered power for the DRAM clock circuitry.
AF38	DRAM_VDD_S4_AF38	DRAM_VDD_CLK	✅	DRAM clock power supply pins connected to DRAM_VDD_CLK rail. This rail is derived from +VDIMM through 0-ohm resistor R275 to provide filtered power for the DRAM clock circuitry.
AF30	TP_CORE_V1P05_S4	$9N613	✅	Test point pin for monitoring 1.05V core supply in S4 state. Connected to test point TP1 which is marked DNI (Do Not Install).

R275 - 0 ohm JMPR 1/10W 0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	0-ohm jumper connecting +VDIMM (1.35V DDR3L supply) to DRAM_VDD_CLK net, providing a separate power domain for DRAM clock circuitry with dedicated decoupling.
2	2	DRAM_VDD_CLK	✅	0-ohm jumper connecting +VDIMM (1.35V DDR3L supply) to DRAM_VDD_CLK net, providing a separate power domain for DRAM clock circuitry with dedicated decoupling.

TP1 - TEST_POINT_0.040_SMT ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$9N613	✅	Test point connected to CPU1 pin AF30 (TP_CORE_V1P05_S4) for monitoring the 1.05V core voltage supply in S4 power state. Component is marked DNI (Do Not Install), which is standard practice for debug test points.

TP2 - TEST_POINT_0.040_SMT ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$9N615	✅	Test point connected to CPU1 pin AA22 (TP2_CORE_VCC_S0IX) for monitoring the variable core VCC voltage in S0IX low-power idle state. Component is marked DNI (Do Not Install), which is standard practice for debug test points.

CPU1 - INTEL_ATOM_E3825_SOC ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
AC32	CORE_V1P05_S3_AC32	+V1P0S	❌	CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications. These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic) All pins are connected to the +V1P0S net (from schematic) The +V1P0S net name suggests 1.0V nominal voltage (from schematic) Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic) V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet 140-0004628, page 120) V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet 140-0004628, page 119) CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet 140-0004628, page 120) Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic) Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic) Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning) The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning) Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning) The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet 140-0004628, page 119-120) These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)
Y32	CORE_V1P05_S3_Y32	+V1P0S	❌	CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications. These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic) All pins are connected to the +V1P0S net (from schematic) The +V1P0S net name suggests 1.0V nominal voltage (from schematic) Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic) V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet 140-0004628, page 120) V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet 140-0004628, page 119) CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet 140-0004628, page 120) Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic) Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic) Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning) The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning) Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning) The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet 140-0004628, page 119-120) These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)
AA33	CORE_V1P05_S3_AA33	+V1P0S	❌	CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications. These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic) All pins are connected to the +V1P0S net (from schematic) The +V1P0S net name suggests 1.0V nominal voltage (from schematic) Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic) V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet 140-0004628, page 120) V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet 140-0004628, page 119) CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet 140-0004628, page 120) Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic) Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic) Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning) The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning) Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning) The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet 140-0004628, page 119-120) These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)
AF33	CORE_V1P05_S3_AF33	+V1P0S	❌	CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications. These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic) All pins are connected to the +V1P0S net (from schematic) The +V1P0S net name suggests 1.0V nominal voltage (from schematic) Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic) V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet 140-0004628, page 120) V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet 140-0004628, page 119) CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet 140-0004628, page 120) Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic) Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic) Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning) The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning) Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning) The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet 140-0004628, page 119-120) These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)
AG33	CORE_V1P05_S3_AG33	+V1P0S	❌	CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications. These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic) All pins are connected to the +V1P0S net (from schematic) The +V1P0S net name suggests 1.0V nominal voltage (from schematic) Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic) V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet 140-0004628, page 120) V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet 140-0004628, page 119) CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet 140-0004628, page 120) Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic) Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic) Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning) The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning) Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning) The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet 140-0004628, page 119-120) These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)
AG35	CORE_V1P05_S3_AG35	+V1P0S	❌	CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications. These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic) All pins are connected to the +V1P0S net (from schematic) The +V1P0S net name suggests 1.0V nominal voltage (from schematic) Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic) V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet 140-0004628, page 120) V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet 140-0004628, page 119) CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet 140-0004628, page 120) Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic) Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic) Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning) The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning) Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning) The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet 140-0004628, page 119-120) These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)
U33	CORE_V1P05_S3_U33	+V1P0S	❌	CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications. These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic) All pins are connected to the +V1P0S net (from schematic) The +V1P0S net name suggests 1.0V nominal voltage (from schematic) Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic) V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet 140-0004628, page 120) V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet 140-0004628, page 119) CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet 140-0004628, page 120) Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic) Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic) Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning) The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning) Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning) The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet 140-0004628, page 119-120) These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)
U35	CORE_V1P05_S3_U35	+V1P0S	❌	CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications. These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic) All pins are connected to the +V1P0S net (from schematic) The +V1P0S net name suggests 1.0V nominal voltage (from schematic) Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic) V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet 140-0004628, page 120) V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet 140-0004628, page 119) CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet 140-0004628, page 120) Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic) Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic) Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning) The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning) Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning) The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet 140-0004628, page 119-120) These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)
V33	CORE_V1P05_S3_V33	+V1P0S	❌	CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications. These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic) All pins are connected to the +V1P0S net (from schematic) The +V1P0S net name suggests 1.0V nominal voltage (from schematic) Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic) V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet 140-0004628, page 120) V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet 140-0004628, page 119) CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet 140-0004628, page 120) Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic) Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic) Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning) The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning) Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning) The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet 140-0004628, page 119-120) These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)
A3	VSS_A3_A3	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
A5	VSS_A5_A5	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
A6	VSS_A6_A6	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
A49	VSS_A49_A49	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
A51	VSS_A51_A51	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
A52	VSS_A52_A52	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
B2	VSS_B2_B2	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
B52	VSS_B52_B52	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
B53	VSS_B53_B53	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BE1	VSS_BE1_BE1	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BE53	VSS_BE53_BE53	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BG1	VSS_BG1_BG1	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BG53	VSS_BG53_BG53	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BH1	VSS_BH1_BH1	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BH2	VSS_BH2_BH2	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BH52	VSS_BH52_BH52	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BH53	VSS_BH53_BH53	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BJ2	VSS_BJ2_BJ2	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BJ3	VSS_BJ3_BJ3	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BJ5	VSS_BJ5_BJ5	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BJ49	VSS_BJ49_BJ49	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BJ51	VSS_BJ51_BJ51	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
BJ52	VSS_BJ52_BJ52	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
C1	VSS_C1_C1	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
C53	VSS_C53_C53	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
E1	VSS_E1_E1	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
E53	VSS_E53_E53	GND	✅	Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC.
B6	UNCORE_V1P0_G3_B6	+V1P0A	✅	UNCORE_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling.
C5	UNCORE_V1P0_G3_C5	+V1P0A	✅	UNCORE_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling.
U22	UNCORE_V1P0_G3_U22	+V1P0A	✅	UNCORE_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling.
V22	UNCORE_V1P0_G3_V22	+V1P0A	✅	UNCORE_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling.
C3	USB3_V1P0_G3_C3	+V1P0A	✅	USB3_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling.
Y19	USB3_V1P0_G3_Y19	+V1P0A	✅	USB3_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling.
F1	RESERVED_F1	$10N1595	✅	RESERVED_F1 pin connected to test point TP4. This is acceptable for a reserved pin used for debug access.
M14	USB_V1P0_S3_M14	+V1P0S	✅	USB_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
U18	USB_V1P0_S3_U18	+V1P0S	✅	USB_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
U19	USB_V1P0_S3_U19	+V1P0S	✅	USB_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
N18	USB_V3P3_G3_N18	+3VSB	✅	USB_V3P3_G3 pins correctly connected to +3VSB (3.3V) always-on rail with appropriate decoupling.
P18	USB_V3P3_G3_P18	+3VSB	✅	USB_V3P3_G3 pins correctly connected to +3VSB (3.3V) always-on rail with appropriate decoupling.
N20	USB_V1P8_G3_N20	+V1P8A	✅	USB_V1P8_G3 pin correctly connected to +V1P8A (1.8V) always-on rail with appropriate decoupling.
N22	PCU_V3P3_G3_N22	+3VSB	✅	PCU_V3P3_G3 pin correctly connected to +3VSB (3.3V) always-on rail with appropriate decoupling.
P22	RTC_VCC_P22	+RTCVCC	✅	RTC_VCC pin correctly connected to +RTCVCC rail with appropriate decoupling. This is the always-on RTC power supply.
U16	USB_VSSA_U16	GND	✅	USB_VSSA analog ground pin correctly connected to GND net.
U24	UNCORE_V1P8_G3_U24	+V1P8A	✅	UNCORE_V1P8_G3 and PMU_V1P8_G3 pins correctly connected to +V1P8A (1.8V) always-on rail with appropriate decoupling.
U25	PMU_V1P8_G3_U25	+V1P8A	✅	UNCORE_V1P8_G3 and PMU_V1P8_G3 pins correctly connected to +V1P8A (1.8V) always-on rail with appropriate decoupling.
U36	UNCORE_V1P35_S0IX_F4_U36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX_F4 pin correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead.
V18	USB_HSIC_V1P24_G3_V18	+V1P0A	✅	USB_HSIC_V1P24_G3 pin correctly connected to +V1P0A (1.0V) instead of 1.24V. This is acceptable when USB HSIC is not used per datasheet.
V22	UNCORE_V1P0_G3_V22	+V1P0A	✅	Multiple power pins correctly connected to their respective rails: V22 to +V1P0A, V24 to VCC_VIS_V1P0, V25 to +V1P8A.
V24	UNCORE_V1P0_S0IX_V24	VCC_VIS_V1P0	✅	Multiple power pins correctly connected to their respective rails: V22 to +V1P0A, V24 to VCC_VIS_V1P0, V25 to +V1P8A.
V25	PCU_V1P8_G3_V25	+V1P8A	✅	Multiple power pins correctly connected to their respective rails: V22 to +V1P0A, V24 to VCC_VIS_V1P0, V25 to +V1P8A.
V32	SVID_V1P0_S3_V32	+V1P0S	✅	SVID_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
V36	UNCORE_V1P35_S0IX_F3_V36	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX_F3 pin correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead.
Y18	UNCORE_V1P0_S3_Y18	+V1P0S	✅	UNCORE_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
Y22	UNCORE_V1P0_S0IX_Y22	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222.
Y24	UNCORE_V1P0_S0IX_Y24	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222.
AA18	UNCORE_V1P8_G3_AA18	+V1P8A	✅	UNCORE_V1P8_G3 pin correctly connected to +V1P8A (1.8V) always-on rail with appropriate decoupling.
AA25	UNCORE_V1P35_S0IX_F5_AA25	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX_F5 pin correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead.
AA36	DRAM_V1P0_S0IX_AA36	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper.
AD35	DRAM_V1P0_S0IX_AD35	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper.
AF35	DRAM_V1P0_S0IX_AF35	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper.
AF36	DRAM_V1P0_S0IX_AF36	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper.
AJ36	DRAM_V1P0_S0IX_AJ36	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper.
AK35	DRAM_V1P0_S0IX_AK35	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper.
AK36	DRAM_V1P0_S0IX_AK36	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper.
Y35	DRAM_V1P0_S0IX_Y35	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper.
Y36	DRAM_V1P0_S0IX_Y36	VCC_DRAM	✅	DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper.
AD16	VSS_AD16	VCC_VSS_V1P2	✅	VSS pins connected to VCC_VSS_V1P2 net which is grounded through R216. This is correct for Bay Trail-I when MIPI CSI is not used.
AD18	VSS_AD18	VCC_VSS_V1P2	✅	VSS pins connected to VCC_VSS_V1P2 net which is grounded through R216. This is correct for Bay Trail-I when MIPI CSI is not used.
AD36	DRAM_V1P35_S0IX_F1_AD36	VCC_UNCORE_V1P35	✅	DRAM_V1P35_S0IX_F1 pin correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead.
BD1	VGA_V1P35_S3_F1_BD1	VCC_CRT_V1P35	✅	VGA_V1P35_S3_F1 pin correctly connected to VCC_CRT_V1P35 rail derived from +V1P35S through FB4 ferrite bead.
AF16	UNCORE_V1P0_S3_AF16	+V1P0S	✅	UNCORE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AF18	UNCORE_V1P0_S3_AF18	+V1P0S	✅	UNCORE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
G1	UNCORE_V1P0_S3_G1	+V1P0S	✅	UNCORE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
Y18	UNCORE_V1P0_S3_Y18	+V1P0S	✅	UNCORE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AF19	UNCORE_V1P35_S0IX_F6	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX_F6 pin correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead.
AF21	UNCORE_V1P0_S0IX_AF21	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222.
AG21	UNCORE_V1P0_S0IX_AG21	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222.
AG18	ICLK_V1P35_S3_F2	VCC_ICLK_V1P35	✅	ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail derived from +V1P35S through FB5 ferrite bead.
AJ19	ICLK_V1P35_S3_F1_AJ19	VCC_ICLK_V1P35	✅	ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail derived from +V1P35S through FB5 ferrite bead.
AG19	UNCORE_V1P35_S0IX_F1_AG19	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead.
AG32	UNCORE_V1P35_S0IX_F2_AG32	VCC_UNCORE_V1P35	✅	UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead.
AJ18	DDI_V1P0_S0IX_AJ18	+V1P0S	✅	DDI_V1P0_S0IX pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AK19	DDI_V1P0_S0IX_AK19	+V1P0S	✅	DDI_V1P0_S0IX pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AK21	DDI_V1P0_S0IX_AK21	+V1P0S	✅	DDI_V1P0_S0IX pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AM16	DDI_V1P0_S0IX_AM16	+V1P0S	✅	DDI_V1P0_S0IX pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
BJ6	VGA_V1P0_S3_BJ6	+V1P0S	✅	VGA_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AK18	PCIE_V1P0_S3_AK18	+V1P0S	✅	PCIE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AM18	PCIE_V1P0_S3_AM18	+V1P0S	✅	PCIE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AM21	PCIE_V1P0_S3_AM21	+V1P0S	✅	PCIE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AN21	PCIE_V1P0_S3_AN21	+V1P0S	✅	PCIE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AM27	LPC_V1P8V3P3_S3_AM27	+VCC3S	✅	LPC_V1P8V3P3_S3 pin correctly connected to +VCC3S (3.3V) rail. Design chose 3.3V option for LPC interface.
AM30	UNCORE_V1P8_S3_AM30	+V1P8S	✅	UNCORE_V1P8_S3 pins correctly connected to +V1P8S (1.8V) rail with appropriate decoupling.
AN32	UNCORE_V1P8_S3_AN32	+V1P8S	✅	UNCORE_V1P8_S3 pins correctly connected to +V1P8S (1.8V) rail with appropriate decoupling.
U38	UNCORE_V1P8_S3_U38	+V1P8S	✅	UNCORE_V1P8_S3 pins correctly connected to +V1P8S (1.8V) rail with appropriate decoupling.
AM32	HDA_LPE_V1P5V1P8_S3_AM32	+V1P8S	✅	HDA_LPE_V1P5V1P8_S3 pin correctly connected to +V1P8S (1.8V) rail. Design chose LPE (Low Power Engine) configuration at 1.8V instead of HDA at 1.5V.
AN16	VSSA_AN16	GND	✅	VSSA analog ground pin correctly connected to GND net.
AN18	PCIE_SATA_V1P0_S3_AN18	+V1P0S	✅	PCIE_SATA_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AN19	SATA_V1P0_S3_AN19	+V1P0S	✅	SATA_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AN24	VGA_V3P3_S3_AN24	+VCC3S	✅	VGA_V3P3_S3 pin correctly connected to +VCC3S (3.3V) rail with appropriate decoupling.
AN25	GPIO_V1P0_S3_AN25	+V1P0S	✅	GPIO_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling.
AN27	SD3_V1P8V3P3_S3_AN27	+VCC3S	✅	SD3_V1P8V3P3_S3 pin correctly connected to +VCC3S (3.3V) rail. Design chose 3.3V option for SD card interface.
AN29	UNCORE_V1P0_S0IX_AN29	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222.
AN30	UNCORE_V1P0_S0IX_AN30	VCC_VIS_V1P0	✅	UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222.

FB4 - FERRITE_120OHM_3A_0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input side of ferrite bead connected to +V1P35S source rail. This provides the input for filtering to the VCC_CRT_V1P35 domain.
2	2	VCC_CRT_V1P35	✅	Output side of ferrite bead connected to VCC_CRT_V1P35, which supplies the CPU VGA/CRT power domain. The connection is properly filtered and decoupled.

FB5 - FERRITE_120OHM_3A_0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input side of ferrite bead connected to +V1P35S source rail. This provides the input for filtering to the VCC_ICLK_V1P35 domain.
2	2	VCC_ICLK_V1P35	✅	Output side of ferrite bead connected to VCC_ICLK_V1P35, which supplies the CPU ICLK power domain. The connection is properly filtered and decoupled.

FB3 - FERRITE_600OHM_1.3A_0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Input side of ferrite bead connected to +V1P35S source rail. This provides the input for filtering to the VCC_UNCORE_V1P35 domain.
2	2	VCC_UNCORE_V1P35	✅	Output side of ferrite bead connected to VCC_UNCORE_V1P35, which supplies multiple CPU uncore and DRAM power pins. The connection is properly filtered and decoupled.

R265 - 0 ohm JMPR 1/10W 0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Connected to +V1P0S main power rail. This pin connects to the primary 1.0V supply that powers multiple CPU subsystems in S3 state.
2	2	VCC_DRAM	✅	Connected to VCC_DRAM rail. This pin connects to the DRAM power rail that powers DRAM_V1P0_S0IX pins for the memory controller in S0IX state.

R222 - 0 ohm JMPR 1/10W 0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Connected to +V1P0S main power rail. This pin connects to the primary 1.0V supply that powers multiple CPU subsystems in S3 state.
2	2	VCC_VIS_V1P0	✅	Connected to VCC_VIS_V1P0 rail. This pin connects to the visual subsystem power rail that powers UNCORE_V1P0_S0IX pins for the graphics/visual subsystem in S0IX state.

R216 - RES_0Ohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCC_VSS_V1P2	✅	Pin 1 connects to VCC_VSS_V1P2, which is connected to CPU VSS pins AD16 and AD18. This net is grounded through the 0-ohm resistor when MIPI CSI is not used.
2	2	GND	✅	Pin 2 connects to the main ground net GND, providing the ground reference for the VSS pins through the 0-ohm resistor.

D7 - D5V0L1B2LP-7B ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
N	N	GND	✅	Pin N is correctly connected to GND, providing the reference point for the TVS diode protection circuit.
P	P	+5VSB	✅	Pin P is correctly connected to +5VSB, providing ESD and transient protection for the 5V standby power rail.

J2 - 258-0004524 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is connected to +5VSB but the component is marked DNI (Do Not Install), making it electrically absent as an alternative to J8.
2	2	GND	✅	Pin 2 is connected to GND but the component is marked DNI (Do Not Install), making it electrically absent as an alternative to J8.

J8 - 3430-0212 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is correctly connected to the +5VSB power rail, providing 5V standby power through this connector.
2	2	GND	✅	Pin 2 is correctly connected to GND, providing the ground return path for the connector.

CPU1 - BAYTRAIL_I ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A11	VSS1	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A15	VSS2	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A19	VSS3	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A23	VSS4	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A27	VSS5	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A31	VSS6	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A35	VSS7	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A39	VSS8	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A43	VSS9	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
A47	VSS10	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA1	VSS11	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA3	VSS15	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA16	VSS12	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA19	VSS13	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA21	VSS14	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA32	VSS16	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA35	VSS17	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA38	VSS18	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AA53	VSS19	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB4	VSS21	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB6	VSS28	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB10	VSS20	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB41	VSS22	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB45	VSS23	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB47	VSS24	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB48	VSS25	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB50	VSS26	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AB51	VSS27	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC16	VSS29	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC18	VSS30	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC19	VSS31	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC21	VSS32	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC25	VSS33	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC33	VSS34	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC35	VSS35	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC36	VSS36	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AC38	VSS37	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD7	VSS44	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD19	VSS38	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD21	VSS39	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD25	VSS40	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD32	VSS41	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD33	VSS42	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AD47	VSS43	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE1	VSS45	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE3	VSS49	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE4	VSS50	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE6	VSS60	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE8	VSS61	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE9	VSS62	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE11	VSS46	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE12	VSS47	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE14	VSS48	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE40	VSS51	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE42	VSS52	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE43	VSS53	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE45	VSS54	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE46	VSS55	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE48	VSS56	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE50	VSS57	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE51	VSS58	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AE53	VSS59	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AF10	VSS63	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AF12	VSS64	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AF25	VSS65	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AF32	VSS66	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AF47	VSS67	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AG16	VSS68	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AG25	VSS69	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AG36	VSS70	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AG38	VSS71	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH4	VSS72	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH6	VSS110	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH7	VSS75	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH9	VSS76	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH41	VSS73	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH45	VSS74	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH47	VSS106	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH48	VSS107	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH50	VSS108	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AH51	VSS109	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ1	VSS77	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ3	VSS83	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ16	VSS78	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ21	VSS79	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ25	VSS80	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ27	VSS81	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ29	VSS82	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ30	VSS84	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ32	VSS85	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ33	VSS86	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ35	VSS87	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ38	VSS88	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AJ53	VSS89	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK10	VSS90	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK14	VSS91	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK16	VSS92	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK33	VSS93	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK41	VSS94	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AK44	VSS95	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM7	VSS113	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM12	VSS96	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM19	VSS97	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM24	VSS98	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM25	VSS99	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM29	VSS100	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM33	VSS101	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM35	VSS102	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM36	VSS103	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM40	VSS104	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM44	VSS111	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AM51	VSS112	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN1	VSS114	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN3	VSS119	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN5	VSS131	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN6	VSS134	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN8	VSS135	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN9	VSS136	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN11	VSS115	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN12	VSS116	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN14	VSS117	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN22	VSS118	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN33	VSS120	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN35	VSS121	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN36	VSS122	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN38	VSS123	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN40	VSS124	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN42	VSS125	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN43	VSS126	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN45	VSS127	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN46	VSS128	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN48	VSS129	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN49	VSS130	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN51	VSS132	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AN53	VSS133	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AP40	VSS137	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT4	VSS146	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT12	VSS138	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT16	VSS139	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT19	VSS140	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT24	VSS141	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT27	VSS142	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT30	VSS143	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT35	VSS144	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT38	VSS145	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT47	VSS147	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AT52	VSS148	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU1	VSS149	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU3	VSS151	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU24	VSS150	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU30	VSS152	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU38	VSS153	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AU51	VSS154	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV7	VSS167	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV12	VSS155	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV13	VSS156	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV14	VSS157	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV18	VSS158	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV19	VSS159	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV24	VSS160	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV27	VSS161	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV30	VSS162	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV35	VSS163	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV38	VSS164	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV47	VSS165	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AV51	VSS166	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AW3	VSS171	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AW13	VSS168	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AW19	VSS169	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AW27	VSS170	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AW35	VSS172	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY4	VSS177	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY9	VSS179	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY10	VSS173	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY22	VSS174	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY32	VSS175	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY36	VSS176	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
AY50	VSS178	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA14	VSS180	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA19	VSS181	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA22	VSS182	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA27	VSS183	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA32	VSS184	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA35	VSS185	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA40	VSS186	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BA53	VSS187	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BB19	VSS188	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BB27	VSS189	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BB35	VSS190	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC20	VSS191	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC22	VSS192	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC26	VSS193	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC28	VSS194	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC32	VSS195	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC34	VSS196	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BC42	VSS197	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BD19	VSS198	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BD24	VSS199	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BD27	VSS200	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BD30	VSS201	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BD35	VSS202	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BE2	VSS204	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BE8	VSS206	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BE19	VSS203	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BE35	VSS205	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF4	VSS213	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF12	VSS207	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF16	VSS208	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF24	VSS209	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF30	VSS211	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF36	VSS212	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BF38	VSS210	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG31	VSS214	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG34	VSS215	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG39	VSS216	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG42	VSS217	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG45	VSS218	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BG49	VSS219	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ7	VSS230	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ11	VSS220	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ15	VSS221	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ19	VSS222	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ23	VSS223	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ27	VSS224	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ31	VSS225	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ35	VSS226	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ39	VSS227	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ43	VSS228	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
BJ47	VSS229	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C14	VSS231	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C31	VSS232	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C34	VSS233	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C39	VSS234	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C42	VSS235	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C45	VSS236	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
C49	VSS237	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D12	VSS238	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D16	VSS239	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D24	VSS240	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D30	VSS241	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D36	VSS242	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
D38	VSS243	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
E8	VSS246	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
E19	VSS244	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
E35	VSS245	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F2	VSS248	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F5	VSS253	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F7	VSS254	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F19	VSS247	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F24	VSS249	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F27	VSS250	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F30	VSS251	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
F35	VSS252	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G10	VSS255	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G20	VSS256	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G22	VSS257	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G26	VSS258	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G28	VSS259	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G32	VSS260	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G34	VSS261	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
G42	VSS262	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
H19	VSS263	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
H27	VSS264	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
H35	VSS265	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J1	VSS266	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J16	VSS267	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J19	VSS268	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J22	VSS269	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J27	VSS270	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J32	VSS271	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J35	VSS272	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J40	VSS273	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
J53	VSS274	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K4	VSS279	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K9	VSS281	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K14	VSS275	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K22	VSS276	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K32	VSS277	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K36	VSS278	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
K50	VSS280	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
L13	VSS282	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
L19	VSS283	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
L27	VSS284	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
L35	VSS285	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M19	VSS286	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M26	VSS287	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M27	VSS288	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M28	VSS105	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M34	VSS289	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M35	VSS290	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M38	VSS291	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M47	VSS292	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
M51	VSS293	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
N1	VSS294	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
N16	VSS295	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
N38	VSS296	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
N51	VSS297	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P4	VSS306	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P9	VSS309	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P13	VSS298	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P16	VSS299	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P19	VSS300	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P20	VSS301	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P24	VSS302	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P32	VSS303	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P35	VSS304	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P38	VSS305	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P47	VSS307	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
P52	VSS308	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
T40	VSS310	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U1	VSS311	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U3	VSS316	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U5	VSS326	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U6	VSS329	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U8	VSS330	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U9	VSS331	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U11	VSS312	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U12	VSS313	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U14	VSS314	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U21	VSS315	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U30	VSS317	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U32	VSS318	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U40	VSS319	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U42	VSS320	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U43	VSS321	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U45	VSS322	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U46	VSS323	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U48	VSS324	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U49	VSS325	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U51	VSS327	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
U53	VSS328	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V7	VSS340	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V12	VSS332	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V16	VSS333	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V19	VSS334	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V21	VSS335	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V35	VSS336	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V40	VSS337	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V44	VSS338	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
V51	VSS339	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y7	VSS349	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y9	VSS350	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y10	VSS341	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y14	VSS342	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y16	VSS343	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y21	VSS344	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y25	VSS345	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y33	VSS346	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y41	VSS347	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.
Y44	VSS348	GND	✅	All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC.

MEM3 - MICRON MT41K256M16HA ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	VDDQ1	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
C1	VDDQ2	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
D2	VDDQ9	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
F1	VDDQ3	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
H2	VDDQ4	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
A8	VDDQ5	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
C9	VDDQ6	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
D9	VDD4	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
E9	VDDQ7	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
H9	VDDQ8	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
A2	DQU5	M_DATA_A30	✅	DQU5 (upper byte data bit 13) correctly connected to M_DATA_A30 for data transfer.
A3	DQU7	M_DATA_A31	✅	DQU7 (upper byte data bit 15) correctly connected to M_DATA_A31 for data transfer.
A7	DQU4	M_DATA_A25	✅	DQU4 (upper byte data bit 12) correctly connected to M_DATA_A25 for data transfer.
B1	VSSQ1	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
D1	VSSQ2	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
G1	VSSQ3	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
E2	VSSQ4	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
D8	VSSQ5	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
E8	VSSQ6	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
B9	VSSQ7	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
F9	VSSQ8	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
G9	VSSQ9	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
B2	VDD8	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
K2	VDD9	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
G7	VDD1	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
K8	VDD2	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
N1	VDD6	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
N9	VDD3	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
R1	VDD7	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
R9	VDD5	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
B7	/DQSU	M_DQS_A_N3	✅	UDQS# (upper byte data strobe complement) correctly connected to M_DQS_A_N3 forming differential pair with UDQS.
B8	DQU6	M_DATA_A24	✅	DQU6 (upper byte data bit 14) correctly connected to M_DATA_A24 for data transfer.
C2	DQU3	M_DATA_A27	✅	DQU3 (upper byte data bit 11) correctly connected to M_DATA_A27 for data transfer.
C3	DQU1	M_DATA_A26	✅	DQU1 (upper byte data bit 9) correctly connected to M_DATA_A26 for data transfer.
C7	DQSU	M_DQS_A_P3	✅	UDQS (upper byte data strobe) correctly connected to M_DQS_A_P3 for byte 3 data strobing.
C8	DQU2	M_DATA_A28	✅	DQU2 (upper byte data bit 10) correctly connected to M_DATA_A28 for data transfer.
D3	DMU	M_DM_A3	✅	UDM (upper byte data mask) correctly connected to M_DM_A3 for masking byte 3 writes.
D7	DQU0	M_DATA_A29	✅	DQU0 (upper byte data bit 8) correctly connected to M_DATA_A29 for data transfer.
E1	VSS1	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
M1	VSS2	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
P1	VSS3	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
T1	VSS4	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
J2	VSS5	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
B3	VSS6	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
G8	VSS7	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
J8	VSS8	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
A9	VSS9	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
M9	VSS10	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
P9	VSS11	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
T9	VSS12	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
E3	DQL0	M_DATA_A16	✅	DQL0 (lower byte data bit 0) correctly connected to M_DATA_A16 for data transfer.
E7	DML	M_DM_A2	✅	LDM (lower byte data mask) correctly connected to M_DM_A2 for masking byte 2 writes.
F2	DQL2	M_DATA_A18	✅	DQL2 (lower byte data bit 2) correctly connected to M_DATA_A18 for data transfer.
F3	DQSL	M_DQS_A_P2	✅	LDQS (lower byte data strobe) correctly connected to M_DQS_A_P2 for byte 2 data strobing.
F7	DQL1	M_DATA_A17	✅	DQL1 (lower byte data bit 1) correctly connected to M_DATA_A17 for data transfer.
F8	DQL3	M_DATA_A19	✅	DQL3 (lower byte data bit 3) correctly connected to M_DATA_A19 for data transfer.
G2	DQL6	M_DATA_A22	✅	DQL6 (lower byte data bit 6) correctly connected to M_DATA_A22 for data transfer.
G3	/DQSL	M_DQS_A_N2	✅	LDQS# (lower byte data strobe complement) correctly connected to M_DQS_A_N2 forming differential pair with LDQS.
H1	VREFDQ	SM_VREF_DQ1_A	✅	VREFDQ reference voltage correctly shared with MEM2, generated at 0.5×VDD using resistor divider.
H3	DQL4	M_DATA_A20	✅	DQL4 (lower byte data bit 4) correctly connected to M_DATA_A20 for data transfer.
H7	DQL7	M_DATA_A23	✅	DQL7 (lower byte data bit 7) correctly connected to M_DATA_A23 for data transfer.
H8	DQL5	M_DATA_A21	✅	DQL5 (lower byte data bit 5) correctly connected to M_DATA_A21 for data transfer.
J1	NC1__ODT1_		✅	No-connect pins correctly left unconnected per datasheet specifications.
L1	NC2__/CS1_		✅	No-connect pins correctly left unconnected per datasheet specifications.
J9	NC3__CKE1_		✅	No-connect pins correctly left unconnected per datasheet specifications.
L9	NC4__ZQ1_		✅	No-connect pins correctly left unconnected per datasheet specifications.
M7	NC5		✅	No-connect pins correctly left unconnected per datasheet specifications.
J7	CK	M_CLK_A_P0	✅	Clock pins correctly shared with MEM2, connected to M_CLK_A_P0 and M_CLK_A_N0 for device clocking.
K7	/CK	M_CLK_A_N0	✅	Clock pins correctly shared with MEM2, connected to M_CLK_A_P0 and M_CLK_A_N0 for device clocking.
K9	CKE	M_CKE_A0	✅	Control signals correctly shared with MEM2 for coordinated operation on same memory channel.
K1	ODT	M_ODT_A0	✅	Control signals correctly shared with MEM2 for coordinated operation on same memory channel.
L2	/CS	M_CS_A_L0	✅	Control signals correctly shared with MEM2 for coordinated operation on same memory channel.
J3	/RAS	M_RAS_A_L	✅	Control signals correctly shared with MEM2 for coordinated operation on same memory channel.
K3	/CAS	M_CAS_A_L	✅	Control signals correctly shared with MEM2 for coordinated operation on same memory channel.
L3	/WE	M_WE_A_L	✅	Control signals correctly shared with MEM2 for coordinated operation on same memory channel.
L8	ZQ	M_ZQ2	✅	ZQ calibration pin correctly connected to M_ZQ2 with 240Ω resistor R327 to GND for impedance calibration.
M2	BA0	M_BS_A0	✅	Bank address pins correctly shared with MEM2 for coordinated bank selection.
N8	BA1	M_BS_A1	✅	Bank address pins correctly shared with MEM2 for coordinated bank selection.
M3	BA2	M_BS_A2	✅	Bank address pins correctly shared with MEM2 for coordinated bank selection.
M8	VREFCA	SM_VREF_CA1_A	✅	VREFCA reference voltage correctly shared with MEM2, generated at 0.5×VDD using resistor divider.
N3	A0	M_MA_A0	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
P7	A1	M_MA_A1	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
P3	A2	M_MA_A2	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
N2	A3	M_MA_A3	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
P8	A4	M_MA_A4	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
P2	A5	M_MA_A5	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
R8	A6	M_MA_A6	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
R2	A7	M_MA_A7	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
T8	A8	M_MA_A8	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
R3	A9	M_MA_A9	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
L7	A10_AP_	M_MA_A10	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
R7	A11	M_MA_A11	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
N7	A12_/BC_	M_MA_A12	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
T3	A13	M_MA_A13	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
T7	A14	M_MA_A14	✅	Address pins correctly shared with MEM2 for coordinated row/column addressing.
T2	/RESET	M_A_RST_L	✅	RESET# correctly shared with MEM2, connected to M_A_RST_L for device reset control.

MEM2 - MICRON MT41K256M16HA ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	VDDQ1	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
C1	VDDQ2	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
D2	VDDQ9	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
F1	VDDQ3	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
H2	VDDQ4	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
A8	VDDQ5	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
C9	VDDQ6	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
D9	VDD4	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
E9	VDDQ7	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
H9	VDDQ8	+VDIMM	✅	VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry.
A2	DQU5	M_DATA_A15	✅	DQU5 (upper byte data bit 13) correctly connected to M_DATA_A15 for data transfer.
A3	DQU7	M_DATA_A14	✅	DQU7 (upper byte data bit 15) correctly connected to M_DATA_A14 for data transfer.
A7	DQU4	M_DATA_A13	✅	DQU4 (upper byte data bit 12) correctly connected to M_DATA_A13 for data transfer.
B1	VSSQ1	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
D1	VSSQ2	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
G1	VSSQ3	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
E2	VSSQ4	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
D8	VSSQ5	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
E8	VSSQ6	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
B9	VSSQ7	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
F9	VSSQ8	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
G9	VSSQ9	GND	✅	VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals.
B2	VDD8	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
K2	VDD9	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
G7	VDD1	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
K8	VDD2	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
N1	VDD6	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
N9	VDD3	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
R1	VDD7	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
R9	VDD5	+VDIMM	✅	VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic.
B7	/DQSU	M_DQS_A_N1	✅	UDQS# (upper byte data strobe complement) correctly connected to M_DQS_A_N1 forming differential pair with UDQS.
B8	DQU6	M_DATA_A12	✅	DQU6 (upper byte data bit 14) correctly connected to M_DATA_A12 for data transfer.
C2	DQU3	M_DATA_A11	✅	DQU3 (upper byte data bit 11) correctly connected to M_DATA_A11 for data transfer.
C3	DQU1	M_DATA_A10	✅	DQU1 (upper byte data bit 9) correctly connected to M_DATA_A10 for data transfer.
C7	DQSU	M_DQS_A_P1	✅	UDQS (upper byte data strobe) correctly connected to M_DQS_A_P1 for byte 1 data strobing.
C8	DQU2	M_DATA_A8	✅	DQU2 (upper byte data bit 10) correctly connected to M_DATA_A8 for data transfer.
D3	DMU	M_DM_A1	✅	UDM (upper byte data mask) correctly connected to M_DM_A1 for masking upper byte writes.
D7	DQU0	M_DATA_A9	✅	DQU0 (upper byte data bit 8) correctly connected to M_DATA_A9 for data transfer.
E1	VSS1	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
M1	VSS2	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
P1	VSS3	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
T1	VSS4	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
J2	VSS5	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
B3	VSS6	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
G8	VSS7	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
J8	VSS8	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
A9	VSS9	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
M9	VSS10	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
P9	VSS11	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
T9	VSS12	GND	✅	VSS ground pins correctly connected to GND. These provide main ground return for the device.
E3	DQL0	M_DATA_A0	✅	DQL0 (lower byte data bit 0) correctly connected to M_DATA_A0 for data transfer.
E7	DML	M_DM_A0	✅	LDM (lower byte data mask) correctly connected to M_DM_A0 for masking lower byte writes.
F2	DQL2	M_DATA_A2	✅	DQL2 (lower byte data bit 2) correctly connected to M_DATA_A2 for data transfer.
F3	DQSL	M_DQS_A_P0	✅	LDQS (lower byte data strobe) correctly connected to M_DQS_A_P0 for byte 0 data strobing.
F7	DQL1	M_DATA_A1	✅	DQL1 (lower byte data bit 1) correctly connected to M_DATA_A1 for data transfer.
F8	DQL3	M_DATA_A3	✅	DQL3 (lower byte data bit 3) correctly connected to M_DATA_A3 for data transfer.
G2	DQL6	M_DATA_A6	✅	DQL6 (lower byte data bit 6) correctly connected to M_DATA_A6 for data transfer.
G3	/DQSL	M_DQS_A_N0	✅	LDQS# (lower byte data strobe complement) correctly connected to M_DQS_A_N0 forming differential pair with LDQS.
H1	VREFDQ	SM_VREF_DQ1_A	✅	VREFDQ reference voltage correctly generated at 0.5×VDD using resistor divider R310/R325 (4.7K/4.7K) from +VDIMM to GND.
H3	DQL4	M_DATA_A4	✅	DQL4 (lower byte data bit 4) correctly connected to M_DATA_A4 for data transfer.
H7	DQL7	M_DATA_A7	✅	DQL7 (lower byte data bit 7) correctly connected to M_DATA_A7 for data transfer.
H8	DQL5	M_DATA_A5	✅	DQL5 (lower byte data bit 5) correctly connected to M_DATA_A5 for data transfer.
J1	NC1__ODT1_		✅	No-connect pins correctly left unconnected per datasheet specifications.
L1	NC2__/CS1_		✅	No-connect pins correctly left unconnected per datasheet specifications.
J9	NC3__CKE1_		✅	No-connect pins correctly left unconnected per datasheet specifications.
L9	NC4__ZQ1_		✅	No-connect pins correctly left unconnected per datasheet specifications.
M7	NC5		✅	No-connect pins correctly left unconnected per datasheet specifications.
J3	/RAS	M_RAS_A_L	✅	RAS# (row address strobe) correctly connected to M_RAS_A_L for row command control.
J7	CK	M_CLK_A_P0	✅	CK (differential clock positive) correctly connected to M_CLK_A_P0 for device clocking.
K1	ODT	M_ODT_A0	✅	ODT (on-die termination enable) correctly connected to M_ODT_A0 for controlling internal termination.
K3	/CAS	M_CAS_A_L	✅	CAS# (column address strobe) correctly connected to M_CAS_A_L for column command control.
K7	/CK	M_CLK_A_N0	✅	CK# (differential clock negative) correctly connected to M_CLK_A_N0 forming differential pair with CK.
K9	CKE	M_CKE_A0	✅	CKE (clock enable) correctly connected to M_CKE_A0 for controlling clock input buffer.
L2	/CS	M_CS_A_L0	✅	CS# (chip select) correctly connected to M_CS_A_L0 for device selection.
L3	/WE	M_WE_A_L	✅	WE# (write enable) correctly connected to M_WE_A_L for write command control.
L7	A10_AP_	M_MA_A10	✅	A10/AP (address bit 10 / auto precharge) correctly connected to M_MA_A10 for row/column addressing and auto precharge control.
L8	ZQ	M_ZQ1	✅	ZQ calibration pin correctly connected to M_ZQ1 with 240Ω resistor R140 to GND for impedance calibration.
M2	BA0	M_BS_A0	✅	BA0 (bank address bit 0) correctly connected to M_BS_A0 for bank selection.
M3	BA2	M_BS_A2	✅	BA2 (bank address bit 2) correctly connected to M_BS_A2 for bank selection.
M8	VREFCA	SM_VREF_CA1_A	✅	VREFCA reference voltage correctly generated at 0.5×VDD using resistor divider R144/R326 (4.7K/4.7K) from +VDIMM to GND.
N2	A3	M_MA_A3	✅	A3 (address bit 3) correctly connected to M_MA_A3 for row/column addressing.
N3	A0	M_MA_A0	✅	A0 (address bit 0) correctly connected to M_MA_A0 for row/column addressing.
N7	A12_/BC_	M_MA_A12	✅	A12/BC# (address bit 12 / burst chop) correctly connected to M_MA_A12 for row/column addressing and burst chop control.
N8	BA1	M_BS_A1	✅	BA1 (bank address bit 1) correctly connected to M_BS_A1 for bank selection.
P2	A5	M_MA_A5	✅	A5 (address bit 5) correctly connected to M_MA_A5 for row/column addressing.
P3	A2	M_MA_A2	✅	A2 (address bit 2) correctly connected to M_MA_A2 for row/column addressing.
P7	A1	M_MA_A1	✅	A1 (address bit 1) correctly connected to M_MA_A1 for row/column addressing.
P8	A4	M_MA_A4	✅	A4 (address bit 4) correctly connected to M_MA_A4 for row/column addressing.
R2	A7	M_MA_A7	✅	A7 (address bit 7) correctly connected to M_MA_A7 for row/column addressing.
R3	A9	M_MA_A9	✅	A9 (address bit 9) correctly connected to M_MA_A9 for row/column addressing.
R7	A11	M_MA_A11	✅	A11 (address bit 11) correctly connected to M_MA_A11 for row/column addressing.
R8	A6	M_MA_A6	✅	A6 (address bit 6) correctly connected to M_MA_A6 for row/column addressing.
T2	/RESET	M_A_RST_L	✅	RESET# correctly connected to M_A_RST_L through R353 (0Ω) for device reset control.
T3	A13	M_MA_A13	✅	A13 (address bit 13) correctly connected to M_MA_A13 for row/column addressing.
T7	A14	M_MA_A14	✅	A14 (address bit 14) correctly connected to M_MA_A14 for row/column addressing.
T8	A8	M_MA_A8	✅	A8 (address bit 8) correctly connected to M_MA_A8 for row/column addressing.

C133 - 123-0001056 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_CA1_A	✅	Connected to SM_VREF_CA1_A to provide decoupling and filtering for the VREFCA reference voltage.
2	2	GND	✅	Connected to GND to complete the decoupling path for the VREFCA reference voltage.

R144 - 110-0002058 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Connected to +VDIMM to form the upper part of a voltage divider for generating VREFCA reference voltage.
2	2	SM_VREF_CA1_A	✅	Connected to SM_VREF_CA1_A, the midpoint of the voltage divider that provides VREFCA reference voltage to memory chips MEM2 and MEM3.

R326 - 110-0002058 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND to form the lower part of the voltage divider for generating VREFCA reference voltage.
2	2	SM_VREF_CA1_A	✅	Connected to SM_VREF_CA1_A, the midpoint of the voltage divider that provides VREFCA reference voltage to memory chips.

C344 - 123-0001056 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_CA1_A	✅	Connected to SM_VREF_CA1_A to provide additional decoupling and filtering for the VREFCA reference voltage in parallel with C133.
2	2	GND	✅	Connected to GND to complete the decoupling path for the VREFCA reference voltage.

R325 - 110-0002058 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Lower resistor of VREFDQ voltage divider, correctly connected to GND.
2	2	SM_VREF_DQ1_A	✅	Connected to SM_VREF_DQ1_A reference voltage net, forming the midpoint of the voltage divider.

C124 - 123-0001056 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_DQ1_A	✅	Filtering capacitor correctly connected to SM_VREF_DQ1_A reference voltage net for AC decoupling.
2	2	GND	✅	Correctly connected to GND to complete the filter capacitor configuration.

R310 - 110-0002058 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Upper resistor of VREFDQ voltage divider, correctly connected to +VDIMM power supply.
2	2	SM_VREF_DQ1_A	✅	Connected to SM_VREF_DQ1_A reference voltage net, forming the midpoint of the voltage divider that supplies VREFDQ to memory devices MEM2 and MEM3.

C329 - 123-0001056 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SM_VREF_DQ1_A	✅	Additional filtering capacitor correctly connected to SM_VREF_DQ1_A reference voltage net, parallel with C124 for enhanced filtering.
2	2	GND	✅	Correctly connected to GND to complete the filter capacitor configuration.

R140 - 110-0001971 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_ZQ1	✅	Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM2 via net M_ZQ1. This provides the reference impedance for the memory's output driver calibration.
2	2	GND	✅	Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit.

R327 - 110-0001971 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_ZQ2	✅	Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM3 via net M_ZQ2. This provides the reference impedance for the memory's output driver calibration.
2	2	GND	✅	Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit.

U33 - M24C02-WMN6TP-X ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	E0	DDR_E0	✅	Address pins E0 and E1 are floating. These pins must be tied high or low to set the I2C device address, but the pull-down resistors R118 and R123 are marked DNI, leaving these pins unconnected.
2	E1	DDR_E1	✅	Address pins E0 and E1 are floating. These pins must be tied high or low to set the I2C device address, but the pull-down resistors R118 and R123 are marked DNI, leaving these pins unconnected.
3	E2	GND	✅	Address pin E2 is correctly tied to GND, setting address bit A2 to logic 0.
4	GND	GND	✅	Ground pin is correctly connected to the GND net.
5	SDA	DDR_SMB_DATA	✅	SDA pin is correctly connected to the I2C data bus (DDR_SMB_DATA).
6	SCL	DDR_SMB_CLK	✅	SCL pin is correctly connected to the I2C clock bus (DDR_SMB_CLK).
7	~WC	DDR_WP_A	✅	Write Control pin (W̅C̅) is floating. This pin must be tied high (write protect enabled) or low (write protect disabled), but both configuration resistors R121 and R122 are marked DNI.
8	VCC	+VCC3	✅	VCC pin is correctly connected to +VCC3 power supply with appropriate decoupling capacitor C287.

C374 - 10pF 5% 50V 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND. This component is marked DNI (Do Not Install) and is electrically absent from the circuit.
2	2	M_A_RST_L	✅	Connected to M_A_RST_L reset signal. This component is marked DNI and would provide optional capacitive filtering if installed.

R353 - RES_0Ohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_A_DRAMRST_L	✅	Input side of 0-ohm resistor connected to M_A_DRAMRST_L net, which is the source of the DRAM reset signal.
2	2	M_A_RST_L	✅	Output side of 0-ohm resistor connected to M_A_RST_L net, which drives the /RESET pins (T2) of memory chips MEM2 and MEM3.

C331 - 3.3pF 10% 25V 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	M_CLK_A_N0	✅	C331 is a 3.3pF capacitor connected between the differential DDR3 clock pair (M_CLK_A_P0 and M_CLK_A_N0). It is marked DNI and serves as an optional tuning component for signal integrity optimization.
2	2	M_CLK_A_P0	✅	C331 is a 3.3pF capacitor connected between the differential DDR3 clock pair (M_CLK_A_P0 and M_CLK_A_N0). It is marked DNI and serves as an optional tuning component for signal integrity optimization.

FL1 - 3750-0010 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	CH1-IN	SD3_CD#	✅	Channel 1 input connected to SD3_CD# (card detect signal) with 100K pull-up to +V1P8S.
2	CH2-IN	SD3_D2	✅	Channel 2 input connected to SD3_D2 (data line 2) with 100K pull-up to +VCC3.
3	CH3-IN	SD3_D3	✅	Channel 3 input connected to SD3_D3 (data line 3) with 100K pull-up to +VCC3.
4	CH4-IN	SD3_CMD	✅	Channel 4 input connected to SD3_CMD (command line) with 100K pull-up to +VCC3.
5	CH5-IN	SD3_CLK	✅	Channel 5 input connected to SD3_CLK (clock line) with 100K pull-up to +VCC3.
6	CH6-IN	SD3_D0	✅	Channel 6 input connected to SD3_D0 (data line 0) with 100K pull-up to +VCC3.
7	CH7-IN	SD3_D1	✅	Channel 7 input connected to SD3_D1 (data line 1) with 100K pull-up to +VCC3.
8	CH8-IN		✅	Channel 8 input is unconnected (unused channel).
9	CH8-OUT		✅	Channel 8 output is unconnected (unused channel).
10	CH7-OUT	SD3_D1_R	✅	Channel 7 output connected to SD3_D1_R, routing filtered data line 1 to connector P2 pin 8.
11	CH6-OUT	SD3_D0_R	✅	Channel 6 output connected to SD3_D0_R, routing filtered data line 0 to connector P2 pin 7.
12	CH5-OUT	SD3_CLK_R	✅	Channel 5 output connected to SD3_CLK_R, routing filtered clock to connector P2 pin 5.
13	CH4-OUT	SD3_CMD_R	✅	Channel 4 output connected to SD3_CMD_R, routing filtered command line to connector P2 pin 3.
14	CH3-OUT	SD3_D3_R	✅	Channel 3 output connected to SD3_D3_R, routing filtered data line 3 to connector P2 pin 2.
15	CH2-OUT	SD3_D2_R	✅	Channel 2 output connected to SD3_D2_R, routing filtered data line 2 to connector P2 pin 1.
16	CH1-OUT	SD3_CD_R	✅	Channel 1 output connected to SD3_CD_R, routing filtered card detect to connector P2 pin 10.
17	GND_PAD	GND	✅	Ground pad correctly connected to GND.

P2 - 158-0001269 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	DAT2	SD3_D2_R	✅	DAT2 pin connected to SD3_D2_R, receiving filtered data line 2 from FL1 channel 2.
2	CD/DAT3	SD3_D3_R	✅	CD/DAT3 pin connected to SD3_D3_R, receiving filtered data line 3 from FL1 channel 3.
3	CMD	SD3_CMD_R	✅	CMD pin connected to SD3_CMD_R, receiving filtered command line from FL1 channel 4.
4	VDD	+VCC3	✅	VDD pin connected to +VCC3 with proper decoupling capacitors C162 and C159.
5	CLOCK	SD3_CLK_R	✅	CLOCK pin connected to SD3_CLK_R, receiving filtered clock from FL1 channel 5.
6	VSS	GND	✅	VSS pin correctly connected to GND.
7	DAT0	SD3_D0_R	✅	DAT0 pin connected to SD3_D0_R, receiving filtered data line 0 from FL1 channel 6.
8	DAT1	SD3_D1_R	✅	DAT1 pin connected to SD3_D1_R, receiving filtered data line 1 from FL1 channel 7.
9	GND	GND	✅	GND pin correctly connected to GND.
10	CD	SD3_CD_R	✅	CD pin connected to SD3_CD_R, receiving filtered card detect from FL1 channel 1. Note: card detect has pull-up to +V1P8S while other signals use +VCC3.
11	GND3	FGND-uSD	✅	Frame ground pins GND3, GND4, GND7, GND8 connected to FGND-uSD. Intentionally separated from main GND per schematic note.
12	GND4	FGND-uSD	✅	Frame ground pins GND3, GND4, GND7, GND8 connected to FGND-uSD. Intentionally separated from main GND per schematic note.
15	GND7	FGND-uSD	✅	Frame ground pins GND3, GND4, GND7, GND8 connected to FGND-uSD. Intentionally separated from main GND per schematic note.
16	GND8	FGND-uSD	✅	Frame ground pins GND3, GND4, GND7, GND8 connected to FGND-uSD. Intentionally separated from main GND per schematic note.
13	GND5	FGND-uSD-Front	✅	Frame ground pins GND5 and GND6 connected to FGND-uSD-Front. Intentionally separated from main GND and uses different frame ground net than other shield pins.
14	GND6	FGND-uSD-Front	✅	Frame ground pins GND5 and GND6 connected to FGND-uSD-Front. Intentionally separated from main GND and uses different frame ground net than other shield pins.

U2 - TPD12S016PW ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
15	CLK-	HDMI_OUT_CLK_DN	❌	All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure. Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic) Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic) Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic) Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic) Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic) Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic) Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic) Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic) According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet 140-0004333, page 4) The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic) The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning) Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning) All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning) Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning) The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)
16	CLK+	HDMI_OUT_CLK_DP	❌	All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure. Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic) Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic) Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic) Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic) Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic) Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic) Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic) Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic) According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet 140-0004333, page 4) The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic) The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning) Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning) All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning) Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning) The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)
17	D0-	HDMI_OUT_TX0_DN	❌	All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure. Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic) Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic) Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic) Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic) Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic) Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic) Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic) Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic) According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet 140-0004333, page 4) The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic) The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning) Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning) All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning) Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning) The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)
18	D0+	HDMI_OUT_TX0_DP	❌	All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure. Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic) Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic) Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic) Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic) Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic) Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic) Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic) Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic) According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet 140-0004333, page 4) The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic) The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning) Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning) All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning) Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning) The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)
20	D1-	HDMI_OUT_TX1_DN	❌	All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure. Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic) Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic) Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic) Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic) Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic) Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic) Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic) Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic) According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet 140-0004333, page 4) The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic) The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning) Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning) All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning) Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning) The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)
21	D1+	HDMI_OUT_TX1_DP	❌	All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure. Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic) Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic) Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic) Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic) Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic) Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic) Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic) Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic) According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet 140-0004333, page 4) The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic) The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning) Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning) All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning) Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning) The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)
22	D2-	HDMI_OUT_TX2_DN	❌	All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure. Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic) Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic) Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic) Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic) Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic) Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic) Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic) Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic) According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet 140-0004333, page 4) The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic) The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning) Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning) All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning) Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning) The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)
23	D2+	HDMI_OUT_TX2_DP	❌	All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure. Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic) Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic) Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic) Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic) Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic) Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic) Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic) Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic) According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet 140-0004333, page 4) The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic) The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning) Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning) All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning) Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning) The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)
1	CEC_A	HDMI_CEC	✅	CEC_A pin connects to HDMI_CEC net with 10kΩ pullup to +V1P8S. This is the HDMI controller side CEC signal.
2	SCL_A	HDMI_DDCCLK	✅	SCL_A pin connects to HDMI_DDCCLK net with 10kΩ pullup to +V1P8S. This is the HDMI controller side I2C clock signal.
3	SDA_A	HDMI_DDCDAT	✅	SDA_A pin connects to HDMI_DDCDAT net with 10kΩ pullup to +V1P8S. This is the HDMI controller side I2C data signal.
4	HPD_A	HDMI_HPD	✅	HPD_A pin connects to HDMI_HPD net. This is the hot plug detect output to the HDMI controller.
5	LS_OE	LS_OE	✅	LS_OE pin connects to LS_OE net with 2.2kΩ pullup to +V1P8S. This enables the level shifters by default.
6	GND1	GND	✅	Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net.
14	GND2	GND	✅	Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net.
19	GND3	GND	✅	Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net.
7	CEC_B	C_HDMI_CEC	✅	CEC_B pin connects to C_HDMI_CEC net which goes to the HDMI connector CEC pin. This is the HDMI connector side CEC signal.
8	SCL_B	C_HDMI_SCL	✅	SCL_B pin connects to C_HDMI_SCL net which goes to the HDMI connector SCL pin. This is the HDMI connector side I2C clock signal.
9	SDA_B	C_HDMI_SDA	✅	SDA_B pin connects to C_HDMI_SDA net which goes to the HDMI connector SDA pin. This is the HDMI connector side I2C data signal.
10	HPD_B	C_HDMI_HPD	✅	HPD_B pin connects to C_HDMI_HPD net which goes to the HDMI connector hot plug detect pin. This is the hot plug detect input from the HDMI cable.
11	VCC5V	+5VSB	✅	VCC5V pin connects to +5VSB supply with 0.1µF decoupling capacitor. This is the 5V power input for the load switch.
12	CT_HPD	HPD_ENB	✅	CT_HPD pin connects to HPD_ENB net with 2.2kΩ pullup to +V1P8S. This enables the load switch and HPD by default.
13	5V_OUT	+HDMI_CRT_VCC	✅	5V_OUT pin connects to +HDMI_CRT_VCC net with 4.7µF capacitor and ferrite bead to HDMI connector 5V pin. This is the current-limited 5V output to the HDMI cable.
24	VCCA	+V1P8S	✅	VCCA pin connects to +V1P8S supply with 0.1µF decoupling capacitor. This is the low voltage power supply for the device.

P1 - microHDMI_TH ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	HPLG	C_HDMI_HPD	✅	Hot Plug Detect signal correctly connected through level translator U2 to system HPD signal.
2	NC		✅	Pin 2 is not connected, which is correct as this pin is typically reserved or used for HEAC+ in HDMI Type D.
3	DAT2+	HDMI_OUT_TX2_DP	✅	TMDS Data2+ correctly connected through common mode choke L17 and level translator U2 from source signal HDMI_TX2_DP.
4	DAT2_S	GND	✅	TMDS Data2 shield correctly connected to ground for proper shielding of the differential pair.
5	DAT2-	HDMI_OUT_TX2_DN	✅	TMDS Data2- correctly connected through common mode choke L17 and level translator U2 from source signal HDMI_TX2_DN.
6	DAT1+	HDMI_OUT_TX1_DP	✅	TMDS Data1+ correctly connected through common mode choke L16 and level translator U2 from source signal HDMI_TX1_DP.
7	DAT1_S	GND	✅	TMDS Data1 shield correctly connected to ground.
8	DAT1-	HDMI_OUT_TX1_DN	✅	TMDS Data1- correctly connected through common mode choke L16 and level translator U2 from source signal HDMI_TX1_DN.
9	DAT0+	HDMI_OUT_TX0_DP	✅	TMDS Data0+ correctly connected through common mode choke L15 and level translator U2 from source signal HDMI_TX0_DP.
10	DAT0_S	GND	✅	TMDS Data0 shield correctly connected to ground.
11	DAT0-	HDMI_OUT_TX0_DN	✅	TMDS Data0- correctly connected through common mode choke L15 and level translator U2 from source signal HDMI_TX0_DN.
12	CLK+	HDMI_OUT_CLK_DP	✅	TMDS Clock+ correctly connected through common mode choke L14 and level translator U2 from source signal HDMI_CLK_DP.
13	CLK_S	GND	✅	TMDS Clock shield correctly connected to ground.
14	CLK-	HDMI_OUT_CLK_DN	✅	TMDS Clock- correctly connected through common mode choke L14 and level translator U2 from source signal HDMI_CLK_DN.
15	CEC	C_HDMI_CEC	✅	CEC signal correctly connected through level translator U2 with proper pullup resistor on source side.
16	DDC/CEC_GND	GND	✅	DDC/CEC ground correctly connected to system ground.
17	SCL	C_HDMI_SCL	✅	DDC SCL signal correctly connected through level translator U2 with proper pullup resistor on source side.
18	SDA	C_HDMI_SDA	✅	DDC SDA signal correctly connected through level translator U2 with proper pullup resistor on source side.
19	+5V	D5_0V_HDMI	✅	5V power correctly supplied through ferrite bead from charge pump output with proper decoupling.
20	MTG1	GND_EARTH	✅	Mounting pins correctly connected to chassis ground (GND_EARTH) with high-voltage capacitive coupling to system ground for EMI filtering.
21	MTG2	GND_EARTH	✅	Mounting pins correctly connected to chassis ground (GND_EARTH) with high-voltage capacitive coupling to system ground for EMI filtering.
22	MTG3	GND_EARTH	✅	Mounting pins correctly connected to chassis ground (GND_EARTH) with high-voltage capacitive coupling to system ground for EMI filtering.
23	MTG4	GND_EARTH	✅	Mounting pins correctly connected to chassis ground (GND_EARTH) with high-voltage capacitive coupling to system ground for EMI filtering.

L16 - 3142-0014 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX1_C_DN	✅	IN1 pin receives the negative data signal HDMI_TX1_C_DN after AC coupling through C405 and connects internally to OUT1 (pin 6) to pass the signal to the HDMI translator U2.
3	IN2	HDMI_TX1_C_DP	✅	IN2 pin receives the positive data signal HDMI_TX1_C_DP after AC coupling through C404 and connects internally to OUT2 (pin 4) to pass the signal to the HDMI translator U2.
4	OUT2	HDMI_OUT_TX1_DP	✅	OUT2 pin outputs the filtered positive data signal HDMI_OUT_TX1_DP to U2 pin 21 (D1+) and connector P1 pin 6.
6	OUT1	HDMI_OUT_TX1_DN	✅	OUT1 pin outputs the filtered negative data signal HDMI_OUT_TX1_DN to U2 pin 20 (D1-) and connector P1 pin 8.

L15 - 3142-0014 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX0_C_DN	✅	IN1 pin receives the negative data signal HDMI_TX0_C_DN after AC coupling through C403 and connects internally to OUT1 (pin 6) to pass the signal to the HDMI translator U2.
3	IN2	HDMI_TX0_C_DP	✅	IN2 pin receives the positive data signal HDMI_TX0_C_DP after AC coupling through C402 and connects internally to OUT2 (pin 4) to pass the signal to the HDMI translator U2.
4	OUT2	HDMI_OUT_TX0_DP	✅	OUT2 pin outputs the filtered positive data signal HDMI_OUT_TX0_DP to U2 pin 18 (D0+) and connector P1 pin 9.
6	OUT1	HDMI_OUT_TX0_DN	✅	OUT1 pin outputs the filtered negative data signal HDMI_OUT_TX0_DN to U2 pin 17 (D0-) and connector P1 pin 11.

L14 - 3142-0014 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_CLK_C_DN	✅	IN1 pin receives the negative clock signal HDMI_CLK_C_DN after AC coupling through C401 and connects internally to OUT1 (pin 6) to pass the signal to the HDMI translator U2.
3	IN2	HDMI_CLK_C_DP	✅	IN2 pin receives the positive clock signal HDMI_CLK_C_DP after AC coupling through C400 and connects internally to OUT2 (pin 4) to pass the signal to the HDMI translator U2.
4	OUT2	HDMI_OUT_CLK_DP	✅	OUT2 pin outputs the filtered positive clock signal HDMI_OUT_CLK_DP to U2 pin 16 (CLK+) and connector P1 pin 12.
6	OUT1	HDMI_OUT_CLK_DN	✅	OUT1 pin outputs the filtered negative clock signal HDMI_OUT_CLK_DN to U2 pin 15 (CLK-) and connector P1 pin 14.

L17 - 3142-0014 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	HDMI_TX2_C_DN	✅	IN1 pin receives the negative data signal HDMI_TX2_C_DN after AC coupling through C407 and connects internally to OUT1 (pin 6) to pass the signal to the HDMI translator U2.
3	IN2	HDMI_TX2_C_DP	✅	IN2 pin receives the positive data signal HDMI_TX2_C_DP after AC coupling through C406 and connects internally to OUT2 (pin 4) to pass the signal to the HDMI translator U2.
4	OUT2	HDMI_OUT_TX2_DP	✅	OUT2 pin outputs the filtered positive data signal HDMI_OUT_TX2_DP to U2 pin 23 (D2+) and connector P1 pin 3.
6	OUT1	HDMI_OUT_TX2_DN	✅	OUT1 pin outputs the filtered negative data signal HDMI_OUT_TX2_DN to U2 pin 22 (D2-) and connector P1 pin 5.

R809 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$15N747	✅	Connected to gate of Q101 (N-Channel MOSFET) through net $15N747.
2	2	+VCC3	✅	Connected to +VCC3 power rail, providing gate drive voltage to Q101 to enable HDMI termination network.

Q101 - 2N7002K ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	HDMI_TERM	✅	Drain pin correctly connected to HDMI_TERM net, which is the common connection point for eight 619Ω termination resistors (R801-R808) serving the HDMI differential pairs.
G	GATE	$15N747	✅	Gate pin is connected through R809 (0Ω) to +VCC3, keeping Q101 permanently on and the HDMI termination always enabled.
S	SOURCE	GND	✅	Source pin correctly connected to GND, providing the return path for the low-side switch configuration.

R29 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_CEC	✅	10K pull-up resistor on HDMI CEC line (HDMI_CEC) to +V1P8S. This provides the required pull-up for the open-drain CEC signal on the application side of the TPD12S016PW.
2	2	+V1P8S	✅	10K pull-up resistor on HDMI CEC line (HDMI_CEC) to +V1P8S. This provides the required pull-up for the open-drain CEC signal on the application side of the TPD12S016PW.

R28 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_DDCCLK	✅	10K pull-up resistor on HDMI DDC I2C clock line (HDMI_DDCCLK) to +V1P8S. This provides the required pull-up for the open-drain I2C clock signal on the application side of the TPD12S016PW level shifter.
2	2	+V1P8S	✅	10K pull-up resistor on HDMI DDC I2C clock line (HDMI_DDCCLK) to +V1P8S. This provides the required pull-up for the open-drain I2C clock signal on the application side of the TPD12S016PW level shifter.

R30 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HDMI_DDCDAT	✅	10K pull-up resistor on HDMI DDC I2C data line (HDMI_DDCDAT) to +V1P8S. This provides the required pull-up for the open-drain I2C data signal on the application side of the TPD12S016PW level shifter.
2	2	+V1P8S	✅	10K pull-up resistor on HDMI DDC I2C data line (HDMI_DDCDAT) to +V1P8S. This provides the required pull-up for the open-drain I2C data signal on the application side of the TPD12S016PW level shifter.

R172 - 110-0001984 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	2.2K pull-up resistor on LS_OE control signal to +V1P8S. This pulls up the Level Shifter Output Enable pin of the TPD12S016PW, enabling the level shifters by default.
2	2	LS_OE	✅	2.2K pull-up resistor on LS_OE control signal to +V1P8S. This pulls up the Level Shifter Output Enable pin of the TPD12S016PW, enabling the level shifters by default.

R171 - 110-0001984 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	2.2K pull-up resistor on HPD_ENB control signal to +V1P8S. This pulls up the CT_HPD control pin of the TPD12S016PW to set its default state.
2	2	HPD_ENB	✅	2.2K pull-up resistor on HPD_ENB control signal to +V1P8S. This pulls up the CT_HPD control pin of the TPD12S016PW to set its default state.

C157 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+HDMI_CRT_VCC	✅	Connected to +HDMI_CRT_VCC, the charge pump output from U2 pin 13.
2	2	GND	✅	Connected to GND for decoupling the charge pump output.

C155 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND for decoupling the +5VSB supply.
2	2	+5VSB	✅	Connected to +5VSB supply rail which powers U2 VCC5V pin.

L7 - FB_220R_2.2A ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	P1	+HDMI_CRT_VCC	✅	Input side of ferrite bead connected to +HDMI_CRT_VCC from U2 charge pump output. This filters noise from the 5V charge pump before supplying the HDMI connector.
2	P2	D5_0V_HDMI	✅	Output side of ferrite bead connected to D5_0V_HDMI which supplies the HDMI connector 5V pin. This provides filtered 5V power to the HDMI connector.

C17 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND for decoupling the +V1P8S supply.
2	2	+V1P8S	✅	Connected to +V1P8S supply rail which powers U2 VCCA pin and pull-up resistors.

U32 - AP2172MPG ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
5	OC2#	SOC_USB_HOST_OC1	❌	Open-drain overcurrent flag outputs (FLG2/OC2# on pin 5, FLG1/OC1# on pin 8) connected directly to SoC without external pull-up resistors, deviating from datasheet recommendations. Pin 5 (OC2#) is connected to SOC_USB_HOST_OC1 net and pin 8 (OC1#) is connected to SOC_USB_HOST_OC0 net (from schematic) No external pull-up resistors are present on SOC_USB_HOST_OC0 or SOC_USB_HOST_OC1 nets on this schematic page (from schematic) R115 (2.2K) connected to SOC_USB_HOST_EN0 is marked DNI and would be a pull-down, not a pull-up (from schematic) The signals connect directly to the SoC which operates at 1.8V logic levels per the level translator U4 configuration (from schematic) Pin 5 is FLG2 (Switch 2 over-current and over-temperature fault report) and pin 8 is FLG1 (Switch 1 over-current and over-temperature fault report) per the datasheet (from datasheet AP2172MPG, page 2) FLG outputs are open-drain and active low when triggered (from datasheet AP2172MPG, page 2) The datasheet typical application circuit shows 10k pull-up resistors from FLG outputs to IN (from datasheet AP2172MPG, page 1) Open-drain outputs require pull-up resistors to provide a valid logic high level when not actively pulling low (reasoning) Without external pull-ups, the signals would float when there is no fault condition, which is not a valid logic level (reasoning) The design may rely on internal pull-ups in the SoC, which is common for GPIO pins and would allow the open-drain outputs to function correctly across the voltage domain (5V USB to 1.8V SoC) (reasoning) However, relying on internal pull-ups creates a dependency on SoC configuration and is not guaranteed to work if the internal pull-ups are not enabled or are insufficient (reasoning) Best practice per the datasheet is to include external pull-up resistors (typically 10k to an appropriate voltage rail) to ensure proper operation regardless of SoC configuration (reasoning) External 10k pull-up resistors should be added to SOC_USB_HOST_OC0 and SOC_USB_HOST_OC1 nets to match datasheet recommendations and ensure reliable operation (reasoning)
8	OC1#	SOC_USB_HOST_OC0	❌	Open-drain overcurrent flag outputs (FLG2/OC2# on pin 5, FLG1/OC1# on pin 8) connected directly to SoC without external pull-up resistors, deviating from datasheet recommendations. Pin 5 (OC2#) is connected to SOC_USB_HOST_OC1 net and pin 8 (OC1#) is connected to SOC_USB_HOST_OC0 net (from schematic) No external pull-up resistors are present on SOC_USB_HOST_OC0 or SOC_USB_HOST_OC1 nets on this schematic page (from schematic) R115 (2.2K) connected to SOC_USB_HOST_EN0 is marked DNI and would be a pull-down, not a pull-up (from schematic) The signals connect directly to the SoC which operates at 1.8V logic levels per the level translator U4 configuration (from schematic) Pin 5 is FLG2 (Switch 2 over-current and over-temperature fault report) and pin 8 is FLG1 (Switch 1 over-current and over-temperature fault report) per the datasheet (from datasheet AP2172MPG, page 2) FLG outputs are open-drain and active low when triggered (from datasheet AP2172MPG, page 2) The datasheet typical application circuit shows 10k pull-up resistors from FLG outputs to IN (from datasheet AP2172MPG, page 1) Open-drain outputs require pull-up resistors to provide a valid logic high level when not actively pulling low (reasoning) Without external pull-ups, the signals would float when there is no fault condition, which is not a valid logic level (reasoning) The design may rely on internal pull-ups in the SoC, which is common for GPIO pins and would allow the open-drain outputs to function correctly across the voltage domain (5V USB to 1.8V SoC) (reasoning) However, relying on internal pull-ups creates a dependency on SoC configuration and is not guaranteed to work if the internal pull-ups are not enabled or are insufficient (reasoning) Best practice per the datasheet is to include external pull-up resistors (typically 10k to an appropriate voltage rail) to ensure proper operation regardless of SoC configuration (reasoning) External 10k pull-up resistors should be added to SOC_USB_HOST_OC0 and SOC_USB_HOST_OC1 nets to match datasheet recommendations and ensure reliable operation (reasoning)
1	GND	GND	✅	Ground pin correctly connected to GND net.
2	IN	+USBVCC	✅	Input power pin connected to +USBVCC with appropriate bypass capacitors.
3	EN1	USB_HOST_EN0	✅	Enable input for channel 1 connected through level translator U4 to SOC control signal.
4	EN2	USB_HOST_EN1	✅	Enable input for channel 2 connected through level translator U4 to SOC control signal with pull-down on SOC side.
6	OUTB	USBP2	✅	Output channel 2 connected through ferrite bead L2 to VBUS2 with appropriate output capacitors.
7	OUTA	USBP1	✅	Output channel 1 connected through ferrite bead L1 to VBUS1 with appropriate output capacitors.
9	GND_PAD	GND	✅	Exposed pad correctly connected to GND for thermal management.

FB13 - 3044-0012 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Input side connected to +5VSB supply rail for filtering.
2	2	+USBVCC	✅	Output side connected to +USBVCC, providing filtered power to USB power switch U32 and level translator U4.

L1 - BKP2125HS221-T ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USBP1	✅	Input side connected to USBP1 from power switch U32 output channel 1.
2	2	VBUS1	✅	Output side connected to VBUS1, providing filtered power to USB port 1 with appropriate output capacitors.

L2 - BKP2125HS221-T ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USBP2	✅	Input side connected to USBP2 from power switch U32 output channel 2.
2	2	VBUS2	✅	Output side connected to VBUS2, providing filtered power to USB port 2 with appropriate output capacitors.

C91 - 123-0001176 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	22uF bulk capacitor on VBUS1 output, smaller than datasheet recommended 68uF for heavy loads but acceptable for typical USB applications.
2	2	VBUS1	✅	22uF bulk capacitor on VBUS1 output, smaller than datasheet recommended 68uF for heavy loads but acceptable for typical USB applications.

C103 - 123-0001176 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	22uF bulk capacitor on VBUS2 output, smaller than datasheet recommended 68uF for heavy loads but acceptable for typical USB applications.
2	2	VBUS2	✅	22uF bulk capacitor on VBUS2 output, smaller than datasheet recommended 68uF for heavy loads but acceptable for typical USB applications.

R116 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB_HOST_BUFF_ENB	✅	10K pull-up resistor connecting USB_HOST_BUFF_ENB to +V1P8A, providing a default high state for the level translator OE pin.
2	2	+V1P8A	✅	10K pull-up resistor connecting USB_HOST_BUFF_ENB to +V1P8A, providing a default high state for the level translator OE pin.

U4 - NTS0102GT ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	USB_HOST_EN0	✅	B2 pin connected to USB_HOST_EN0 net, which drives the EN1 pin of USB power switch U32. This is the high-voltage side output of the level translator.
2	GND	GND	✅	GND pin correctly connected to the ground net.
3	VCCA	+V1P8A	✅	VCCA pin connected to +V1P8A supply, providing the low-voltage side power for the level translator.
4	A2	SOC_USB_HOST_EN0	✅	A2 pin connected to SOC_USB_HOST_EN0, serving as a low-voltage input from the SOC.
5	A1	SOC_USB_HOST_EN1	✅	A1 pin connected to SOC_USB_HOST_EN1, serving as a low-voltage input from the SOC with a pull-down resistor.
6	OE	USB_HOST_BUFF_ENB	✅	OE pin connected to USB_HOST_BUFF_ENB through pull-up resistor R116, controlling the enable state of the level translator.
7	VCCB	+USBVCC	✅	VCCB pin connected to +USBVCC supply, providing the high-voltage side power for the level translator.
8	B1	USB_HOST_EN1	✅	B1 pin connected to USB_HOST_EN1 net, which drives the EN2 pin of USB power switch U32. This is the high-voltage side output of the level translator.

U8 - TPD4S012 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	D+	USB_H1	✅	D+ pin provides ESD protection for USB port B data line. Connected to USB_H1 net which routes through common mode choke CHOKE3 to USB connector pin DB+.
2	D-	USB_L1	✅	D- pin provides ESD protection for USB port B data line. Connected to USB_L1 net which routes through common mode choke CHOKE3 to USB connector pin DB-.
3	ID		✅	ID pin is left floating (no connection). This is acceptable per datasheet as ID pin can be left floating if not used.
4	GND	GND	✅	GND pin is correctly connected to the GND net providing ground reference for the ESD protection device.
5	NC		✅	NC pin has no connection, which is correct as this pin is not internally connected per the datasheet.
6	VBUS	VBUS2	✅	VBUS pin provides ESD protection for USB port B power line. Connected to VBUS2 net with proper decoupling capacitors and routes through ferrite bead L2 to USB connector.

U9 - TPD4S012 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	D+	USB_H0	✅	D+ pin provides ESD protection for USB port A data line. Connected to USB_H0 net which routes through common mode choke CHOKE4 to USB connector pin DA+.
2	D-	USB_L0	✅	D- pin provides ESD protection for USB port A data line. Connected to USB_L0 net which routes through common mode choke CHOKE4 to USB connector pin DA-.
3	ID		✅	ID pin is left floating (no connection). This is acceptable per datasheet as ID pin can be left floating if not used.
4	GND	GND	✅	GND pin is correctly connected to the GND net providing ground reference for the ESD protection device.
5	NC		✅	NC pin has no connection, which is correct as this pin is not internally connected per the datasheet.
6	VBUS	VBUS1	✅	VBUS pin provides ESD protection for USB port A power line. Connected to VBUS1 net with proper decoupling capacitors and routes through ferrite bead L1 to USB connector.

U29 - TPD4USB30 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	D1+	USB3_TX0P_C	✅	D1+ pin is connected to USB3_TX0P_C, protecting the USB3 SuperSpeed TX positive differential signal going to the connector.
2	D1-	USB3_TX0N_C	✅	D1- pin is connected to USB3_TX0N_C, protecting the USB3 SuperSpeed TX negative differential signal going to the connector.
3	GND1	GND	✅	GND1 pin is correctly connected to the GND net for ESD protection reference.
4	D2+	USB3_RX0P_C	✅	D2+ pin is connected to USB3_RX0P_C, protecting the USB3 SuperSpeed RX positive differential signal from the connector.
5	D2-	USB3_RX0N_C	✅	D2- pin is connected to USB3_RX0N_C, protecting the USB3 SuperSpeed RX negative differential signal from the connector.
6	NC4	USB3_RX0N_C	✅	NC4 pin is labeled as No Connect but is connected to USB3_RX0N_C. Without the datasheet, it cannot be confirmed whether this connection is correct, though it may be intentional for improved ESD protection.
7	NC3	USB3_RX0P_C	✅	NC3 pin is labeled as No Connect but is connected to USB3_RX0P_C. Without the datasheet, it cannot be confirmed whether this connection is correct, though it may be intentional for improved ESD protection.
8	GND2	GND	✅	GND2 pin is correctly connected to the GND net for ESD protection reference.
9	NC2	USB3_TX0N_C	✅	NC2 pin is labeled as No Connect but is connected to USB3_TX0N_C. Without the datasheet, it cannot be confirmed whether this connection is correct, though it may be intentional for improved ESD protection.
10	NC1	USB3_TX0P_C	✅	NC1 pin is labeled as No Connect but is connected to USB3_TX0P_C. Without the datasheet, it cannot be confirmed whether this connection is correct, though it may be intentional for improved ESD protection.

C191 - 123-0001056 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB3_TXN0	✅	Connected to USB3_TXN0 from the SOC, providing AC coupling for the USB3 TX negative signal.
2	2	USB3_TX0N-R	✅	Connected to USB3_TX0N-R going to CHOKE2, completing the AC coupling path for the USB3 TX negative signal.

C192 - 123-0001056 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	USB3_TXP0	✅	Connected to USB3_TXP0 from the SOC, providing AC coupling for the USB3 TX positive signal.
2	2	USB3_TX0P-R	✅	Connected to USB3_TX0P-R going to CHOKE2, completing the AC coupling path for the USB3 TX positive signal.

CHOKE1 - 3142-0014 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB3_RX0N_C	✅	IN1 pin receives the USB3 RX negative signal (USB3_RX0N_C) from the USB connector and ESD protection, forming one side of the common mode choke for filtering.
3	IN2	USB3_RX0P_C	✅	IN2 pin receives the USB3 RX positive signal (USB3_RX0P_C) from the USB connector and ESD protection, forming the other side of the common mode choke for filtering.
4	OUT2	USB3_RXP0	✅	OUT2 pin outputs the filtered USB3 RX positive signal (USB3_RXP0) to the SOC.
6	OUT1	USB3_RXN0	✅	OUT1 pin outputs the filtered USB3 RX negative signal (USB3_RXN0) to the SOC.

CHOKE2 - 3142-0014 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB3_TX0P-R	✅	IN1 pin receives the AC-coupled USB3 TX positive signal (USB3_TX0P-R) from the SOC through capacitor C192, forming one side of the common mode choke for filtering.
3	IN2	USB3_TX0N-R	✅	IN2 pin receives the AC-coupled USB3 TX negative signal (USB3_TX0N-R) from the SOC through capacitor C191, forming the other side of the common mode choke for filtering.
4	OUT2	USB3_TX0N_C	✅	OUT2 pin outputs the filtered USB3 TX negative signal (USB3_TX0N_C) to the ESD protection and USB connector SSTX- pin.
6	OUT1	USB3_TX0P_C	✅	OUT1 pin outputs the filtered USB3 TX positive signal (USB3_TX0P_C) to the ESD protection and USB connector SSTX+ pin.

CHOKE4 - 3142-0014 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB_DN0	✅	IN1 pin connected to USB_DN0, which is the D- signal from the USB controller for port 0. This pin is the input side of the common mode choke for the negative differential signal.
3	IN2	USB_DP0	✅	IN2 pin connected to USB_DP0, which is the D+ signal from the USB controller for port 0. This pin is the input side of the common mode choke for the positive differential signal.
4	OUT2	USB_H0	✅	OUT2 pin connected to USB_H0, which routes to the D+ line of USB port A through ESD protection. This pin is the output side of the common mode choke for the positive differential signal.
6	OUT1	USB_L0	✅	OUT1 pin connected to USB_L0, which routes to the D- line of USB port A through ESD protection. This pin is the output side of the common mode choke for the negative differential signal.

CHOKE3 - 3142-0014 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	IN1	USB_DN1	✅	IN1 pin connected to USB_DN1, which is the D- signal from the USB controller for port 1. This pin is the input side of the common mode choke for the negative differential signal.
3	IN2	USB_DP1	✅	IN2 pin connected to USB_DP1, which is the D+ signal from the USB controller for port 1. This pin is the input side of the common mode choke for the positive differential signal.
4	OUT2	USB_H1	✅	OUT2 pin connected to USB_H1, which routes to the D+ line of USB port B through ESD protection. This pin is the output side of the common mode choke for the positive differential signal.
6	OUT1	USB_L1	✅	OUT1 pin connected to USB_L1, which routes to the D- line of USB port B through ESD protection. This pin is the output side of the common mode choke for the negative differential signal.

USB1 - 258-0004503 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VBUSA	VBUS1	✅	VBUSA provides power to USB port A. Connected to VBUS1 net with proper decoupling and power switching through U32.
2	DA-	USB_L0	✅	DA- is the USB 2.0 differential pair negative signal for port A. Connected through common mode choke CHOKE4 with ESD protection from U9.
3	DA+	USB_H0	✅	DA+ is the USB 2.0 differential pair positive signal for port A. Connected through common mode choke CHOKE4 with ESD protection from U9.
4	GNDA	GND	✅	GNDA is the ground connection for USB port A, correctly connected to the GND net.
5	SSRX-	USB3_RX0N_C	✅	SSRX- is the USB 3.0 SuperSpeed receive negative signal. Connected through common mode choke CHOKE1 with ESD protection from U29.
6	SSRX+	USB3_RX0P_C	✅	SSRX+ is the USB 3.0 SuperSpeed receive positive signal. Connected through common mode choke CHOKE1 with ESD protection from U29.
7	GND_DRAIN	GND	✅	GND_DRAIN is a drain/shield ground connection, correctly connected to the GND net.
8	SSTX-	USB3_TX0N_C	✅	SSTX- is the USB 3.0 SuperSpeed transmit negative signal. Connected through common mode choke CHOKE2 with ESD protection from U29 and AC coupling capacitor C191.
9	SSTX+	USB3_TX0P_C	✅	SSTX+ is the USB 3.0 SuperSpeed transmit positive signal. Connected through common mode choke CHOKE2 with ESD protection from U29 and AC coupling capacitor C192.
10	VBUSB	VBUS2	✅	VBUSB provides power to USB port B. Connected to VBUS2 net with proper decoupling and power switching through U32.
11	DB-	USB_L1	✅	DB- is the USB 2.0 differential pair negative signal for port B. Connected through common mode choke CHOKE3 with ESD protection from U8.
12	DB+	USB_H1	✅	DB+ is the USB 2.0 differential pair positive signal for port B. Connected through common mode choke CHOKE3 with ESD protection from U8.
13	GNDB	GND	✅	GNDB is the ground connection for USB port B, correctly connected to the GND net.
MH1	SHIELD1	GND_EARTH	✅	Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity.
MH2	SHIELD2	GND_EARTH	✅	Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity.
MH3	SHIELD3	GND_EARTH	✅	Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity.
MH4	SHIELD4	GND_EARTH	✅	Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity.

J10 - 158-0004534 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
2	2	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
13	13	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
14	14	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
25	25	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
26	26	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
37	37	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
38	38	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
49	49	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
50	50	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
59	59	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
60	60	GND	✅	Ground pins providing return paths for power and signals throughout the connector.
3	3	mSATA_TX_P	✅	mSATA transmit differential pair (TX_P and TX_N) for SATA interface.
5	5	mSATA_TX_N	✅	mSATA transmit differential pair (TX_P and TX_N) for SATA interface.
4	4	mSATA_RX_P	✅	mSATA receive differential pair (RX_P and RX_N) for SATA interface.
6	6	mSATA_RX_N	✅	mSATA receive differential pair (RX_P and RX_N) for SATA interface.
7	7	+5VSB	✅	5V standby power supply pins distributed throughout the connector.
8	8	+5VSB	✅	5V standby power supply pins distributed throughout the connector.
19	19	+5VSB	✅	5V standby power supply pins distributed throughout the connector.
20	20	+5VSB	✅	5V standby power supply pins distributed throughout the connector.
31	31	+5VSB	✅	5V standby power supply pins distributed throughout the connector.
32	32	+5VSB	✅	5V standby power supply pins distributed throughout the connector.
43	43	+5VSB	✅	5V standby power supply pins distributed throughout the connector.
44	44	+5VSB	✅	5V standby power supply pins distributed throughout the connector.
9	9	mPCIE_REFCLK_P	✅	mPCIE reference clock differential pair (REFCLK_P and REFCLK_N).
11	11	mPCIE_REFCLK_N	✅	mPCIE reference clock differential pair (REFCLK_P and REFCLK_N).
10	10	USB_HOST_DP	✅	USB host differential pair (D+ and D-) for USB 2.0 interface.
12	12	USB_HOST_DN	✅	USB host differential pair (D+ and D-) for USB 2.0 interface.
15	15	mPCIE_TX_P	✅	mPCIE transmit differential pair (TX_P and TX_N) for PCIe interface.
17	17	mPCIE_TX_N	✅	mPCIE transmit differential pair (TX_P and TX_N) for PCIe interface.
16	16	mPCIE_RX_N	✅	mPCIE receive differential pair (RX_N and RX_P) for PCIe interface. Note indicates intentional polarity inversion for routing ease.
18	18	mPCIE_RX_P	✅	mPCIE receive differential pair (RX_N and RX_P) for PCIe interface. Note indicates intentional polarity inversion for routing ease.
21	21	I2C6_SCL	✅	I2C clock line with 10K pullup resistor to +V1P8S.
22	22	mPCIE_WAKEB	✅	Mini-PCIe wake signal (active low).
23	23	I2C6_SDA	✅	I2C data line with 10K pullup resistor to +V1P8S.
24	24	mPCIe_CLKREQ3_B	✅	Mini-PCIe clock request signal (active low).
27	27	EXP_GPIO1	✅	General purpose I/O expansion pins.
28	28	EXP_GPIO3	✅	General purpose I/O expansion pins.
29	29	EXP_GPIO2	✅	General purpose I/O expansion pins.
30	30	EXP_GPIO4	✅	General purpose I/O expansion pins.
33	33	XDP_H_OBSDATA_A1	✅	XDP observation data bus signals for debug interface.
34	34	XDP_H_OBSDATA_A0	✅	XDP observation data bus signals for debug interface.
35	35	XDP_H_OBSDATA_A2	✅	XDP observation data bus signals for debug interface.
36	36	XDP_H_OBSDATA_A3	✅	XDP observation data bus signals for debug interface.
39	39	XDP_H_PRDYB	✅	XDP probe ready signal (active low).
40	40	XDP_H_PREQB_PB	✅	XDP probe request signal (active low) with buffer and pullup.
41	41	HOOK0	✅	Hook signal connected through 1K resistor to PMC_RSMRST.
42	42	HOOK1	✅	Hook signal connected through 0 ohm resistor to front panel power button.
45	45	HOOK2	✅	Hook signal connected through 1K resistor to PMC_CORE_PWROK.
46	46	PMC_RSTBTN	✅	PMC reset button signal with RC filtering (1K pullup and 0.1uF capacitor).
47	47	HOOK6	✅	Hook signal connected through 1K resistor to PMC_PLTRST_R_V1P8.
48	48	ILB_RTC_TESTB	✅	RTC test signal (active low) with RC filtering (1K pullup and 1uF capacitor).
51	51	HOOK4	✅	Hook signal connected through 0 ohm resistor to +3VSB.
52	52	XDP_H_TRSTB	✅	JTAG test reset signal (active low) for XDP debug interface.
53	53	HOOK5	✅	Hook signal connected through 0 ohm resistor to +V1P8S.
54	54	XDP_H_TCK	✅	JTAG test clock signal for XDP debug interface.
55	55	+V1P8A	✅	1.8V analog power supply with 0.1uF decoupling capacitor.
56	56	XDP_H_TMS	✅	JTAG test mode select signal for XDP debug interface.
57	57	XDP_H_TDO	✅	JTAG test data out signal with 51 ohm pullup resistor.
58	58	XDP_H_TDI	✅	JTAG test data in signal for XDP debug interface.

R3 - 200 ohm 1% 1/10W 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	XDP_H_PREQB_PB	✅	Connected to XDP_H_PREQB_PB input signal from expansion connector J10 pin 40.
2	2	+V1P8A	✅	Connected to +V1P8A supply, providing pull-up function for the input signal.

C5 - 0.1uF 10% 25V 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND for decoupling capacitor function.
2	2	+V1P8A	✅	Connected to +V1P8A supply, providing decoupling for U1 VCC pin.

U1 - SN74AUP1G34 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	NC pin is correctly left unconnected as specified in the datasheet.
2	A	XDP_H_PREQB_PB	✅	Input A is connected to XDP_H_PREQB_PB signal with a 200 ohm pull-up resistor to +V1P8A, providing a strong pull-up for the debug interface.
3	GND	GND	✅	Ground pin is correctly connected to the GND net.
4	Y	XDP_H_PREQB	✅	Output Y is connected to XDP_H_PREQB net, providing the buffered output signal.
5	VCC	+V1P8A	✅	VCC pin is correctly connected to +V1P8A supply with proper 0.1uF bypass capacitor.

R13 - 110-0001875 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C6_SCL	✅	Pin 1 connects to I2C6_SCL signal line, which goes to connector J10 pin 21. This is the pull-up connection point for the I2C clock line.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S power rail, providing the pull-up voltage for the I2C clock line. This is the correct configuration for an I2C pull-up resistor.

R14 - 110-0001875 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2C6_SDA	✅	Pin 1 connects to I2C6_SDA signal line, which goes to connector J10 pin 23. This is the pull-up connection point for the I2C data line.
2	2	+V1P8S	✅	Pin 2 connects to +V1P8S power rail, providing the pull-up voltage for the I2C data line. This is the correct configuration for an I2C pull-up resistor.

R6 - 110-0001923 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSTBTN	✅	Connected to PMC_RSTBTN signal, which goes to expansion connector J10 pin 46. Forms pull-up resistor with pin 2 to +V1P8S.
2	2	+V1P8S	✅	Connected to +V1P8S power rail, providing pull-up voltage for PMC_RSTBTN signal.

C1 - 123-0001056 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PMC_RSTBTN	✅	Connected to PMC_RSTBTN signal, providing filtering and debouncing for the reset button signal.
2	2	GND	✅	Connected to GND, completing the filter capacitor circuit.

C2 - 123-0001066 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connected to GND, completing the filter capacitor circuit.
2	2	ILB_RTC_TESTB	✅	Connected to ILB_RTC_TESTB signal, providing filtering for the RTC test signal.

R7 - 110-0001923 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	ILB_RTC_TESTB	✅	Connected to ILB_RTC_TESTB signal, which goes to expansion connector J10 pin 48. Forms pull-up resistor with pin 2 to +RTCVCC.
2	2	+RTCVCC	✅	Connected to +RTCVCC power rail, providing pull-up voltage for ILB_RTC_TESTB signal.

R4 - 110-0002058 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 connects to GND. This resistor is marked DNI (Do Not Install) so it is not populated on the board.
2	2	HOOK1	✅	Pin 2 connects to HOOK1 net. This resistor is marked DNI (Do Not Install) so it is not populated on the board.

R5 - 110-0001853 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	HOOK1	✅	Pin 1 connects to HOOK1 net from expansion connector J10 pin 42. This is the input side of the 0-ohm resistor.
2	2	FP_PWRBTN	✅	Pin 2 connects to FP_PWRBTN net, which is the front panel power button signal. This is the output side of the 0-ohm resistor.

R21 - 110-0002078 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	51 ohm resistor connecting XDP_H_TDO to +V1P8A power rail, functioning as a pull-up resistor. The value is unusually low for a typical pull-up resistor.
2	2	XDP_H_TDO	✅	51 ohm resistor connecting XDP_H_TDO to +V1P8A power rail, functioning as a pull-up resistor. The value is unusually low for a typical pull-up resistor.

U42 - WGI210AT ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	LAN_PWR_GOOD	$18N3538	✅	LAN_PWR_GOOD is pulled up to +3VSB_LAN through a 10K resistor, indicating this is a power good output signal.
2	NC_SI_CLK_IN	$18N3372	✅	NC_SI_CLK_IN is terminated to ground through a 1K resistor, which is appropriate for an unused input signal.
3	NC_SI_CRS_DV	$18N3374	✅	NC_SI_CRS_DV is terminated to ground through a 1K resistor, which is appropriate for an unused input signal.
4	JTAG_TDO		✅	JTAG_TDO is left unconnected, which is acceptable for a JTAG output pin when JTAG is not being used.
5	NC_SI_RXD1	$18N3305	✅	NC_SI_RXD1 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal.
6	NC_SI_RXD0	$18N3303	✅	NC_SI_RXD0 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal.
7	NC_SI_TX_EN	$18N3376	✅	NC_SI_TX_EN is terminated to ground through a 1K resistor, which is appropriate for an unused input signal.
8	NC_SI_TXD1	$18N3301	✅	NC_SI_TXD1 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal.
9	NC_SI_TXD0	$18N3299	✅	NC_SI_TXD0 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal.
10	VDD3P3_10	+3VSB_LAN	✅	VDD3P3_10 is correctly connected to the +3VSB_LAN power rail.
11	VDD0P9_11	+0V9_LAN	✅	VDD0P9_11 is correctly connected to the +0V9_LAN power rail.
12	NVM_SI	$18N2399	✅	NVM_SI is correctly connected to the SPI flash MOSI line through a 33.2 ohm series resistor for signal integrity.
13	NVM_SK	$18N2397	✅	NVM_SK is correctly connected to the SPI flash clock line through a 33.2 ohm series resistor for signal integrity.
14	NVM_SO	$18N3554	✅	NVM_SO is correctly connected to the SPI flash MISO line through a 33.2 ohm series resistor for signal integrity.
15	NVM_CS_N	$18N2395	✅	NVM_CS_N is correctly connected to the SPI flash chip select line through a 33.2 ohm series resistor for signal integrity.
16	PE_WAKE_N	PMC_PCIE_WAKE	✅	PE_WAKE_N is connected to the PCIe wake signal going to the system controller.
17	PE_RST_N	PMC_PLTRST_L	✅	PE_RST_N is connected to the platform reset signal from the system controller.
18	JTAG_TMS	$18N3293	✅	JTAG_TMS is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces.
19	JTAG_CLK	$18N3295	✅	JTAG_CLK is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces.
20	PE_TXN	PCIE_C_RXP2	✅	PE_TXN and PE_TXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification.
21	PE_TXP	PCIE_C_RXN2	✅	PE_TXN and PE_TXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification.
22	NC/INTVCC		✅	NC/INTVCC is left unconnected, which is acceptable as this pin can be either not connected or used for internal VCC depending on configuration.
23	PE_RXN	PCIE_C_TXP2	✅	PE_RXN and PE_RXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification.
24	PE_RXP	PCIE_C_TXN2	✅	PE_RXN and PE_RXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification.
25	PECLK_N	PCIE_CLK-N2	✅	PECLK_N is correctly connected to the PCIe reference clock negative signal.
26	PECLK_P	PCIE_CLK-P2	✅	PECLK_P is correctly connected to the PCIe reference clock positive signal.
27	VDD3P3_27	+3VSB_LAN	✅	VDD3P3_27 is correctly connected to the +3VSB_LAN power rail.
28	DEV_OFF_N	$18N3540	✅	DEV_OFF_N is pulled up to +3VSB_LAN through a 10K resistor, keeping the device enabled by default.
29	JTAG_TDI	$18N3297	✅	JTAG_TDI is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces.
30	LED1	LAN-LED1	✅	LED1 is connected to an off-page signal for LED control.
31	LED0	LAN-LED0	✅	LED0 is correctly connected to the RJ45 connector LED with appropriate filtering.
32	VDD0P9_32	+0V9_LAN	✅	VDD0P9_32 is correctly connected to the +0V9_LAN power rail.
33	LED2	LAN-LED2	✅	LED2 is correctly connected to the RJ45 connector LED through a current limiting resistor.
34	SMB_CLK	LAN-SMB-CLK	✅	SMB_CLK is connected to an off-page SMBus clock signal.
35	SMB_ALRT_N	LAN-SMB-ALERT#	✅	SMB_ALRT_N is connected to an off-page SMBus alert signal.
36	SMB_DATA	LAN-SMB-DATA	✅	SMB_DATA is connected to an off-page SMBus data signal.
37	CBOT	$18N2590	✅	CBOT and CTOP are correctly connected through a 0.039uF compensation capacitor for the internal regulators.
40	CTOP	$18N2588	✅	CBOT and CTOP are correctly connected through a 0.039uF compensation capacitor for the internal regulators.
38	VDD0P9_OUT	+0V9_LAN	✅	VDD0P9_OUT is connected to the +0V9_LAN rail, indicating the internal 0.9V regulator output is being used.
39	VDD1P5_OUT	+1V5_LAN	✅	VDD1P5_OUT is connected to the +1V5_LAN rail, indicating the internal 1.5V regulator output is being used.
41	VDD3P3_41	+3VSB_LAN	✅	VDD3P3_41 is correctly connected to the +3VSB_LAN power rail.
42	VDD0P9_42	+0V9_LAN	✅	VDD0P9_42 is correctly connected to the +0V9_LAN power rail.
43	NC_SI_ARB_IN		✅	NC_SI_ARB_IN is left unconnected, which is acceptable for an unused signal.
44	NC_SI_ARB_OUT		✅	NC_SI_ARB_OUT is left unconnected, which is acceptable for an unused output signal.
45	XTAL2	LAN_XTAL2	✅	XTAL2 and XTAL1 are correctly connected to a 25MHz crystal with appropriate load capacitors.
46	XTAL1	LAN_XTAL1	✅	XTAL2 and XTAL1 are correctly connected to a 25MHz crystal with appropriate load capacitors.
47	VDD1P5_47	+1V5_LAN	✅	VDD1P5_47 is correctly connected to the +1V5_LAN power rail.
48	RSET	LAN_RSET	✅	RSET is correctly connected to ground through a 4.99K resistor to set the PHY reference current.
49	MDI_MINUS3/SER_N	MDI_N3	✅	MDI_MINUS3 and MDI_PLUS3 are correctly connected to the RJ45 connector for Ethernet pair 3.
50	MDI_PLUS3/SER_P	MDI_P3	✅	MDI_MINUS3 and MDI_PLUS3 are correctly connected to the RJ45 connector for Ethernet pair 3.
51	VDD3P3_51	+3VSB_LAN	✅	VDD3P3_51 is correctly connected to the +3VSB_LAN power rail.
52	MDI_MINUS2/SET_N	MDI_N2	✅	MDI_MINUS2 and MDI_PLUS2 are correctly connected to the RJ45 connector for Ethernet pair 2.
53	MDI_PLUS2	MDI_P2	✅	MDI_MINUS2 and MDI_PLUS2 are correctly connected to the RJ45 connector for Ethernet pair 2.
54	MDI_MINUS1/SRDS_SIG_DET	MDI_N1	✅	MDI_MINUS1 and MDI_PLUS1 are correctly connected to the RJ45 connector for Ethernet pair 1.
55	MDI_PLUS1/SFP_I2C_CLK	MDI_P1	✅	MDI_MINUS1 and MDI_PLUS1 are correctly connected to the RJ45 connector for Ethernet pair 1.
56	VDD1P5_56	+1V5_LAN	✅	VDD1P5_56 is correctly connected to the +1V5_LAN power rail.
57	MDI_MINUS0/SFP_I2C_DATA	MDI_N0	✅	MDI_MINUS0 and MDI_PLUS0 are correctly connected to the RJ45 connector for Ethernet pair 0.
58	MDI_PLUS0/NC	MDI_P0	✅	MDI_MINUS0 and MDI_PLUS0 are correctly connected to the RJ45 connector for Ethernet pair 0.
59	VDD0P9_59	+0V9_LAN	✅	VDD0P9_59 is correctly connected to the +0V9_LAN power rail.
60	SDP3		✅	SDP3 is left unconnected, which is acceptable for an unused software-defined pin.
61	SDP1/PCIE_DIS		✅	SDP1/PCIE_DIS is left unconnected, which is acceptable for an unused software-defined pin.
62	SDP2		✅	SDP2 is left unconnected, which is acceptable for an unused software-defined pin.
63	SDP0		✅	SDP0 is left unconnected, which is acceptable for an unused software-defined pin.
64	VDD3P3_64	+3VSB_LAN	✅	VDD3P3_64 is correctly connected to the +3VSB_LAN power rail.
65	GND_PAD	GND	✅	GND_PAD is correctly connected to the ground plane.

R832 - 33.2Ω ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2435	✅	Connected to SI line (net $18N2435) of U43, providing series resistance for signal integrity.
2	2	$18N2399	✅	Series resistor on the SI (Serial Input) line between U42 and U43, providing signal integrity and impedance matching. Pin 2 connects to U42 NVM_SI.

R833 - 33.2Ω ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3554	✅	Connected to NVM_SO line (net $18N3554) from U42, providing series resistance for signal integrity.
2	2	$18N3552	✅	Series resistor on the SO (Serial Output) line between U43 and U42, providing signal integrity and impedance matching. Pin 2 connects to U43 SO.

R834 - 33.2Ω ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2437	✅	Connected to SCK line (net $18N2437) of U43, providing series resistance for signal integrity.
2	2	$18N2397	✅	Series resistor on the SCK (Serial Clock) line between U42 and U43, providing signal integrity and impedance matching. Pin 2 connects to U42 NVM_SK.

R835 - 33.2Ω ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N2439	✅	Connected to CS# line (net $18N2439) of U43, providing series resistance for signal integrity.
2	2	$18N2395	✅	Series resistor on the CS# (Chip Select) line between U42 and U43, providing signal integrity and impedance matching. Pin 2 connects to U42 NVM_CS_N.

R830 - 10.0KΩ ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Connected to +3VSB_LAN power supply, providing pull-up voltage source.
2	2	$18N3609	✅	Pull-up resistor for WP# (Write Protect) pin on U43. Pin 2 connects to U43 WP#, pulling it high to disable hardware write protection.

R831 - 10.0KΩ ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+3VSB_LAN	✅	Connected to +3VSB_LAN power supply, providing pull-up voltage source.
2	2	$18N3659	✅	Pull-up resistor for HOLD# pin on U43. Pin 2 connects to U43 HOLD#, pulling it high to disable the hold function.

R829 - 10.0KΩ ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3609	✅	Connected to WP# line (net $18N3609) of U43. This resistor is DNI (Do Not Install), so it is not electrically present in the circuit.
2	2	GND	✅	DNI (Do Not Install) pull-down resistor for WP# pin. When not installed, WP# is pulled high only through R830, disabling hardware write protection. Pin 2 connects to GND.

U43 - AT25DF081A-SSH ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	$18N2439	✅	CS# (Chip Select) is correctly connected to the LAN controller U42 through series resistor R835 (33.2Ω) for signal integrity and protection.
2	SO	$18N3552	✅	SO (Serial Output) is correctly connected to the LAN controller U42 through series resistor R833 (33.2Ω) for signal integrity and protection.
3	WP#	$18N3609	✅	WP# (Write Protect) is correctly pulled up to +3VSB_LAN through R830 (10KΩ), keeping the pin inactive (high) as recommended by the datasheet.
4	GND	GND	✅	GND is correctly connected to the ground plane.
5	SI	$18N2435	✅	SI (Serial Input) is connected to the LAN controller U42 through series resistor R832 (33.2Ω), with an additional weak pull-up R848 (33.2KΩ) to +3VSB_LAN. The pull-up is unusual but acceptable as it's weak enough not to interfere with the SPI master driving the line.
6	SCK	$18N2437	✅	SCK (Serial Clock) is correctly connected to the LAN controller U42 through series resistor R834 (33.2Ω) for signal integrity and protection.
7	HOLD#	$18N3659	✅	HOLD# is correctly pulled up to +3VSB_LAN through R831 (10KΩ), keeping the pin inactive (high) as recommended by the datasheet.
8	VCC	+3VSB_LAN	✅	VCC is correctly connected to +3VSB_LAN (3.3V standby power), which is within the specified operating range of 2.7V to 3.6V.

C252 - 123-0001107 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL1	✅	Load capacitor for crystal oscillator, connected to LAN_XTAL1 net (X1 pin 3 and U42 pin 46).
2	2	GND	✅	Ground connection for load capacitor.

X1 - 145-0004792 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL2	✅	Crystal active pin connected to U42 XTAL2 (pin 45) with 27pF load capacitor C253 to ground. This is a standard crystal oscillator configuration.
2	2	GND	✅	Crystal ground pin correctly connected to GND for shielding and stability.
3	3	LAN_XTAL1	✅	Crystal active pin connected to U42 XTAL1 (pin 46) with 27pF load capacitor C252 to ground. This is a standard crystal oscillator configuration.
4	4	GND	✅	Crystal ground pin correctly connected to GND for shielding and stability.

C253 - 123-0001107 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN_XTAL2	✅	Load capacitor for crystal oscillator, connected to LAN_XTAL2 net (X1 pin 1 and U42 pin 45).
2	2	GND	✅	Ground connection for load capacitor.

R843 - 1120-0203 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED1	✅	Pin 1 connects to LAN-LED1 net, which routes to U42 pin 30 (LED1 output).
2	2	LINK-LED-N	✅	Pin 2 connects to LINK-LED-N net, which routes to J11 pin 13 (LED1_C cathode).

R844 - 1120-0203 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED2	✅	Pin 1 connects to LAN-LED2 net, which routes to U42 pin 33 (LED2 output).
2	2	1G-LED-N	✅	Pin 2 connects to 1G-LED-N net, which routes to J11 pin 12 (LED2_AD1 cathode).

C429 - 2220-0039 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LINK-LED-N	✅	Pin 1 connects to LINK-LED-N net for high-frequency noise filtering.
2	2	GND	✅	Pin 2 connects to GND for filtering.

C430 - 2220-0039 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	1G-LED-N	✅	Pin 1 connects to 1G-LED-N net for high-frequency noise filtering.
2	2	GND	✅	Pin 2 connects to GND for filtering.

C431 - 2220-0039 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	LAN-LED0	✅	Pin 1 connects to LAN-LED0 net for high-frequency noise filtering.
2	2	GND	✅	Pin 2 connects to GND for filtering.

C426 - 2222-0016 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Pin 1 connects to the center tap net $18N3856 for common mode filtering.
2	2	GND	✅	Pin 2 connects to GND for common mode filtering.

C427 - 2222-0016 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Pin 1 connects to the center tap net $18N3856 for common mode filtering, in parallel with C426 and C428.
2	2	GND	✅	Pin 2 connects to GND for common mode filtering.

C428 - 2222-0014 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$18N3856	✅	Pin 1 connects to the center tap net $18N3856 for common mode filtering, in parallel with C426 and C427.
2	2	GND	✅	Pin 2 connects to GND for common mode filtering.

J11 - RJ45 W XFMR GRN-ORN GRN LEDS ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	MD1+	MDI_P0	✅	MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation.
2	MD1-	MDI_N0	✅	MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation.
3	MD2+	MDI_P1	✅	MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation.
4	MD2-	MDI_N1	✅	MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation.
7	MD3+	MDI_P2	✅	MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation.
8	MD3-	MDI_N2	✅	MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation.
9	MD4+	MDI_P3	✅	MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation.
10	MD4-	MDI_N3	✅	MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation.
5	CT1	$18N3856	✅	Center tap pins correctly connected to common net with AC coupling capacitors to ground for common-mode filtering.
6	CT2	$18N3856	✅	Center tap pins correctly connected to common net with AC coupling capacitors to ground for common-mode filtering.
11	LED2_AC1	LAN-LED0	✅	LED2 pins configured as bi-color LED with pin 11 driven directly by U42 LED0 and pin 12 driven through R844 by U42 LED2. Pin 11 lacks a series current-limiting resistor, which is inconsistent with other LED connections but may be intentional depending on controller configuration or connector design.
12	LED2_AD1	1G-LED-N	✅	LED2 pins configured as bi-color LED with pin 11 driven directly by U42 LED0 and pin 12 driven through R844 by U42 LED2. Pin 11 lacks a series current-limiting resistor, which is inconsistent with other LED connections but may be intentional depending on controller configuration or connector design.
13	LED1_C	LINK-LED-N	✅	LED1 pins correctly configured with pin 14 as anode connected to +3VSB_LAN and pin 13 as cathode driven through R843 by U42 LED1 output.
14	LED1_A	+3VSB_LAN	✅	LED1 pins correctly configured with pin 14 as anode connected to +3VSB_LAN and pin 13 as cathode driven through R843 by U42 LED1 output.
15	SHLD1	GND_EARTH	✅	Shield pins correctly connected to GND_EARTH for EMI shielding.
16	SHLD2	GND_EARTH	✅	Shield pins correctly connected to GND_EARTH for EMI shielding.

U10 - NTS0104GU12 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA pin correctly connected to +V1P8A (1.8V supply) with proper decoupling.
2	A1	SOC_GPIO_S5_2	✅	A1 pin correctly connected to SOC_GPIO_S5_2 on the 1.8V side.
3	A2	SOC_GPIO_S5_1	✅	A2 pin correctly connected to SOC_GPIO_S5_1 on the 1.8V side.
4	A3	SOC_GPIO_S5_0	✅	A3 pin correctly connected to SOC_GPIO_S5_0 on the 1.8V side.
5	A4		✅	A4 (pin 5) is not connected while B4 (pin 7) is tied to GND. This is a non-standard configuration for an unused channel that causes minor power consumption but should not affect functionality.
7	B4	GND	✅	A4 (pin 5) is not connected while B4 (pin 7) is tied to GND. This is a non-standard configuration for an unused channel that causes minor power consumption but should not affect functionality.
6	GND	GND	✅	GND pin correctly connected to ground.
8	B3	GPIO_S5_0	✅	B3 pin correctly connected to GPIO_S5_0 on the 3.3V side.
9	B2	GPIO_S5_1	✅	B2 pin correctly connected to GPIO_S5_1 on the 3.3V side.
10	B1	GPIO_S5_2	✅	B1 pin correctly connected to GPIO_S5_2 on the 3.3V side.
11	VCCB	+PS_3VSB	✅	VCCB pin correctly connected to +PS_3VSB (3.3V supply) with proper decoupling.
12	OE	PMC_PLTRST_R_V1P8	✅	OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal.

U17 - NTS0104GU12 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S (1.8V supply) with proper decoupling.
2	A1	I2S_MCLK	✅	A1 pin correctly connected to I2S_MCLK on the 1.8V side.
3	A2	SOC_PWM1	✅	A2 pin correctly connected to SOC_PWM1 on the 1.8V side.
4	A3	SOC_PWM0	✅	A3 pin correctly connected to SOC_PWM0 on the 1.8V side.
5	A4		✅	A4 (pin 5) is not connected while B4 (pin 7) is tied to GND. This is a non-standard configuration for an unused channel that causes minor power consumption but should not affect functionality.
7	B4	GND	✅	A4 (pin 5) is not connected while B4 (pin 7) is tied to GND. This is a non-standard configuration for an unused channel that causes minor power consumption but should not affect functionality.
6	GND	GND	✅	GND pin correctly connected to ground.
8	B3	PWM0	✅	B3 pin correctly connected to PWM0 on the 3.3V side.
9	B2	PWM1	✅	B2 pin correctly connected to PWM1 on the 3.3V side.
10	B1	I2SMCLK_GPIO	✅	B1 pin correctly connected to I2SMCLK_GPIO on the 3.3V side.
11	VCCB	+3VSB	✅	VCCB pin correctly connected to +3VSB (3.3V supply) with proper decoupling.
12	OE	PMC_PLTRST_R_V1P8	✅	OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal.

U16 - NTS0104GU12 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S (1.8V supply) with proper decoupling.
2	A1	I2S_DATIN_R	✅	A1 pin correctly connected to I2S_DATIN_R on the 1.8V side, with series resistor R128 to LPE_I2S_DATIN.
3	A2	I2S_DATOUT_R	✅	A2 pin correctly connected to I2S_DATOUT_R on the 1.8V side, with series resistor R130 to LPE_I2S_DATOUT.
4	A3	I2S_FRM_R	✅	A3 pin correctly connected to I2S_FRM_R on the 1.8V side, with series resistor R129 to LPE_I2S_FRM.
5	A4	I2S_CLK_R	✅	A4 pin correctly connected to I2S_CLK_R on the 1.8V side, with series resistor R127 to LPE_I2S_CLK.
6	GND	GND	✅	GND pin correctly connected to ground.
7	B4	I2SCLK_GPIO	✅	B4 pin correctly connected to I2SCLK_GPIO on the 3.3V side.
8	B3	I2SFRM_GPIO	✅	B3 pin correctly connected to I2SFRM_GPIO on the 3.3V side.
9	B2	I2SDO_GPIO	✅	B2 pin correctly connected to I2SDO_GPIO on the 3.3V side.
10	B1	I2SDI_GPIO	✅	B1 pin correctly connected to I2SDI_GPIO on the 3.3V side.
11	VCCB	+3VSB	✅	VCCB pin correctly connected to +3VSB (3.3V supply) with proper decoupling.
12	OE	PMC_PLTRST_R_V1P8	✅	OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal.

U7 - NTS0102GT ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	B2	UART2_RXD	✅	B2 pin correctly connected to UART2_RXD on the 3.3V side of the level translator.
2	GND	GND	✅	GND pin correctly connected to ground.
3	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S (1.8V supply) with proper decoupling.
4	A2	SIO_UART2_RXD	✅	A2 pin correctly connected to SIO_UART2_RXD on the 1.8V side of the level translator.
5	A1	SIO_UART2_TXD	✅	A1 pin correctly connected to SIO_UART2_TXD on the 1.8V side of the level translator.
6	OE	PMC_PLTRST_R_V1P8	✅	OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal to enable translation when platform is active.
7	VCCB	+3VSB	✅	VCCB pin correctly connected to +3VSB (3.3V supply) with proper decoupling.
8	B1	UART2_TXD	✅	B1 pin correctly connected to UART2_TXD on the 3.3V side of the level translator.

U15 - NTS0104GU12 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S (1.8V supply) with proper decoupling.
2	A1	SIO_UART1_RTSB	✅	A1 pin correctly connected to SIO_UART1_RTSB on the 1.8V side.
3	A2	SIO_UART1_CTSB	✅	A2 pin correctly connected to SIO_UART1_CTSB on the 1.8V side.
4	A3	SIO_UART1_RXD	✅	A3 pin correctly connected to SIO_UART1_RXD on the 1.8V side.
5	A4	SIO_UART1_TXD	✅	A4 pin correctly connected to SIO_UART1_TXD on the 1.8V side.
6	GND	GND	✅	GND pin correctly connected to ground.
7	B4	UART1_TXD	✅	B4 pin correctly connected to UART1_TXD on the 3.3V side.
8	B3	UART1_RXD	✅	B3 pin correctly connected to UART1_RXD on the 3.3V side.
9	B2	UART1_CTSB	✅	B2 pin correctly connected to UART1_CTSB on the 3.3V side.
10	B1	UART1_RTSB	✅	B1 pin correctly connected to UART1_RTSB on the 3.3V side.
11	VCCB	+3VSB	✅	VCCB pin correctly connected to +3VSB (3.3V supply) with proper decoupling.
12	OE	PMC_PLTRST_R_V1P8	✅	OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal.

U18 - NTB0104GU12 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8A	✅	VCCA pin correctly connected to +V1P8A (1.8V supply) with proper decoupling.
2	A1	SOC_SPI_MOSI-R	✅	A1 pin correctly connected to SOC_SPI_MOSI-R on the 1.8V side.
3	A2	SOC_SPI_CLK-R	✅	A2 pin correctly connected to SOC_SPI_CLK-R on the 1.8V side.
4	A3	SOC_SPI_MISO-R	✅	A3 pin correctly connected to SOC_SPI_MISO-R on the 1.8V side.
5	A4	SOC_SPI_CS0B-R	✅	A4 pin correctly connected to SOC_SPI_CS0B-R on the 1.8V side.
6	GND	GND	✅	GND pin correctly connected to ground.
7	B4	SPI_CS0	✅	B4 pin correctly connected to SPI_CS0 which connects to the SPI flash chip select.
8	B3	SPI_MISO	✅	B3 pin correctly connected to SPI_MISO which connects to the SPI flash data output.
9	B2	SPI_CLK	✅	B2 pin correctly connected to SPI_CLK which connects to the SPI flash clock input.
10	B1	SPI_MOSI	✅	B1 pin correctly connected to SPI_MOSI which connects to the SPI flash data input.
11	VCCB	+V_SPI	✅	VCCB pin correctly connected to +V_SPI, which is a selectable voltage supply (1.8V or 3.3V) for the SPI flash, with proper decoupling.
12	OE	DDP_IO3L	✅	OE pin correctly connected to DDP_IO3L with 100K pull-up to +V1P8A, allowing DediProg programmer to control translator enable.

U14 - NTS0104GU12 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VCCA	+V1P8S	✅	VCCA pin correctly connected to +V1P8S (1.8V supply) with proper decoupling.
2	A1	SOC_SIO_SPI_CLK	✅	A1 pin correctly connected to SOC_SIO_SPI_CLK on the 1.8V side.
3	A2	SOC_SIO_SPI_MOSI	✅	A2 pin correctly connected to SOC_SIO_SPI_MOSI on the 1.8V side.
4	A3	SOC_SIO_SPI_MISO	✅	A3 pin correctly connected to SOC_SIO_SPI_MISO on the 1.8V side.
5	A4	SOC_SIO_SPI_CS1	✅	A4 pin correctly connected to SOC_SIO_SPI_CS1 on the 1.8V side.
6	GND	GND	✅	GND pin correctly connected to ground.
7	B4	SIO_SPI_CS1	✅	B4 pin correctly connected to SIO_SPI_CS1 on the 3.3V side.
8	B3	SIO_SPI_MISO	✅	B3 pin correctly connected to SIO_SPI_MISO on the 3.3V side.
9	B2	SIO_SPI_MOSI	✅	B2 pin correctly connected to SIO_SPI_MOSI on the 3.3V side.
10	B1	SIO_SPI_CLK	✅	B1 pin correctly connected to SIO_SPI_CLK on the 3.3V side.
11	VCCB	+3VSB	✅	VCCB pin correctly connected to +3VSB (3.3V supply) with proper decoupling.
12	OE	PMC_PLTRST_R_V1P8	✅	OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal.

U40 - PCA9306DCUT ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	GND	GND	✅	GND pin correctly connected to ground plane.
2	VREF1	+V1P8S	✅	VREF1 pin correctly connected to +V1P8S (1.8V supply) with proper decoupling capacitor C376.
3	SCL1	I2C5_SCL	✅	SCL1 pin correctly connected to I2C5_SCL with 10K pullup resistor R267 to VREF1.
4	SDA1	I2C5_SDA	✅	SDA1 pin correctly connected to I2C5_SDA with 10K pullup resistor R266 to VREF1.
5	SDA2	GPIO_I2C_SDA	✅	SDA2 pin connected to GPIO_I2C_SDA going to external connector JP1. Pullup resistors are likely on the external board.
6	SCL2	GPIO_I2C_SCL	✅	SCL2 pin connected to GPIO_I2C_SCL going to external connector JP1. Pullup resistors are likely on the external board.
7	VREF2	$20N1576	✅	VREF2 pin is correctly connected to EN pin and pulled up to +3VSB through R812 (200K ohm). However, the datasheet-recommended 100pF filter capacitor on VREF2 is missing.
8	EN	$20N1576	✅	EN pin correctly shorted to VREF2 and pulled up to +3VSB through R812 (200K) for always-enabled operation.

R812 - 110-0001951 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$20N1576	✅	Connected to VREF2/EN net ($20N1576) of U40.
2	2	+3VSB	✅	Connected to +3VSB supply rail, providing pullup for VREF2/EN through 200K resistance.

U3 - W25Q64BVSSIG ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	CS#	SPI_CS0	✅	CS# (Chip Select) is correctly connected to SPI_CS0 with a 10K pull-up resistor R163 to +V_SPI, and routed through level translator U18 to the SOC.
2	SO/IO1	SPI_MISO	✅	SO/IO1 (Data Output) is correctly connected to SPI_MISO and routed through level translator U18 to the SOC for SPI read operations.
3	WP#/IO2	SPI_WP	✅	WP#/IO2 (Write Protect) is correctly pulled high with 10K resistor R164 to +V_SPI, disabling hardware write protection. It is not connected through the level translator, which is acceptable for standard SPI mode where software-only write protection is used.
4	GND	GND	✅	GND is correctly connected to the ground net.
5	SI/IO0	SPI_MOSI	✅	SI/IO0 (Data Input) is correctly connected to SPI_MOSI and routed through level translator U18 to the SOC for SPI write operations.
6	SCK	SPI_CLK	✅	SCK (Serial Clock) is correctly connected to SPI_CLK and routed through level translator U18 to the SOC.
7	HOLD#/IO3	SPI_HOLD	✅	HOLD#/IO3 is correctly pulled high with 10K resistor R165 to +V_SPI, disabling the hold function. It is not connected through the level translator, which is acceptable for standard SPI mode where the hold function is not used.
8	VCC	+V_SPI	✅	VCC is correctly connected to +V_SPI, which is derived from +3VSB through 0-ohm resistor R152 and Schottky diode D8. The resulting voltage (approximately 2.9-3.0V after diode drop) is within the datasheet specification of 2.7-3.6V.

R164 - 10K0 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V_SPI	✅	10K pull-up resistor correctly pulls WP# (SPI_WP) high to +V_SPI, disabling hardware write protection for standard SPI operation.
2	2	SPI_WP	✅	10K pull-up resistor correctly pulls WP# (SPI_WP) high to +V_SPI, disabling hardware write protection for standard SPI operation.

R163 - 10K0 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V_SPI	✅	10K pull-up resistor correctly pulls CS# (SPI_CS0) high to +V_SPI, meeting the datasheet requirement for CS# to track VCC at power-up.
2	2	SPI_CS0	✅	10K pull-up resistor correctly pulls CS# (SPI_CS0) high to +V_SPI, meeting the datasheet requirement for CS# to track VCC at power-up.

R165 - 10K0 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V_SPI	✅	10K pull-up resistor correctly pulls HOLD# (SPI_HOLD) high to +V_SPI, disabling the hold function for standard SPI operation.
2	2	SPI_HOLD	✅	10K pull-up resistor correctly pulls HOLD# (SPI_HOLD) high to +V_SPI, disabling the hold function for standard SPI operation.

R152 - 110-0002124 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$20N2079	✅	Connected to intermediate net $20N2079, which connects to D8 pin A2 (anode 2 of OR-ing diode). Part of the voltage selection scheme for SPI flash operating voltage.
2	2	+3VSB	✅	Connected to +3VSB (3.3V standby power supply). Provides the 3.3V source for SPI flash operation when R152 is populated.

R147 - 110-0001859 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A	✅	Connected to +V1P8A (1.8V power rail). Provides the pull-up voltage source for U18 OE pin.
2	2	DDP_IO3L	✅	Connected to net DDP_IO3L, which connects to U18 pin 12 (OE) and J1 pin 8. Pulls up the output enable pin of voltage translator U18 to enable it during normal operation.

D8 - BAT754C ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A1	A1	DDP_VCC	✅	Connected to DDP_VCC from the external programmer connector. Forms one input of an OR-ing diode configuration to power +V_SPI.
A2	A2	$20N2079	✅	Connected to board supply (+3VSB) through jumper R152 for 3.3V operation. Forms the second input of an OR-ing diode configuration to power +V_SPI when the programmer is not connected.
C	C	+V_SPI	✅	Connected to +V_SPI output, which powers the SPI flash and voltage translator. Outputs the higher of the two input voltages minus the diode forward voltage drop.

J1 - HEADER 4x2 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDP_VCC	✅	DDP_VCC provides power input from DediProg programmer to the SPI flash through diode OR circuit with internal supply. This allows the flash to be powered from either the external programmer or the internal +3VSB supply.
2	2	GND	✅	Ground connection for the DediProg programmer interface.
3	3	SPI_CS0	✅	SPI_CS0 provides chip select signal to the SPI flash. Connected to U3 CS# pin and level translator U18 B4 output, with 10K pull-up to +V_SPI.
4	4	SPI_CLK	✅	SPI_CLK provides clock signal to the SPI flash. Connected to U3 SCK pin and level translator U18 B2 output.
5	5	SPI_MISO	✅	SPI_MISO provides data output from the SPI flash. Connected to U3 SO/IO1 pin and level translator U18 B3 output.
6	6	SPI_MOSI	✅	SPI_MOSI provides data input to the SPI flash. Connected to U3 SI/IO0 pin and level translator U18 B1 output.
7	7		✅	No connection on pin 7. This is acceptable as the SPI flash WP# and HOLD# pins are pulled high through resistors and do not require programmer control.
8	8	DDP_IO3L	✅	DDP_IO3L controls the level translator output enable. Connected to U18 OE pin with 100K pull-up to +V1P8A, allowing the DediProg programmer to disable the SOC interface when programming.

JP1 - HEADER 4x2 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Ground pins for the header, providing a solid ground reference for connected devices.
2	2	GND	✅	Ground pins for the header, providing a solid ground reference for connected devices.
3	3	+PS_5VSB	✅	Provides +PS_5VSB (5V standby power) to the header for powering external devices.
4	4	+3VSB	✅	Provides +3VSB (3.3V standby power) to the header for powering external devices.
5	5	SIO_SPI_CS1	✅	SPI chip select signal (CS1) at 3.3V level, translated from SOC_SIO_SPI_CS1 via U14.
6	6	UART1_TXD	✅	UART1 transmit signal at 3.3V level, translated from SIO_UART1_TXD via U15.
7	7	SIO_SPI_MISO	✅	SPI MISO signal at 3.3V level, translated from SOC_SIO_SPI_MISO via U14.
8	8	UART1_RXD	✅	UART1 receive signal at 3.3V level, translated from SIO_UART1_RXD via U15.
9	9	SIO_SPI_MOSI	✅	SPI MOSI signal at 3.3V level, translated from SOC_SIO_SPI_MOSI via U14.
10	10	UART1_CTSB	✅	UART1 clear-to-send signal (active low) at 3.3V level, translated from SIO_UART1_CTSB via U15.
11	11	SIO_SPI_CLK	✅	SPI clock signal at 3.3V level, translated from SOC_SIO_SPI_CLK via U14.
12	12	UART1_RTSB	✅	UART1 request-to-send signal (active low) at 3.3V level, translated from SIO_UART1_RTSB via U15.
13	13	GPIO_I2C_SCL	✅	I2C clock signal at 3.3V level, translated from I2C5_SCL via U40 (PCA9306DCUT I2C level translator).
14	14	I2SCLK_GPIO	✅	I2S clock signal at 3.3V level, translated from I2S_CLK_R via U16.
15	15	GPIO_I2C_SDA	✅	I2C data signal at 3.3V level, translated from I2C5_SDA via U40 (PCA9306DCUT I2C level translator).
16	16	I2SFRM_GPIO	✅	I2S frame signal at 3.3V level, translated from I2S_FRM_R via U16.
17	17	UART2_TXD	✅	UART2 transmit signal at 3.3V level, translated from SIO_UART2_TXD via U7.
18	18	I2SDO_GPIO	✅	I2S data output signal at 3.3V level, translated from I2S_DATOUT_R via U16.
19	19	UART2_RXD	✅	UART2 receive signal at 3.3V level, translated from SIO_UART2_RXD via U7.
20	20	I2SDI_GPIO	✅	I2S data input signal at 3.3V level, translated from I2S_DATIN_R via U16.
21	21	GPIO_S5_0	✅	GPIO S5_0 signal at 3.3V level, translated from SOC_GPIO_S5_0 via U10.
22	22	PWM0	✅	PWM0 signal at 3.3V level, translated from SOC_PWM0 via U17.
23	23	GPIO_S5_1	✅	GPIO S5_1 signal at 3.3V level, translated from SOC_GPIO_S5_1 via U10.
24	24	PWM1	✅	PWM1 signal at 3.3V level, translated from SOC_PWM1 via U17.
25	25	GPIO_S5_2	✅	GPIO S5_2 signal at 3.3V level, translated from SOC_GPIO_S5_2 via U10.
26	26	I2SMCLK_GPIO	✅	I2S master clock signal at 3.3V level, translated from I2S_MCLK via U17.

R129 - 110-0001853 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_FRM_R	✅	0-ohm series resistor connecting I2S frame sync signal from level translator U16 (pin A3) to LPE interface. This provides a series connection point for the I2S_FRM signal at 1.8V.
2	2	LPE_I2S_FRM	✅	0-ohm series resistor connecting I2S frame sync signal from level translator U16 (pin A3) to LPE interface. This provides a series connection point for the I2S_FRM signal at 1.8V.

R128 - 110-0001853 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_DATIN_R	✅	0-ohm series resistor connecting I2S data input signal from level translator U16 (pin A1) to LPE interface. This provides a series connection point for the I2S_DATIN signal at 1.8V.
2	2	LPE_I2S_DATIN	✅	0-ohm series resistor connecting I2S data input signal from level translator U16 (pin A1) to LPE interface. This provides a series connection point for the I2S_DATIN signal at 1.8V.

R130 - 110-0001853 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_DATOUT_R	✅	0-ohm series resistor connecting I2S data output signal from level translator U16 (pin A2) to LPE interface. This provides a series connection point for the I2S_DATOUT signal at 1.8V.
2	2	LPE_I2S_DATOUT	✅	0-ohm series resistor connecting I2S data output signal from level translator U16 (pin A2) to LPE interface. This provides a series connection point for the I2S_DATOUT signal at 1.8V.

R127 - 110-0001853 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	I2S_CLK_R	✅	0-ohm series resistor connecting I2S clock signal from level translator U16 (pin A4) to LPE interface. This provides a series connection point for the I2S_CLK signal at 1.8V.
2	2	LPE_I2S_CLK	✅	0-ohm series resistor connecting I2S clock signal from level translator U16 (pin A4) to LPE interface. This provides a series connection point for the I2S_CLK signal at 1.8V.

Q105 - FDN327N ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	GPIO_LED_CONTROL	❌	Drain is connected to GPIO_LED_CONTROL net along with LED D2 anode and resistor R746, creating a parallel (shunt switch) configuration. The standard series topology should be used instead, with the drain connecting to D2 cathode. Pin D is connected to net GPIO_LED_CONTROL (from schematic) GPIO_LED_CONTROL net connects to R746 pin 2 (470Ω from +VCC), D2 anode, and C149 pin 1 (2.2µF to GND) (from schematic) Pin D is the Drain terminal according to the FDN327N datasheet (from datasheet FDN327N, page 1) The current configuration places D2 and Q105 in parallel between GPIO_LED_CONTROL and GND, creating a shunt switch topology where the MOSFET bypasses the LED (reasoning) In the shunt switch topology, when Q105 is ON (gate high), current flows from +VCC through R746 and Q105 to GND, pulling GPIO_LED_CONTROL low and turning off D2, but wasting approximately VCC/470Ω (7-11mA depending on VCC voltage) of continuous current (reasoning) When Q105 is OFF (gate low), GPIO_LED_CONTROL is pulled high through R746, forward-biasing D2 and turning the LED on, creating inverted control logic (GPIO high = LED off) (reasoning) The standard low-side N-channel MOSFET LED driver topology requires the LED in series with the MOSFET: VCC → R746 → D2 anode → D2 cathode → Q105 drain → Q105 source → GND (reasoning) The series topology provides non-inverted logic (GPIO high = LED on), eliminates power waste when the LED is off, and is the standard approach used in 99% of GPIO-controlled LED circuits (reasoning) While the shunt switch topology is functional, it wastes significant power (7-11mA continuously when LED is off) and has no apparent advantage over the standard series topology for a system status indicator (reasoning) The text note 'SYSTEM POWER LED - GPIO CONTROLLED' confirms this is intended as a GPIO-controlled system status indicator, which would typically use the standard series topology (from schematic) The drain should connect to D2 cathode (not to GPIO_LED_CONTROL with R746 and D2 anode) to implement the standard, efficient series topology (reasoning)
G	GATE	GPIO_D2_LED_CTRL	✅	Gate is connected to GPIO_D2_LED_CTRL control signal with a 10kΩ pulldown resistor (R706) to ensure the MOSFET stays off when not actively driven.
S	SOURCE	GND	✅	Source is correctly connected to GND, providing the return path for the MOSFET in this shunt switch configuration.

D2 - 4560-0045 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GPIO_LED_CONTROL	✅	Anode is correctly connected to current limiting resistor R746 via the GPIO_LED_CONTROL net. However, Q105 drain is also on this net, creating an incorrect parallel configuration instead of the intended series topology.
C	CATHODE	GND	✅	Cathode is connected to GND, which is incorrect for a series LED-MOSFET topology. The cathode should connect to Q105 drain instead to form the proper series path.

J5 - 258-0002513 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Header pin 1 connects to FP_PWRBTN, providing an external connection point for a front panel power button. The signal is pulled up to +PS_5VSB and protected by TVS diode D9.
2	2	GND	✅	Header pin 2 connects to GND, providing the ground reference for an external front panel power button. When a button connected to J5 is pressed, it pulls pin 1 (FP_PWRBTN) to ground.

D9 - D5V0L1B2LP-7B ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
N	N	GND	✅	TVS diode D9 provides bidirectional ESD protection for the FP_PWRBTN signal. Pin P connects to FP_PWRBTN and pin N connects to GND, protecting against ESD events on the external front panel connection.
P	P	FP_PWRBTN	✅	TVS diode D9 provides bidirectional ESD protection for the FP_PWRBTN signal. Pin P connects to FP_PWRBTN and pin N connects to GND, protecting against ESD events on the external front panel connection.

SW1 - 3770-0026 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	FP_PWRBTN	✅	Switch pin 1 connects to FP_PWRBTN signal, which is pulled up to +PS_5VSB through R149 and protected by TVS diode D9. When the switch is pressed, this pin is shorted to pin 2 (GND), creating an active-low power button signal.
2	2	GND	✅	Switch pin 2 connects to GND. When the switch is pressed, it shorts pin 1 to pin 2, pulling FP_PWRBTN low to signal a power button press.
3	GND1	GND_EARTH	✅	Switch pins 3 and 4 (GND1 and GND2) connect to GND_EARTH, providing chassis ground connection for EMI shielding. GND_EARTH is isolated from GND by DNI resistor R145.
4	GND2	GND_EARTH	✅	Switch pins 3 and 4 (GND1 and GND2) connect to GND_EARTH, providing chassis ground connection for EMI shielding. GND_EARTH is isolated from GND by DNI resistor R145.

D1 - 4560-0045 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	+PS_5VSB	✅	Anode is correctly connected to +PS_5VSB (5V standby supply). This LED serves as an adaptor power indicator.
C	CATHODE	PWR_LEDR	✅	Cathode is correctly connected through current limiting resistor R148 (470Ω) to ground. The circuit provides approximately 3-4mA LED current.

U13 - REG_LDO_BUCK_24V ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VIN	PS5VSB_VIN	✅	VIN pin correctly connected to PS5VSB_VIN with appropriate input decoupling capacitors (88.1µF total) and ferrite bead filtering from +PS_5VSB.
2	PGND	GND	✅	PGND pin correctly connected to GND for power ground return.
3	N/C		✅	N/C pin correctly left unconnected per datasheet.
4	PG	+PS_3VSB_PG	✅	PG pin correctly connected as open-drain output with 100kΩ pull-up resistor R119 to PS3_VCC, and connected to power sequencing diode D6.
5	CLK	$22N1411	✅	CLK pin correctly connected to charge pump circuit using diode arrays Q2 and Q9 with capacitors C72 and C283 to generate higher voltage for gate drive.
6	LDO	PS3_LDO	✅	LDO pin correctly connected with 10µF decoupling capacitor C95, exceeding the minimum 4.7µF requirement.
7	VOUT	+PS_3VSB	✅	VOUT pin correctly connected to +PS_3VSB output through inductor L3, with multiple 22µF output capacitors (110µF total) for filtering.
8	SW1	PS3VSB_PHASE	✅	SW pins correctly connected together to switching node PS3VSB_PHASE, which connects to inductor L3 and bootstrap circuit. However, bootstrap circuit includes unusual 4.7Ω series resistor R291 not shown in datasheet typical application.
9	SW2	PS3VSB_PHASE	✅	SW pins correctly connected together to switching node PS3VSB_PHASE, which connects to inductor L3 and bootstrap circuit. However, bootstrap circuit includes unusual 4.7Ω series resistor R291 not shown in datasheet typical application.
15	SW3	PS3VSB_PHASE	✅	SW pins correctly connected together to switching node PS3VSB_PHASE, which connects to inductor L3 and bootstrap circuit. However, bootstrap circuit includes unusual 4.7Ω series resistor R291 not shown in datasheet typical application.
16	SW4	PS3VSB_PHASE	✅	SW pins correctly connected together to switching node PS3VSB_PHASE, which connects to inductor L3 and bootstrap circuit. However, bootstrap circuit includes unusual 4.7Ω series resistor R291 not shown in datasheet typical application.
10	BST	PS3_BST	✅	BST pin connected to bootstrap circuit through 4.7Ω resistor R291, with C306 (0.1µF) as bootstrap capacitor. Series resistor is unusual but may be intentional for current limiting or damping.
11	VCC	PS3_VCC	✅	VCC pin correctly connected with 1µF decoupling capacitor C97 meeting minimum requirement, and 100kΩ pull-up resistor R119 for power-good signal.
12	ENLDO		✅	ENLDO pin correctly left open to enable LDO per datasheet recommendation.
13	EN	PS3_EN	✅	EN pin connected with 499kΩ pull-up resistor R109 to PS5VSB_VIN for enable control. Datasheet-recommended 10nF noise filtering capacitor C85 is marked DNI, which may be acceptable if noise is not an issue.
14	AGND	GND	✅	AGND pin correctly connected to GND for analog ground reference.

C306 - 0.1uF 10% 25V 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3VSB_PHASE	✅	C306 is the 0.1µF bootstrap capacitor connected between switching node PS3VSB_PHASE and intermediate node (through R291 to BST). Capacitor value matches datasheet recommendation, but series resistor R291 is unusual.
2	2	$22N1498	✅	C306 is the 0.1µF bootstrap capacitor connected between switching node PS3VSB_PHASE and intermediate node (through R291 to BST). Capacitor value matches datasheet recommendation, but series resistor R291 is unusual.

L3 - IND_2.2uH_20%_10A_0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3VSB_PHASE	✅	Inductor pin 1 correctly connected to switching node PS3VSB_PHASE from U13 SW pins.
2	2	+PS_3VSB	✅	Inductor pin 2 correctly connected to output +PS_3VSB with appropriate output capacitors.

R291 - 4.7 ohm 1% 1/4W 0603 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	PS3_BST	✅	R291 is a 4.7Ω resistor in series with bootstrap circuit between BST pin and bootstrap capacitor C306. This configuration is unusual and not shown in NB670 datasheet typical application, but may be intentional for current limiting or damping.
2	2	$22N1498	✅	R291 is a 4.7Ω resistor in series with bootstrap circuit between BST pin and bootstrap capacitor C306. This configuration is unusual and not shown in NB670 datasheet typical application, but may be intentional for current limiting or damping.

U35 - PWR_CTRL_EMB_PROC ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	DeepS5_Sel	S5_SEL	✅	DeepS5_Sel configuration pin connected to S5_SEL net with 2.2K pull-up to +PS_5VSB. This appears to configure the Deep S5 mode behavior.
2	VSB	+PS_5VSB	✅	VSB power supply pin correctly connected to +PS_5VSB rail with adequate decoupling capacitors nearby.
3	PS_IN#	PB_RES	✅	PS_IN# power button input connected to PB_RES net through 33 ohm series resistor R308, which connects to front panel power button.
4	SLP_S5#	SLP_S4_L	✅	SLP_S5# pin is connected to SLP_S4_L net. There is a naming mismatch between S5 (pin name) and S4 (net name), which represents different ACPI sleep states. However, this may be intentional if the system design treats S4 and S5 identically or uses a simplified power state model common in embedded systems.
5	SDA	DDR_SMB_DATA	✅	SDA pin correctly connected to DDR_SMB_DATA for I2C/SMBus communication with DDR memory.
6	SCLK	DDR_SMB_CLK	✅	SCLK pin correctly connected to DDR_SMB_CLK for I2C/SMBus clock communication with DDR memory.
7	PS_OUT#	PS_OUT_L	✅	PS_OUT# power state output connected to PS_OUT_L net. The pull-up resistor R289 is marked DNI, which may be acceptable if the receiving circuit has its own pull-up or if the pin has an internal pull-up.
8	SYS5VSB_OFF	5VSB_CTRL	✅	SYS5VSB_OFF output controls 5VSB system power through 5VSB_CTRL net. Connected with appropriate pull-up and drives FET gate for EuP control. Text notes indicate Low=EuP Disable, High=EuP Enable.
9	GND	GND	✅	GND pin correctly connected to system ground.

Q104 - SISA18ADN-T1-GE3 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	+3VSB	✅	Source pins correctly connected to +3VSB output rail. These pins carry the output current when the MOSFET is conducting.
2	S2	+3VSB	✅	Source pins correctly connected to +3VSB output rail. These pins carry the output current when the MOSFET is conducting.
3	S3	+3VSB	✅	Source pins correctly connected to +3VSB output rail. These pins carry the output current when the MOSFET is conducting.
4	G	+3VSB_EN	✅	Gate pin correctly connected to +3VSB_EN control signal with appropriate drive voltage of +10V to turn on the MOSFET.
5	D1	+PS_3VSB	✅	Drain pins correctly connected to +PS_3VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting.
6	D2	+PS_3VSB	✅	Drain pins correctly connected to +PS_3VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting.
7	D3	+PS_3VSB	✅	Drain pins correctly connected to +PS_3VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting.
8	D4	+PS_3VSB	✅	Drain pins correctly connected to +PS_3VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting.

Q103 - SISA18ADN-T1-GE3 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	+5VSB	✅	Source pins correctly connected to +5VSB output rail. These pins carry the output current when the MOSFET is conducting.
2	S2	+5VSB	✅	Source pins correctly connected to +5VSB output rail. These pins carry the output current when the MOSFET is conducting.
3	S3	+5VSB	✅	Source pins correctly connected to +5VSB output rail. These pins carry the output current when the MOSFET is conducting.
4	G	5VSB_LSENB	✅	Gate pin correctly connected to 5VSB_LSENB control signal with appropriate drive voltage of +10V to turn on the MOSFET.
5	D1	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting.
6	D2	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting.
7	D3	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting.
8	D4	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting.

D13 - 4.3V Zener ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
A	ANODE	GND	✅	Anode correctly connected to GND. For a Zener diode used in voltage clamping, the anode should be at the lower potential.
C	CATHODE	$22N2300	✅	Cathode correctly connected to $22N2300, which is the gate control voltage for Q106. The Zener clamps this voltage at 4.3V above GND.

Q106 - BSS84 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	D	DC_GATE_ENB	✅	Drain correctly connected to DC_GATE_ENB to control the gate of U36. When Q106 turns on at overvoltage conditions, it pulls DC_GATE_ENB high to turn off U36.
G	G	$22N2300	✅	Gate correctly connected to $22N2300, which is clamped at 4.3V by Zener diode D13. The gate voltage relative to source determines when Q106 turns on to activate overvoltage protection.
S	S	$22N1502	✅	Source correctly connected to $22N1502, which is the same net as U36 source. This provides the reference voltage for Q106's gate-source voltage calculation.

U36 - MOSFET_30V_15A_8-SOIC ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	S1	$22N1502	✅	Source pins correctly connected to $22N1502, which connects through ferrite beads to DC_IN_1 (5V input). This is the correct configuration for a P-channel high-side switch.
2	S2	$22N1502	✅	Source pins correctly connected to $22N1502, which connects through ferrite beads to DC_IN_1 (5V input). This is the correct configuration for a P-channel high-side switch.
3	S3	$22N1502	✅	Source pins correctly connected to $22N1502, which connects through ferrite beads to DC_IN_1 (5V input). This is the correct configuration for a P-channel high-side switch.
4	G	DC_GATE_ENB	✅	Gate pin correctly connected to DC_GATE_ENB, which is controlled by the overvoltage protection circuit consisting of Q106, D13, R855, C75, and R309.
5	D1	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB output. This is the correct configuration for a P-channel high-side switch, where the drain connects to the load/output.
6	D2	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB output. This is the correct configuration for a P-channel high-side switch, where the drain connects to the load/output.
7	D3	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB output. This is the correct configuration for a P-channel high-side switch, where the drain connects to the load/output.
8	D4	+PS_5VSB	✅	Drain pins correctly connected to +PS_5VSB output. This is the correct configuration for a P-channel high-side switch, where the drain connects to the load/output.

Q13 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+5VSB	✅	Drain is connected to +5VSB input rail. This is correct for a high-side switch configuration.
G	GATE	SYS_EN	✅	Gate is connected to SYS_EN control signal. The control circuit provides +10V when enabled and GND when disabled, giving sufficient VGS for proper operation.
S	SOURCE	+VCC	✅	Source is connected to +VCC output rail. This is correct for a high-side switch, with current flowing from drain to source when enabled.

Q6 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+3VSB	✅	Drain is connected to +3VSB input rail. This is correct for a high-side switch configuration.
G	GATE	SYS_EN	✅	Gate is connected to SYS_EN control signal. The control circuit provides +10V when enabled and GND when disabled, giving sufficient VGS for proper operation.
S	SOURCE	+VCC3	✅	Source is connected to +VCC3 output rail. This is correct for a high-side switch, with current flowing from drain to source when enabled.

Q11 - FET_NCH_60V_300mA_SOT23 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+3VSB_EN	✅	Drain pin correctly connected to +3VSB_EN, which drives the gate of Q104 (P-channel power MOSFET). Drain current is limited to approximately 100µA steady-state through R322 (100K to +10V), well within the 300mA rating.
G	GATE	+3VSB_EN_L	✅	Gate pin correctly connected to +3VSB_EN_L, which is driven by Q4 collector and pulled up through R321 (1K to +PS_5VSB). Gate voltage swings between ~0V (Q4 on) and ~5V (Q4 off), providing adequate drive for the MOSFET.
S	SOURCE	GND	✅	Source pin correctly connected to GND, providing proper reference for N-channel MOSFET operation in low-side switch configuration.

Q4 - XSTR_NPN_40V_200mA_SOT23 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
B	BASE	S5_ENBL	✅	Base pin correctly connected to S5_ENBL signal, which is pulled up to +V1P8A through R133 (10K) and can be pulled low by Q10. Provides adequate base current for switching operation.
C	COLLECTOR	+3VSB_EN_L	✅	Collector pin correctly connected to +3VSB_EN_L, which drives the gate of Q11 through R321 (1K pull-up to +PS_5VSB). Collector current is limited to approximately 5mA, well within the 200mA maximum rating.
E	EMITTER	GND	✅	Emitter pin correctly connected to GND, providing proper reference for NPN transistor operation in common-emitter configuration.

Q10 - FET_NCH_60V_300mA_SOT23 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	S5_ENBL	✅	Drain connected to S5_ENBL, which drives the base of NPN transistor Q4. This pin acts as a low-side switch to control Q4's base voltage.
G	GATE	5VSB_CTRL	✅	Gate connected to 5VSB_CTRL, which is the EuP control signal from U35. This provides direct gate drive control for the MOSFET.
S	SOURCE	GND	✅	Source correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch.

Q14 - FET_NCH_60V_300mA_SOT23 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	5VSB_LSENB	✅	Drain connected to 5VSB_LSENB, which drives the gate of power MOSFET Q103. This pin acts as a low-side switch to control Q103's gate voltage.
G	GATE	5VSB_GATE	✅	Gate connected to 5VSB_GATE, which is driven from 5VSB_CTRL through R323 (10K). This provides adequate gate drive voltage to control the MOSFET.
S	SOURCE	GND	✅	Source correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch.

Q7 - FET_NCH_60V_300mA_SOT23 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	SYS_EN_GATE	✅	Drain connected to SYS_EN_GATE, which drives the gate of Q12. This pin acts as a low-side switch to control Q12's gate voltage.
G	GATE	SLP_S3_L	✅	Gate connected to SLP_S3_L, which is an active-low control signal. This provides gate drive control for the MOSFET.
S	SOURCE	GND	✅	Source correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch.

Q12 - FET_NCH_60V_300mA_SOT23 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	SYS_EN	✅	Drain connected to SYS_EN, which drives the gates of power MOSFETs Q13 and Q6. This pin acts as a low-side switch to control the power MOSFETs.
G	GATE	SYS_EN_GATE	✅	Gate connected to SYS_EN_GATE, which is controlled by Q7 and pulled up through R142. This provides gate drive control for the MOSFET.
S	SOURCE	GND	✅	Source correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch.

Q2 - DIODE_ARRAY_75V_0.3A_SOT23 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	A1	+PS_5VSB	✅	Anode 1 connected to +PS_5VSB (5V standby rail). This diode provides negative clamping for the CLK signal through C72, limiting negative excursions to approximately 4.3V.
2	A2	$22N1417	✅	Anode 2 connected to floating node $22N1417, which is also connected to Q9 pin 1 and filtered to GND through C71. This diode appears to be reverse-biased in normal operation and its specific function is unclear.
3	C	$22N1419	✅	Common cathode connected to $22N1419, which is AC-coupled to the CLK pin of U13 through C72. This is the clamped node for negative voltage excursions.

Q9 - DIODE_ARRAY_75V_0.3A_SOT23 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	A1	$22N1417	✅	Anode 1 connected to floating node $22N1417, which is also connected to Q2 pin 2 and filtered to GND through C71. This diode appears to be reverse-biased in normal operation and its specific function is unclear.
2	A2	+10V	✅	Anode 2 connected to +10V rail. This diode provides a secondary negative clamp at approximately 9.3V, which is higher than the Q2 clamp and may serve as backup protection.
3	C	$22N1467	✅	Common cathode connected to $22N1467, which is AC-coupled to the CLK pin of U13 through C283. This provides a secondary clamped path for negative voltage excursions.

D6 - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB_PG	✅	Pin 1 connects to +PS_3VSB_PG, the power good output from the 3.3VSB regulator U13. The exact diode function cannot be verified without the datasheet.
2	2	+3VSB_EN	✅	Pin 2 connects to +3VSB_EN, which drives the gate of P-channel MOSFET Q104 and is pulled up to +10V through R322. The exact diode function cannot be verified without the datasheet.
3	3	PMC_RSMRST	✅	Pin 3 connects to PMC_RSMRST, likely a reset signal to the platform management controller. The exact diode function cannot be verified without the datasheet.

FB11 - FERRITE_120OHM_3A_0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_5VSB	✅	Pin 1 connects to +PS_5VSB, paralleled with FB1 pin 1 for increased current capacity.
2	2	PS5VSB_VIN	✅	Pin 2 connects to PS5VSB_VIN, paralleled with FB1 pin 2 for increased current capacity.

L13 - FERRITE_120OHM_3A_0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$22N1502	✅	Pin 1 connects to $22N1502, paralleled with L12 pin 1 for increased current capacity.
2	2	DC_IN_1	✅	Pin 2 connects to DC_IN_1, paralleled with L12 pin 2 for increased current capacity.

L12 - FERRITE_120OHM_3A_0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$22N1502	✅	Pin 1 connects to $22N1502, the source pins of P-channel MOSFET U36 and the filtered DC input node.
2	2	DC_IN_1	✅	Pin 2 connects to DC_IN_1, the 5V DC input from power jack J9.

FB1 - FERRITE_120OHM_3A_0603 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_5VSB	✅	Pin 1 connects to +PS_5VSB, the filtered 5V standby rail output from power switching MOSFETs Q103 and U36.
2	2	PS5VSB_VIN	✅	Pin 2 connects to PS5VSB_VIN, the input to the 3.3V buck regulator U13 and associated input capacitors.

J9 - JACK_PWR_2.1MM_RAPC712 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DC_IN_1	✅	Center pin connected to DC_IN_1 net, serving as the positive 5V DC power input. The connection includes appropriate filtering capacitors, ferrite beads, and inrush current limiting, feeding into an overvoltage protection circuit.
2	2	GND	✅	Sleeve/barrel contact correctly connected to the GND net, serving as the ground return for the DC power input.
3	3	GND	✅	Switch contact connected to GND net. The switch functionality is not utilized in this design, which is acceptable when plug detection is not required.

U25 - NCP81109GMNTXG ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VRHOT	VR_HOT_L	✅	VRHOT pin connected to VR_HOT_L net for thermal alert output.
2	SDIO	$23N2429	✅	SDIO pin connected to SVID data interface through 16.9Ω series resistor R80.
3	ALERT	$23N2431	✅	ALERT pin connected to SVID alert interface through 0Ω resistor R62.
4	SCLK	$23N2430	✅	SCLK pin connected to SVID clock interface through 20.0Ω series resistor R81.
5	GND	AGND-VCORE	✅	GND pin connected to AGND-VCORE analog ground net, which connects to main GND through 0Ω resistor R37.
6	VR_RDY	$23N3753	✅	VR_RDY pin connected to power good output VCORE_PG through 0Ω resistor R79.
7	VIN1	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors.
11	VIN2	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors.
12	VIN3	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors.
13	VIN4	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors.
14	VIN5	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors.
15	VIN6	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors.
16	VIN7	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors.
17	VIN8	+5VSB_SW	✅	VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors.
8	BST	$23N3711	✅	BST pin connected to bootstrap circuit with R154 (2.20Ω) and C50 (0.22µF) to SW1 node.
9	GH		✅	GH pin has no net connection shown. Without datasheet, cannot verify if this is correct for an integrated power stage or if this is an error.
10	SW1	$23N3731	✅	SW1 pin connected to bootstrap circuit return path through C50.
18	SW2	VCORE-SW	✅	SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE.
25	SW3	VCORE-SW	✅	SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE.
26	SW4	VCORE-SW	✅	SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE.
27	SW5	VCORE-SW	✅	SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE.
28	SW6	VCORE-SW	✅	SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE.
29	SW7	VCORE-SW	✅	SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE.
19	PGND1	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
20	PGND2	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
21	PGND3	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
22	PGND4	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
23	PGND5	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
24	PGND6	GND	✅	PGND1-PGND6 pins all connected to main GND for power ground return.
30	GL		✅	GL pin has no net connection shown. Without datasheet, cannot verify if this is correct for an integrated power stage or if this is an error.
31	VBOOT	$23N3477	✅	VBOOT pin connected through 88.7kΩ resistor to ground for bootstrap voltage monitoring. Text note indicates VBOOT = 1.1V.
32	GND1	AGND-VCORE	✅	GND1 pin connected to AGND-VCORE analog ground net.
33	VCCP	$23N3625	✅	VCCP pin connected to charge pump supply through 1.00Ω resistor from +5VSB with 4.7µF decoupling.
34	TSENSE	$23N3665	✅	TSENSE pin connected to temperature sensing network with 100kΩ thermistor TH2 and 14.0kΩ resistor forming voltage divider.
35	IMAX	$23N3681	✅	IMAX pin connected through 44.2kΩ resistor to ground to set maximum current limit. Text note indicates IMAX = 14A.
36	IOUT	$23N3683	✅	IOUT pin connected through 16.5kΩ resistor and 470pF capacitor to ground for output current reporting.
37	ILIM	VCORE-ILIM	✅	ILIM pin connected to current sense compensation network through 15.0kΩ resistor.
38	CSCOMP	VCORE-CSCOMP	✅	CSCOMP pin connected to current sense compensation network with capacitors, resistors, and thermistor TH1 for temperature compensation.
39	CSSUM	VCORE-CSSUM	✅	CSSUM pin connected to current sense sum network with DCR sensing through shorts SP3 and SP4 measuring inductor voltage drop.
40	CSREF	VCORE-CSREF	✅	CSREF pin connected to current sense reference through 10.0Ω resistor with DCR sensing from output through short SP4.
41	FREQ	$23N2930	✅	FREQ pin connected through 18.7kΩ resistor to ground to set switching frequency. Text note indicates FSW = 650kHz.
42	COMP	VCORE-COMP	✅	COMP pin connected to voltage loop compensation network with capacitors C35 and C37.
43	FB	VCORE-FB	✅	FB pin connected to feedback network with resistor divider and compensation components.
44	DIFFOUT	VCORE-DIFFOUT	✅	DIFFOUT pin connected to differential amplifier output network with resistors R89 and R90.
45	VSN	VR-VCORE-VSN	✅	VSN pin connected to negative remote sense input through 10.0Ω resistor for differential voltage sensing at the load.
46	VSP	VR-VCORE-VSP	✅	VSP pin connected to positive remote sense input through 100Ω resistor for differential voltage sensing at the load.
47	VCC	$23N3860	✅	VCC pin connected to internal supply through 2.20Ω resistor from +5VSB with 1.0µF decoupling.
48	EN	$23N5607	✅	EN pin connected to enable control with pull-up through 0Ω resistor from +VCC and 10kΩ pull-down.
49	GND_PAD	AGND-VCORE	✅	GND_PAD connected to AGND-VCORE analog ground net for thermal and electrical grounding.
50	VIN_PAD	+5VSB_SW	✅	VIN_PAD connected to +5VSB_SW input supply, paralleling the VIN1-VIN8 pins.
51	SW_PAD	VCORE-SW	✅	SW_PAD connected to VCORE-SW switch node output, paralleling the SW2-SW7 pins.

L8 - 3120-0183 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 connects to the +5VSB input supply rail. This is the correct connection for the input side of the input filter inductor.
2	2	+5VSB_SW	✅	Pin 2 connects to the +5VSB_SW filtered supply rail that powers the U25 controller VIN pins. This is the correct connection for the output side of the input filter inductor.

L18 - 3120-0266 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-SW	✅	Pin 1 connects to the VCORE-SW switching node from the U25 multiphase buck controller. This is the correct connection for the input side of the output filter inductor.
2	2	+VCORE	✅	Pin 2 connects to the +VCORE output rail with multiple output capacitors and load connections. This is the correct connection for the output side of the filter inductor.

TH2 - 3880-0004 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3662	✅	Connected to net $23N3662, which receives the TSENSE signal from U25 through R78. This thermistor provides temperature sensing for the voltage regulator.
2	2	GND	✅	Connected to GND, providing the ground reference for the temperature sensing voltage divider.

R78 - 1121-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3665	✅	Connected to net $23N3665, which connects to U25 pin 34 (TSENSE). This 0-ohm jumper allows the TSENSE signal to reach the thermistor network.
2	2	$23N3662	✅	Connected to net $23N3662, which is the junction of TH2 and R131. This completes the connection from TSENSE to the temperature sensing network.

R131 - 1120-0055 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3662	✅	Connected to net $23N3662, forming a parallel combination with TH2 for temperature sensing. The 14K value sets the temperature sensing characteristics.
2	2	GND	✅	Connected to GND, completing the temperature sensing voltage divider to ground.

TH1 - 3880-0004 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	Connected to VCORE-CSCOMP net, which is the current sense compensation pin of U25. This thermistor provides temperature compensation for the current sensing loop.
2	2	$23N3115	✅	Connected to net $23N3115, which is the junction between R96 and R106 in the current sensing compensation network.

D4 - BAT54A-S ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	Cathode 1 of dual Schottky diode, connected to VCORE_PG net. This pin receives the VCORE power good signal and forms part of a wired-AND power good monitoring circuit.
2	2	VGFX_PG	✅	Cathode 2 of dual Schottky diode, connected to VGFX_PG net. This pin receives the graphics voltage regulator power good signal and forms the other input of the wired-AND power good monitoring circuit.
3	3	VCORE_GFX_PG	✅	Common anode of dual Schottky diode, connected to VCORE_GFX_PG net. This pin outputs the combined power good signal that is high only when both VCORE_PG and VGFX_PG are high.

R94 - 110-0001923 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_GFX_PG	✅	Connected to VCORE_GFX_PG combined power good signal. Functions as part of pull-up network.
2	2	+VCC3	✅	Connected to +VCC3 supply rail. Provides pull-up voltage for the combined power good signal.

R79 - 1121-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE_PG	✅	Connected to VCORE_PG power good signal. Functions as 0-ohm jumper to route VR_RDY signal.
2	2	$23N3753	✅	Connected to U25 pin 6 (VR_RDY) through internal net $23N3753. Routes voltage regulator ready signal to VCORE_PG.

R167 - 1120-0052 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Connected to +VCC3 supply rail. Provides pull-up voltage for VCORE_PG signal.
2	2	VCORE_PG	✅	Connected to VCORE_PG power good signal. Provides pull-up for the VR_RDY output from U25.

R62 - 1121-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT-R	✅	Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U25 ALERT pin.
2	2	$23N2431	✅	Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U25 ALERT pin.

R80 - 1120-0329 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_DATA-R	✅	Series resistor on SVID data line between external SVID_DATA-R signal and U25 SDIO pin. Provides signal integrity and protection for the serial data line.
2	2	$23N2429	✅	Series resistor on SVID data line between external SVID_DATA-R signal and U25 SDIO pin. Provides signal integrity and protection for the serial data line.

R87 - 1120-0330 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor that would connect +V1P0S to SVID_CLK-R. Not installed, indicating pull-ups are provided elsewhere in the system.
2	2	SVID_CLK-R	✅	DNI pull-up resistor that would connect +V1P0S to SVID_CLK-R. Not installed, indicating pull-ups are provided elsewhere in the system.

R86 - 1120-0330 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor that would connect +V1P0S to SVID_ALERT-R. Not installed, indicating pull-ups are provided elsewhere in the system.
2	2	SVID_ALERT-R	✅	DNI pull-up resistor that would connect +V1P0S to SVID_ALERT-R. Not installed, indicating pull-ups are provided elsewhere in the system.

R85 - 1120-0330 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	DNI pull-up resistor that would connect +V1P0S to SVID_DATA-R. Not installed, indicating pull-ups are provided elsewhere in the system.
2	2	SVID_DATA-R	✅	DNI pull-up resistor that would connect +V1P0S to SVID_DATA-R. Not installed, indicating pull-ups are provided elsewhere in the system.

R81 - 1120-0099 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_CLK-R	✅	Series resistor on SVID clock line between external SVID_CLK-R signal and U25 SCLK pin. Provides signal integrity and protection for the serial clock line.
2	2	$23N2430	✅	Series resistor on SVID clock line between external SVID_CLK-R signal and U25 SCLK pin. Provides signal integrity and protection for the serial clock line.

C87 - 123-0005035 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VCORE	✅	Positive terminal of the 330µF tantalum capacitor connected to the +VCORE output rail. This provides bulk energy storage and filtering for the VCORE regulator output.
2	N	GND	✅	Negative terminal of the tantalum capacitor connected to ground reference. This completes the output filtering capacitor connection with correct polarity.

C35 - 2220-0002 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-COMP	✅	Connected to VCORE-COMP net which connects to the COMP pin (pin 42) of U25. This is the error amplifier output.
2	2	VCORE-FB	✅	Connected to VCORE-FB net. Forms direct high-frequency path between COMP and FB for stability.

C37 - 2221-0002 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-COMP	✅	Connected to VCORE-COMP net which connects to the COMP pin (pin 42) of U25.
2	2	$23N2824	✅	Connected to intermediate node $23N2824 which connects to R88. Forms RC network with R88 to create compensation zero.

R90 - 1121-0025 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2818	✅	Connected to intermediate node $23N2818 which connects to C36. Forms an RC network for additional phase boost.
2	2	VCORE-DIFFOUT	✅	Connected to VCORE-DIFFOUT net which connects to the DIFFOUT pin (pin 44) of U25.

R88 - 1120-0032 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2824	✅	Connected to intermediate node $23N2824 which connects to C37. Forms part of the Type III compensation network creating a zero with C37.
2	2	VCORE-FB	✅	Connected to VCORE-FB net which connects to the FB pin (pin 43) of U25. This is the feedback node of the compensation network.

R89 - 1120-0010 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-FB	✅	Connected to VCORE-FB net, the feedback node. Provides DC feedback path from FB to DIFFOUT.
2	2	VCORE-DIFFOUT	✅	Connected to VCORE-DIFFOUT net which connects to the DIFFOUT pin (pin 44) of U25. Completes the feedback path.

C36 - 2220-0014 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-FB	✅	Connected to VCORE-FB net which connects to the FB pin (pin 43) of U25.
2	2	$23N2818	✅	Connected to intermediate node $23N2818 which connects to R90. Forms RC network with R90 for additional phase boost.

R146 - 1120-0338 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3683	✅	Connected to U25 pin 36 (IOUT) to set the output current monitoring scale.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE to provide the pulldown reference for IOUT.

R106 - 1120-0037 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3115	✅	Connected to intermediate node $23N3115, continuing the divider from R96.
2	2	VCORE-CSSUM	✅	Connected to VCORE-CSSUM to complete the resistor divider network.

R96 - 1120-0282 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	Connected to VCORE-CSCOMP as part of a resistor divider network with R106.
2	2	$23N3115	✅	Connected to intermediate node $23N3115, which continues to R106 and has TH1 in parallel for temperature compensation.

C45 - 2220-0035 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSREF	✅	Connected to VCORE-CSREF to filter the current sense reference voltage.
2	2	GND	✅	Connected to GND to complete the filtering capacitor.

R95 - 1120-0029 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-ILIM	✅	Connected to VCORE-ILIM (U25 pin 37) to set the current limit threshold.
2	2	VCORE-CSCOMP	✅	Connected to VCORE-CSCOMP to complete the current limit setting network.

R107 - 1130-0002 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSSUM	✅	Connected to VCORE-CSSUM to provide the current sense signal from the switching node.
2	2	$23N3209	✅	Connected to VCORE-SW through PCB bridge short SP3, implementing DCR current sensing from the switching node.

R108 - 1120-0022 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSREF	✅	Connected to VCORE-CSREF (U25 pin 40) to provide a reference voltage for current sensing.
2	2	$23N3208	✅	Connected to +VCORE through PCB bridge short SP4, providing a reference voltage proportional to the output for adaptive voltage positioning.

R105 - 1120-0115 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3681	✅	Connected to U25 pin 35 (IMAX) to set the maximum current limit. A nearby text note indicates IMAX should be 14A.
2	2	AGND-VCORE	✅	Connected to AGND-VCORE to provide the pulldown reference for IMAX.

C40 - 2221-0002 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	Connected to VCORE-CSCOMP, in parallel with C39 to provide additional compensation capacitance.
2	2	VCORE-CSSUM	✅	Connected to VCORE-CSSUM, in parallel with C39 to complete the compensation network.

C39 - 2220-0025 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCORE-CSCOMP	✅	Connected to VCORE-CSCOMP for current loop compensation. This capacitor, along with C40, provides compensation between CSCOMP and CSSUM pins of the PWM controller.
2	2	VCORE-CSSUM	✅	Connected to VCORE-CSSUM to complete the compensation network between CSCOMP and CSSUM.

R849 - 1121-0001 ❌

DRCY flagged 1 potential issues in this component.

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	❌	R849 is a 0 ohm jumper connecting +VCC to the EN pin of U25. With R851 (10K to GND) also populated, this creates a continuous current path from +VCC to GND through R851, drawing approximately 0.33-0.5mA depending on +VCC voltage. This is wasteful and unusual; typically only one of R849 or R851 would be populated. Pin 1 of R849 is connected to net +VCC (from schematic) Pin 2 of R849 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic) R849 is a 0 ohm jumper (part number 1121-0001) (from schematic) R851 is a 10K resistor connecting the same net $23N5607 to GND (from schematic) With R849 as 0 ohm and R851 as 10K both populated, a current path exists from +VCC through R849 to GND through R851 (reasoning) The current through this path would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning) This continuous current draw is wasteful and serves no functional purpose (reasoning) Typical enable circuit design would have either a pull-up (R849) or pull-down (R851) populated, not both (reasoning) The 0 ohm jumper R849 would pull the EN pin high to +VCC, enabling the regulator (reasoning) If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning) If the intent is to disable the regulator by default or allow external control, R849 should be DNI and R851 should be populated (reasoning) One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)
2	2	$23N5607	❌	R849 is a 0 ohm jumper connecting +VCC to the EN pin of U25. With R851 (10K to GND) also populated, this creates a continuous current path from +VCC to GND through R851, drawing approximately 0.33-0.5mA depending on +VCC voltage. This is wasteful and unusual; typically only one of R849 or R851 would be populated. Pin 1 of R849 is connected to net +VCC (from schematic) Pin 2 of R849 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic) R849 is a 0 ohm jumper (part number 1121-0001) (from schematic) R851 is a 10K resistor connecting the same net $23N5607 to GND (from schematic) With R849 as 0 ohm and R851 as 10K both populated, a current path exists from +VCC through R849 to GND through R851 (reasoning) The current through this path would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning) This continuous current draw is wasteful and serves no functional purpose (reasoning) Typical enable circuit design would have either a pull-up (R849) or pull-down (R851) populated, not both (reasoning) The 0 ohm jumper R849 would pull the EN pin high to +VCC, enabling the regulator (reasoning) If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning) If the intent is to disable the regulator by default or allow external control, R849 should be DNI and R851 should be populated (reasoning) One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)

R851 - 1120-0011 ❌

DRCY flagged 1 potential issues in this component.

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N5607	❌	R851 is a 10K pull-down resistor connecting the EN pin of U25 to GND. With R849 (0 ohm to +VCC) also populated, this creates a continuous current path from +VCC to GND, drawing approximately 0.33-0.5mA. This is wasteful and unusual; typically only one of R849 or R851 would be populated. Pin 1 of R851 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic) Pin 2 of R851 is connected to net GND (from schematic) R851 is a 10K resistor (part number 1120-0011) (from schematic) R849 is a 0 ohm jumper connecting +VCC to the same net $23N5607 (from schematic) With both R849 (0 ohm) and R851 (10K) populated, a current path exists from +VCC to GND (reasoning) The current through R851 would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning) This continuous current draw is wasteful and serves no functional purpose (reasoning) A pull-down resistor on an enable pin is typically used when the regulator should be disabled by default or when external control is desired (reasoning) With R849 (0 ohm) populated, the EN pin is strongly pulled high to +VCC, making R851 redundant except for creating unwanted current draw (reasoning) If the intent is to disable the regulator by default, R851 should be populated and R849 should be DNI (reasoning) If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning) One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)
2	2	GND	❌	R851 is a 10K pull-down resistor connecting the EN pin of U25 to GND. With R849 (0 ohm to +VCC) also populated, this creates a continuous current path from +VCC to GND, drawing approximately 0.33-0.5mA. This is wasteful and unusual; typically only one of R849 or R851 would be populated. Pin 1 of R851 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic) Pin 2 of R851 is connected to net GND (from schematic) R851 is a 10K resistor (part number 1120-0011) (from schematic) R849 is a 0 ohm jumper connecting +VCC to the same net $23N5607 (from schematic) With both R849 (0 ohm) and R851 (10K) populated, a current path exists from +VCC to GND (reasoning) The current through R851 would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning) This continuous current draw is wasteful and serves no functional purpose (reasoning) A pull-down resistor on an enable pin is typically used when the regulator should be disabled by default or when external control is desired (reasoning) With R849 (0 ohm) populated, the EN pin is strongly pulled high to +VCC, making R851 redundant except for creating unwanted current draw (reasoning) If the intent is to disable the regulator by default, R851 should be populated and R849 should be DNI (reasoning) If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning) One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)

R154 - 1130-0234 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3711	✅	Connected to BST pin of U25 (NCP81109GMNTXG controller). This is the bootstrap pin connection for the high-side gate driver.
2	2	$23N3733	✅	Connected to bootstrap capacitor C50. This forms the series R-C bootstrap network between BST and SW1 pins.

C50 - 2222-0008 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N3733	✅	Connected to R154 pin 2, forming the bootstrap capacitor connection between the damping resistor and the switch node.
2	2	$23N3731	✅	Connected to SW1 pin of U25. This completes the bootstrap circuit by connecting the capacitor to the switch node.

R93 - 1120-0351 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$23N2930	✅	Pin 1 connects to the FREQ pin (pin 41) of U25 (NCP81109GMNTXG) to set the switching frequency. A nearby text note indicates the target frequency is 650 kHz.
2	2	AGND-VCORE	✅	Pin 2 connects to AGND-VCORE, the analog ground net for the VCORE regulator section. This is the correct reference for the frequency-setting resistor.

U26 - NCP81109GMNTXG ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VRHOT	VR_HOT_L	✅	VRHOT pin is connected to VR_HOT_L net, which is a thermal alert output signal.
2	SDIO	$24N3490	✅	SDIO pin is connected to SVID data line through R193 (16.9Ω) series resistor with pull-up to +V1P0S through R195 (69.8Ω).
3	ALERT	$24N3492	✅	ALERT pin is connected to SVID alert line through R67 (0Ω) jumper with pull-up to +V1P0S through R196 (69.8Ω, DNI).
4	SCLK	$24N3491	✅	SCLK pin is connected to SVID clock line through R194 (20.0Ω) series resistor with pull-up to +V1P0S through R197 (69.8Ω).
5	GND	AGND-VGFX	✅	GND pin is connected to AGND-VGFX analog ground net, which connects to main GND through R66 (0Ω) jumper.
6	VR_RDY	$24N3598	✅	VR_RDY pin is connected to power good output VGFX_PG through R184 (0Ω) jumper, with pull-up R230 (1.91kΩ) to +VCC3 and decoupling C60 (0.1µF).
7	VIN1	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
11	VIN2	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
12	VIN3	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
13	VIN4	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
14	VIN5	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
15	VIN6	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
16	VIN7	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
17	VIN8	+5VSB_SW	✅	VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59).
8	BST	$24N3593	✅	BST pin is connected to bootstrap circuit with R228 (2.20Ω) and C186 (0.22µF) to SW1 for high-side gate driver supply.
9	GH		✅	GH pin has no net connection shown in the schematic, which is expected for an integrated solution where MOSFETs are internal.
10	SW1	$24N3595	✅	SW1 is connected to the bootstrap capacitor return path ($24N3595) but is isolated from the main switch node VGFX-SW. This configuration appears intentional as phase 1 gate drives (GH pin 9, GL pin 30) are not connected, suggesting phase 1 is not used as an active switching phase.
18	SW2	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
25	SW3	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
26	SW4	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
27	SW5	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
28	SW6	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
29	SW7	VGFX-SW	✅	SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output.
19	PGND1	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
20	PGND2	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
21	PGND3	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
22	PGND4	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
23	PGND5	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
24	PGND6	GND	✅	PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs.
30	GL		✅	GL pin has no net connection shown in the schematic, which is expected for an integrated solution where MOSFETs are internal.
31	VBOOT	$24N3564	✅	VBOOT pin is connected to bootstrap voltage sense with R170 (100kΩ) pull-down to AGND-VGFX.
32	GND1	AGND-VGFX	✅	GND1 pin is connected to AGND-VGFX analog ground net.
33	VCCP	$24N3578	✅	VCCP pin is connected to internal LDO/charge pump supply with R846 (1Ω) from +5VSB and C185 (4.7µF) decoupling.
34	TSENSE	$24N3584	✅	TSENSE pin is connected to temperature sense network with TH4 (100kΩ@25C thermistor) and R226 (14.0kΩ) forming a divider to GND, with C168 (0.1µF) filtering.
35	IMAX	$24N3588	✅	IMAX pin is connected to R207 (44.2kΩ) to AGND-VGFX, setting the maximum current limit. A text note indicates IMAX = 14A.
36	IOUT	$24N3589	✅	IOUT pin is connected to output current reporting network with R227 (16.5kΩ) and C184 (470pF) to AGND-VGFX.
37	ILIM	VGFX-ILIM	✅	ILIM pin is connected to current limit threshold network with R204 (15.0kΩ) to VGFX-CSCOMP.
38	CSCOMP	VGFX-CSCOMP	✅	CSCOMP pin is connected to current sense compensation network with R204, R205, TH3, C113, and C166 for current loop stability and thermal compensation.
39	CSSUM	VGFX-CSSUM	✅	CSSUM pin is connected to current sense sum network with R224, R223, C113, and C166 for multiphase current sensing.
40	CSREF	VGFX-CSREF	✅	CSREF pin is connected to current sense reference with R225 (10.0Ω) to output voltage through SP1, and C167 (1000pF) to GND.
41	FREQ	$24N3542	✅	FREQ pin is connected to R203 (18.7kΩ) to AGND-VGFX, setting the switching frequency. A text note indicates FSW = 650kHz.
42	COMP	VGFX-COMP	✅	COMP pin is connected to voltage loop compensation network with C62 (47pF) to FB and C64 (2200pF) to feedback divider.
43	FB	VGFX-FB	✅	FB pin is connected to feedback network with R198 (3.01kΩ) divider, R199 (1.00kΩ) to DIFFOUT, and compensation capacitors C62 and C63.
44	DIFFOUT	VGFX-DIFFOUT	✅	DIFFOUT pin is connected to differential amplifier output network with R199 (1.00kΩ) to FB and R200 (47Ω) to compensation.
45	VSN	VR-VGFX-VSN	✅	VSN pin is connected to negative remote sense input with R169 (10.0Ω) from ground reference point.
46	VSP	VR-VGFX-VSP	✅	VSP pin is connected to positive remote sense input with R202 (100Ω) from +VGFX and R68 (0Ω) from VCCGT_SENSE.
47	VCC	$24N3610	✅	VCC pin is connected to supply input with R229 (2.20Ω) from +5VSB and C53 (1.0µF) decoupling to AGND-VGFX.
48	EN	$24N6011	✅	EN pin is connected to enable input with R850 (0Ω) pull-up to +VCC, R852 (10.0kΩ) pull-down to GND, and C434 (0.1µF) decoupling.
49	GND_PAD	AGND-VGFX	✅	GND_PAD is connected to AGND-VGFX analog ground net for thermal and electrical grounding.
50	VIN_PAD	+5VSB_SW	✅	VIN_PAD is connected to +5VSB_SW input supply for additional current handling capability.
51	SW_PAD	VGFX-SW	✅	SW_PAD is connected to VGFX-SW switch node for additional current handling capability.

SP1 - 999-0000005 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	Pin 1 connects to +VGFX, the regulated output voltage of the buck converter. This connection is part of the DCR (DC Resistance) current sensing network.
2	2	$24N3559	✅	Pin 2 connects to $24N3559, which connects through R225 (10Ω) to VGFX-CSREF (pin 40 of U26). This forms the reference path for DCR current sensing.

SP2 - 999-0000005 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Pin 1 connects to VGFX-SW, the switching node of the buck converter. This connection is part of the DCR current sensing network.
2	2	$24N3558	✅	Pin 2 connects to $24N3558, which connects through R224 (100kΩ) to VGFX-CSSUM (pin 39 of U26). This forms the sum path for DCR current sensing.

L4 - 3120-0266 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Connected to VGFX-SW switching node. This is the correct connection for a buck converter output inductor.
2	2	+VGFX	✅	Connected to +VGFX output rail. This is the correct connection for a buck converter output inductor. However, there is a potential concern regarding current rating.

R198 - 1120-0032 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3524	✅	Connected to internal compensation network node $24N3524, which connects to C64 pin 2. Forms part of the voltage loop compensation network.
2	2	VGFX-FB	✅	Connected to VGFX-FB net, which is the feedback pin (pin 43) of voltage regulator controller U26.

R199 - 1120-0010 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-FB	✅	Connected to VGFX-FB net, the feedback pin of U26. Forms part of the differential amplifier network.
2	2	VGFX-DIFFOUT	✅	Connected to VGFX-DIFFOUT net, the differential output pin (pin 44) of U26.

R200 - 1121-0025 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3522	✅	Connected to internal compensation network node $24N3522, which connects to C63 pin 2.
2	2	VGFX-DIFFOUT	✅	Connected to VGFX-DIFFOUT net, the differential output pin of U26.

C62 - 2220-0002 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-COMP	✅	Connected to VGFX-COMP net, the compensation pin (pin 42) of U26.
2	2	VGFX-FB	✅	Connected to VGFX-FB net, the feedback pin of U26. Provides direct AC coupling between COMP and FB.

C63 - 2220-0014 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-FB	✅	Connected to VGFX-FB net, the feedback pin of U26.
2	2	$24N3522	✅	Connected to internal compensation network node $24N3522, which connects to R200 pin 1.

C64 - 2221-0002 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-COMP	✅	Connected to VGFX-COMP net, the compensation pin of U26.
2	2	$24N3524	✅	Connected to internal compensation network node $24N3524, which connects to R198 pin 1.

R224 - 1130-0002 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSSUM	✅	Connected to VGFX-CSSUM pin of the controller U26 for current sensing.
2	2	$24N3558	✅	Connected through net $24N3558 and short SP2 to the switching node VGFX-SW for DCR current sensing.

C167 - 2220-0035 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSREF	✅	Connected to VGFX-CSREF for filtering the current sense reference.
2	2	GND	✅	Connected to GND to provide AC filtering for the CSREF pin.

R205 - 1120-0282 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP for current sense compensation.
2	2	$24N3557	✅	Connected to intermediate node $24N3557, forming a parallel path with thermistor TH3 for temperature compensation.

R223 - 1120-0037 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3557	✅	Connected to the intermediate node $24N3557 which links to the CSCOMP compensation network.
2	2	VGFX-CSSUM	✅	Connected to VGFX-CSSUM to provide feedback from the current sense sum to the compensation network.

TH3 - 3880-0004 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP for current sensing temperature compensation. This thermistor provides temperature-dependent resistance to compensate the current sensing circuit of the voltage regulator.
2	2	$24N3557	✅	Connected to internal node $24N3557 which forms part of the resistor divider network with R205 and R223. This creates a temperature-dependent voltage for current sensing compensation.

R225 - 1120-0022 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSREF	✅	Connected to VGFX-CSREF pin of the controller for current sense reference.
2	2	$24N3559	✅	Connected through net $24N3559 and short SP1 to the output voltage +VGFX, providing a reference for DCR current sensing.

R204 - 1120-0029 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-ILIM	✅	Connected to VGFX-ILIM pin of the controller for current limit setting.
2	2	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP to link the current limit setting to the compensation network.

C166 - 2221-0002 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP for current loop compensation.
2	2	VGFX-CSSUM	✅	Connected to VGFX-CSSUM, forming part of the current loop compensation network in parallel with C113.

C113 - 2220-0025 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-CSCOMP	✅	Connected to VGFX-CSCOMP for current loop compensation.
2	2	VGFX-CSSUM	✅	Connected to VGFX-CSSUM, forming part of the current loop compensation network in parallel with C166.

TH4 - 3880-0004 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3583	✅	Connected to internal node $24N3583 which forms a voltage divider with R226 (14K) to ground. This provides temperature-dependent voltage to the TSENSE pin of U26 through R178.
2	2	GND	✅	Connected to GND to complete the voltage divider circuit with R226. This is the standard configuration for a thermistor-based temperature sensing circuit.

R226 - 1120-0055 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3583	✅	Connected to $24N3583 which connects to TH4 pin 1, forming the upper part of the voltage divider. This creates a temperature-dependent voltage with the thermistor.
2	2	GND	✅	Connected to GND to complete the voltage divider with TH4. This is the standard lower resistor in a thermistor voltage divider configuration.

C168 - 2222-0016 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3584	✅	Connected to $24N3584 which connects to U26 pin 34 (TSENSE). This capacitor provides filtering for the temperature sensing input to reduce noise.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX (analog ground) to provide a clean ground reference for filtering. This ensures the filter capacitor has a low-noise ground connection.

R178 - 1121-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3584	✅	Connected to $24N3584 which connects to U26 pin 34 (TSENSE) and C168 for filtering. This side of the jumper connects the temperature sensing network to the controller.
2	2	$24N3583	✅	Connected to $24N3583 which connects to the TH4/R226 voltage divider. This side of the jumper connects to the thermistor temperature sensing network.

R67 - 1121-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_ALERT-R	✅	Connected to SVID_ALERT-R net. R196 (69.8Ω pull-up to +V1P0S) is DNI, so no pull-up is present on this board.
2	2	$24N3492	✅	Connected to U26 pin 3 (ALERT) through net $24N3492. This 0Ω jumper provides a direct connection to the ALERT pin.

R195 - 1120-0330 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Connected to +V1P0S supply. This provides the pull-up voltage for the SVID data line.
2	2	SVID_DATA-R	✅	Connected to SVID_DATA-R net, providing pull-up for the SVID data line. The 69.8Ω value provides a strong pull-up for fast signal transitions.

R196 - 1120-0330 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	This component is marked DNI (Do Not Install). If installed, it would provide a 69.8Ω pull-up from +V1P0S to SVID_ALERT-R.
2	2	SVID_ALERT-R	✅	This component is marked DNI (Do Not Install). If installed, it would provide a 69.8Ω pull-up from +V1P0S to SVID_ALERT-R.

C432 - 2222-0014 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Connected to +V1P0S supply. This capacitor provides decoupling for the 1.0V supply used for SVID pull-ups.
2	2	GND	✅	Connected to GND. This completes the decoupling capacitor for the +V1P0S supply.

R197 - 1120-0330 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0S	✅	Connected to +V1P0S supply. This provides the pull-up voltage for the SVID clock line.
2	2	SVID_CLK-R	✅	Connected to SVID_CLK-R net, providing pull-up for the SVID clock line. The 69.8Ω value provides a strong pull-up for fast signal transitions.

R194 - 1120-0099 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_CLK-R	✅	Connected to SVID_CLK-R net, which is pulled up to +V1P0S through R197. This pin forms one end of the series resistor for the SVID clock line.
2	2	$24N3491	✅	Connected to U26 pin 4 (SCLK) through net $24N3491. This pin forms the controller side of the series resistor for the SVID clock line.

R193 - 1120-0329 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	SVID_DATA-R	✅	Connected to SVID_DATA-R net, which is pulled up to +V1P0S through R195. This pin forms one end of the series resistor for the SVID data line.
2	2	$24N3490	✅	Connected to U26 pin 2 (SDIO) through net $24N3490. This pin forms the controller side of the series resistor for the SVID data line.

R202 - 1120-0025 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VGFX	✅	Connects to +VGFX output rail for local voltage sensing. This provides a 100Ω series resistance path from the output to the VSP sense input.
2	2	VR-VGFX-VSP	✅	Connects to VR-VGFX-VSP net, which is the positive sense input (VSP, pin 46) of U26. This forms part of the differential remote sense circuit.

R68 - 1121-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCCGT_SENSE	✅	Connects to VCCGT_SENSE net for remote voltage sensing. This 0Ω jumper enables remote sensing when the VCCGT_SENSE signal is connected.
2	2	VR-VGFX-VSP	✅	Connects to VR-VGFX-VSP net, which is the positive sense input (VSP, pin 46) of U26. This provides the remote sensing path.

R201 - 1120-0025 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connects to GND. This resistor is in parallel with R69 (0Ω), which effectively bypasses R201's 100Ω resistance.
2	2	$24N3528	✅	Connects to $24N3528, an internal node in the VSN sensing network. This node connects to VSN through R169 and to GND through parallel R201 and R69.

R69 - 1121-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Connects to GND. This 0Ω jumper is in parallel with R201 (100Ω), providing a low-impedance ground path.
2	2	$24N3528	✅	Connects to $24N3528, an internal node in the VSN sensing network. This provides the low-impedance ground connection for the VSN path.

R169 - 1120-0022 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3528	✅	Connects to $24N3528, an internal node that connects to GND through parallel R201 and R69. This forms the ground reference side of the differential sense circuit.
2	2	VR-VGFX-VSN	✅	Connects to VR-VGFX-VSN, which is the negative sense input (VSN, pin 45) of U26. This completes the differential sense circuit.

C61 - 2221-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VR-VGFX-VSP	✅	DNI capacitor that would provide differential filtering between VSP and VSN sense inputs. Not installed, likely to avoid phase shift in the feedback loop.
2	2	VR-VGFX-VSN	✅	DNI capacitor that would provide differential filtering between VSP and VSN sense inputs. Not installed, likely to avoid phase shift in the feedback loop.

C104 - 2221-0004 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3528	✅	DNI capacitor that would provide filtering on the VSN sense path. Not installed, likely to avoid phase shift in the feedback loop.
2	2	VR-VGFX-VSN	✅	DNI capacitor that would provide filtering on the VSN sense path. Not installed, likely to avoid phase shift in the feedback loop.

C434 - 2222-0016 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N6011	✅	Connected to enable control net $24N6011 for filtering.
2	2	GND	✅	Connected to GND to complete the bypass capacitor function.

R850 - 1121-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC	✅	Connected to +VCC power rail to provide enable control signal.
2	2	$24N6011	✅	Connected to enable control net $24N6011 which drives U26 pin 48 (EN).

R852 - 1120-0011 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N6011	✅	Connected to enable control net $24N6011 to provide pull-down function.
2	2	GND	✅	Connected to GND to complete the pull-down function.

R230 - 1120-0052 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VCC3	✅	Connected to +VCC3 power rail to provide pull-up voltage source for the power good signal.
2	2	VGFX_PG	✅	Connected to VGFX_PG net, providing pull-up function for the power good signal.

C60 - 2222-0016 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX_PG	✅	Connected to VGFX_PG net to provide signal filtering and noise suppression.
2	2	GND	✅	Connected to GND to complete the filtering path for the power good signal.

R184 - 1121-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX_PG	✅	Connected to VGFX_PG net, which is the conditioned power good signal with pull-up and filtering.
2	2	$24N3598	✅	Connected to U26 pin 6 (VR_RDY), the voltage regulator power ready output signal.

R228 - 1130-0234 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3593	✅	Connected to the BST (bootstrap) pin of U26 (NCP81109GMNTXG) via net $24N3593. This resistor provides series damping and current limiting for the bootstrap circuit.
2	2	$24N3596	✅	Connected to bootstrap capacitor C186 pin 1 via net $24N3596. This forms the series R-C bootstrap network. However, C186 pin 2 has a connection issue that affects the overall bootstrap circuit functionality.

C186 - 2222-0008 ❌

DRCY flagged 1 potential issues in this component.

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
2	2	$24N3595	❌	Connected to U26 pin 10 (SW1) via net $24N3595, but should connect to the main switching node VGFX-SW. The bootstrap capacitor must reference the actual switching node where the inductor connects to provide proper gate drive voltage for the high-side MOSFET. Pin 2 is connected to net $24N3595 (from schematic) Net $24N3595 connects only to U26 pin 10 (SW1) (from schematic) The main switching node is VGFX-SW, which connects to U26 pins 18, 25, 26, 27, 28, 29 (SW2-SW7) and pin 51 (SW_PAD) (from schematic) The output inductor L4 pin 1 connects to VGFX-SW, confirming this is the main switching node (from schematic) SW1 is isolated and not connected to VGFX-SW or to any other part of the power stage except the bootstrap capacitor (from schematic) This is a multiphase buck converter with only one inductor (L4), and all active switch nodes (SW2-SW7) are paralleled to VGFX-SW (from schematic) In a synchronous buck converter, the bootstrap capacitor must be connected between the BST pin and the switching node to provide proper gate drive voltage for the high-side MOSFET (reasoning) The switching node is defined as the connection point between the high-side and low-side MOSFETs, which is where the inductor connects in a buck converter (reasoning) Since the inductor connects to VGFX-SW and all active switch outputs (SW2-SW7) connect to VGFX-SW, the bootstrap capacitor should be connected between BST and VGFX-SW (reasoning) The current configuration with the bootstrap capacitor connected to the isolated SW1 pin will not provide proper bootstrap voltage referenced to the actual switching node (reasoning) Pin 2 should be connected to net VGFX-SW instead of net $24N3595 to form a functional bootstrap circuit (reasoning) While there is a small possibility that SW1 is intentionally designed as a separate bootstrap reference node in the NCP81109GMNTXG, this would be highly unusual and inconsistent with standard synchronous buck converter design practice (reasoning) The 0.22µF capacitance and 16V voltage rating are appropriate for a bootstrap capacitor in a 5V input system (reasoning)
1	1	$24N3596	✅	Connected to bootstrap resistor R228. This is the charging side of the bootstrap capacitor.

R229 - 1130-0234 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Connected to +5VSB supply rail. This pin sources power for the VCC bias supply of U26 through the 2.2 ohm current-limiting resistor.
2	2	$24N3610	✅	Connected to net $24N3610, which supplies U26 pin 47 (VCC) and is bypassed by C53. This provides the bias supply voltage for the controller IC.

R846 - 1130-0193 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Connected to +5VSB supply rail. This pin sources power for the VCCP charge pump supply of U26 through the 1 ohm current-limiting resistor.
2	2	$24N3578	✅	Connected to net $24N3578, which supplies U26 pin 33 (VCCP) and is bypassed by C185. This provides the charge pump supply voltage for the gate driver.

C53 - 2222-0014 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3610	✅	Connected to net $24N3610, which is the VCC supply for U26 after current limiting by R229. This pin provides bypass capacitance for the controller bias supply.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX analog ground. This provides the return path for the VCC bypass capacitor, correctly referenced to the analog ground plane.

C185 - 2232-0016 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3578	✅	Connected to net $24N3578, which is the VCCP charge pump supply for U26 after current limiting by R846. This pin provides bypass capacitance for the charge pump supply.
2	2	GND	✅	Connected to GND power ground. This provides the return path for the VCCP bypass capacitor, referenced to power ground to keep charge pump switching currents separate from the analog ground.

R203 - 1120-0351 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3542	✅	Connected to U26 FREQ pin to set switching frequency. Text note indicates target frequency of 650 kHz.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX (analog ground), which is appropriate for a frequency-setting resistor.

R207 - 1120-0115 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3588	✅	Connected to U26 IMAX pin (pin 35) to set the maximum current limit. A text note near this component indicates IMAX = 14A.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX (analog ground). This provides the ground reference for the IMAX current limit setting.

C184 - 2220-0025 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3589	✅	Connected to U26 IOUT pin (pin 36) for current monitoring. Forms an RC filter with R227 to filter the current sense output signal.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX (analog ground). This completes the RC filter with R227 for current monitoring.

R227 - 1120-0338 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3589	✅	Connected to U26 IOUT pin (pin 36) for current monitoring. Forms an RC filter with C184 to filter the current sense output signal.
2	2	AGND-VGFX	✅	Connected to AGND-VGFX (analog ground). This provides the ground reference for the current monitoring filter.

R231 - 1141-0026 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VGFX-SW	✅	Connected to the switching node VGFX-SW of the DC/DC converter. This is the input of the RC snubber circuit.
2	2	$24N3623	✅	Connected to the intermediate node of the RC snubber, which connects to capacitor C187.

C187 - 2240-0005 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$24N3623	✅	Connected to the intermediate node of the RC snubber, receiving the filtered signal from R231.
2	2	GND	✅	Connected to ground, completing the RC snubber circuit path.

R66 - 1121-0001 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	R66 is a 0-ohm jumper connecting the power ground (GND) to the analog ground (AGND-VGFX), implementing a star ground topology for the DC-DC controller U26.
2	2	AGND-VGFX	✅	R66 is a 0-ohm jumper connecting the power ground (GND) to the analog ground (AGND-VGFX), implementing a star ground topology for the DC-DC controller U26.

U41 - RT8207 ❌

DRCY flagged 1 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
22	BOOT	$25N771	❌	BOOT pin connected to bootstrap network, but bootstrap capacitor C309 is significantly undersized (0.1uF instead of recommended 1uF) and includes non-standard series resistor R298 (4.7Ω), which may cause insufficient gate drive voltage and slower switching transitions. Pin 22 (BOOT) is connected to net $25N771 (from schematic) Net $25N771 connects through R298 (4.7Ω resistor) to DDR_BST net (from schematic) DDR_BST connects to C309 pin 2 (0.1uF capacitor) (from schematic) C309 pin 1 connects to DDR_PHASE net (PHASE pin) (from schematic) BOOT is the boost flying capacitor connection for VDDQ that supplies high side gate driver instantaneous current (from datasheet RT8207, page 2) Datasheet recommends 1uF flying bootstrap capacitor between BOOT and PHASE pins (from datasheet RT8207, page 16) Typical application circuits show direct connection of bootstrap capacitor without series resistance (from datasheet RT8207, page 3) Actual bootstrap capacitor C309 is 0.1uF, which is 10x smaller than the recommended 1uF (reasoning) Undersized bootstrap capacitor may cause insufficient gate drive voltage for high-side MOSFET, especially at high switching frequencies (reasoning) Series resistor R298 (4.7Ω) is not shown in datasheet reference designs and will cause voltage drop during gate charging (reasoning) The series resistor will slow bootstrap capacitor charging and may affect gate drive performance (reasoning) Bootstrap capacitor should be increased to 1uF and series resistor should be removed to match datasheet recommendations (reasoning)
1	VTTGND	GND	✅	VTTGND pin correctly connected to GND for VTT LDO power ground.
2	VTTSNS	+VDIMM_VTT	✅	VTTSNS pin correctly connected to +VDIMM_VTT for remote voltage sensing of VTT output.
3	GND	GND	✅	GND pin correctly connected to system ground for analog ground reference.
4	MODE	GND	✅	MODE pin connected to GND. Function not documented in available datasheet for 20-pin variant, but connection appears to be a valid mode selection.
5	VTTREF	$25N769	✅	VTTREF pin correctly connected to bypass capacitor C342 (0.22uF) for buffered reference output.
6	DEM	$25N1291	✅	DEM pin connected to pull-up resistor R810 (10K to +5VSB). Function not documented in available 20-pin datasheet, likely controls diode emulation mode.
8	VDDQ	+VDIMM	✅	VDDQ pin correctly connected to +VDIMM output rail for reference input and discharge control.
9	FB	$25N987	✅	FB pin correctly connected to resistor divider (R814=8.06K, R815=10K) and compensation capacitor C382 (22pF) to set output voltage to 1.35V for DDR3L.
10	S3	EN_VTT	✅	S3 pin correctly connected to EN_VTT signal through R302 (0 ohm) for VTT output control.
11	S5	EN_VDDQ	✅	S5 pin correctly connected to EN_VDDQ signal through R300 (0 ohm) for overall power state control.
12	TON	$25N1081	✅	TON pin correctly connected to +5VSB through R816, but R816 has incorrect value (464K instead of specified 806K), resulting in switching frequency of approximately 504kHz instead of the intended 285kHz.
13	PGOOD	DRAM_PWROK	✅	PGOOD pin correctly connected to DRAM_PWROK signal for power good indication.
14	VDD	$25N1195	✅	VDD pin correctly connected through RC filter (R813=2.2Ω, C380=1uF) from +5VSB for analog supply.
15	VDDP	+5VSB	✅	VDDP pin correctly connected directly to +5VSB for gate driver supply.
16	CS	$25N1238	✅	CS pin correctly connected through R817 (3.83K) to VDD for current limit threshold setting.
18	PGND	GND	✅	PGND pin correctly connected to GND for power ground of low-side MOSFET.
19	LGATE	$25N901	✅	LGATE pin correctly connected to Q102 pin 8 (Q2G) for low-side MOSFET gate drive.
20	PHASE	DDR_PHASE	✅	PHASE pin correctly connected to switching node between MOSFETs and output inductor L11.
21	UGATE	$25N897	✅	UGATE pin correctly connected to Q102 pin 1 (Q1G) for high-side MOSFET gate drive.
23	VLDOIN	+VDIMM	✅	VLDOIN pin correctly connected to +VDIMM for VTT LDO power supply and tracking discharge mode.
24	VTT	+VDIMM_VTT	✅	VTT pin correctly connected to +VDIMM_VTT output rail for VTT LDO power output.
25	GND_PAD	GND	✅	GND_PAD (exposed pad) correctly connected to GND for thermal dissipation and ground reference.

R816 - 1120-0149 ❌

DRCY flagged 1 potential issues in this component.

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	❌	TON timing resistor has incorrect value of 464K; should be 806K per design specification to achieve the intended 285kHz switching frequency. Current value results in approximately 504kHz operation. R816 pin 1 is connected to +5VSB net (from schematic) R816 pin 2 is connected to net $25N1081 (TON pin of U41) (from schematic) R816 value is 464K per component attributes (from schematic) Schematic design note specifies 'Rton=806K, F=285KHz' (from schematic) On-time formula is tON = 3.85p × RTON × VVDDQ / (VIN - 0.5) (from datasheet RT8207, page 15) Switching frequency formula: f = (VIN - 0.5) / (3.85p × VIN × RTON) (from schematic) With RTON=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 504kHz (reasoning) With RTON=806K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 290kHz, matching the design note (reasoning) The resistor value does not match the design specification, indicating an error in component selection (reasoning) Higher switching frequency affects inductor selection, core losses, switching losses, and EMI performance (reasoning) R816 should be changed from 464K to 806K to achieve the intended 285kHz switching frequency (reasoning)
2	2	$25N1081	❌	TON timing resistor has incorrect value of 464K; should be 806K per design specification to achieve the intended 285kHz switching frequency. Current value results in approximately 504kHz operation. R816 pin 1 is connected to +5VSB net (from schematic) R816 pin 2 is connected to net $25N1081 (TON pin of U41) (from schematic) R816 value is 464K per component attributes (from schematic) Schematic design note specifies 'Rton=806K, F=285KHz' (from schematic) On-time formula is tON = 3.85p × RTON × VVDDQ / (VIN - 0.5) (from datasheet RT8207, page 15) Switching frequency formula: f = (VIN - 0.5) / (3.85p × VIN × RTON) (from schematic) With RTON=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 504kHz (reasoning) With RTON=806K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 290kHz, matching the design note (reasoning) The resistor value does not match the design specification, indicating an error in component selection (reasoning) Higher switching frequency affects inductor selection, core losses, switching losses, and EMI performance (reasoning) R816 should be changed from 464K to 806K to achieve the intended 285kHz switching frequency (reasoning)

R814 - 1120-0187 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Upper feedback resistor correctly connected between +VDIMM output and FB pin to set output voltage to 1.35V for DDR3L operation.
2	2	$25N987	✅	Upper feedback resistor correctly connected between +VDIMM output and FB pin to set output voltage to 1.35V for DDR3L operation.

R815 - 1120-0011 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N987	✅	Lower feedback resistor correctly connected between FB pin and ground to set output voltage to 1.35V for DDR3L operation.
2	2	GND	✅	Lower feedback resistor correctly connected between FB pin and ground to set output voltage to 1.35V for DDR3L operation.

R817 - 1120-0267 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1195	✅	Current limit setting resistor correctly connected between VDD and CS pin to set overcurrent protection threshold to approximately 11A.
2	2	$25N1238	✅	Current limit setting resistor correctly connected between VDD and CS pin to set overcurrent protection threshold to approximately 11A.

R813 - 110-0004466 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1195	✅	RC filter resistor correctly connected between VDDP supply and VDD analog supply for noise filtering. Value is 2.2Ω, which is lower than the typical 5.1Ω recommendation but provides adequate filtering with reduced voltage drop.
2	2	+5VSB	✅	RC filter resistor correctly connected between VDDP supply and VDD analog supply for noise filtering. Value is 2.2Ω, which is lower than the typical 5.1Ω recommendation but provides adequate filtering with reduced voltage drop.

R810 - 110-0001875 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N1291	✅	Pull-up resistor for DEM pin, likely configuring diode emulation mode operation. The schematic uses a 24-pin package variant while available datasheet shows 20-pin variant, so DEM pin function cannot be fully verified from datasheet.
2	2	+5VSB	✅	Pull-up resistor for DEM pin, likely configuring diode emulation mode operation. The schematic uses a 24-pin package variant while available datasheet shows 20-pin variant, so DEM pin function cannot be fully verified from datasheet.

C382 - 2220-0047 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Compensation capacitor (22pF) in feedback network, providing stability for feedback divider.
2	2	$25N987	✅	Compensation capacitor (22pF) in feedback network, providing stability for feedback divider.

Q102 - FDMS3604S ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	Q1G	$25N897	✅	High-side gate (Q1G) correctly connected to UGATE output from controller U41 pin 21 via net $25N897.
2	VIN_A	DDR3L_VIN	✅	Drain pins (VIN_A, VIN_B, VIN_C) correctly connected to input voltage rail DDR3L_VIN, which is derived from +5VSB through ferrite beads.
3	VIN_B	DDR3L_VIN	✅	Drain pins (VIN_A, VIN_B, VIN_C) correctly connected to input voltage rail DDR3L_VIN, which is derived from +5VSB through ferrite beads.
4	VIN_C	DDR3L_VIN	✅	Drain pins (VIN_A, VIN_B, VIN_C) correctly connected to input voltage rail DDR3L_VIN, which is derived from +5VSB through ferrite beads.
5	PGND_A	GND	✅	Source pins (PGND_A, PGND_B, PGND_C) correctly connected to ground, providing the return path for the low-side synchronous FET.
6	PGND_B	GND	✅	Source pins (PGND_A, PGND_B, PGND_C) correctly connected to ground, providing the return path for the low-side synchronous FET.
7	PGND_C	GND	✅	Source pins (PGND_A, PGND_B, PGND_C) correctly connected to ground, providing the return path for the low-side synchronous FET.
8	Q2G	$25N901	✅	Low-side gate (Q2G) correctly connected to LGATE output from controller U41 pin 19 via net $25N901.
9	PHASE	DDR_PHASE	✅	PHASE pin correctly connected to output inductor L11 and bootstrap capacitor C309, forming the switching node of the buck converter.

R298 - 110-0004467 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	$25N771	✅	Bootstrap resistor input correctly connected to U41 BOOT pin via net $25N771, forming part of the bootstrap charging circuit.
2	2	DDR_BST	✅	Bootstrap resistor output correctly connected to intermediate bootstrap node DDR_BST, which connects to bootstrap capacitor C309.

L11 - 125-0004454 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	DDR_PHASE	✅	Inductor input correctly connected to switching node DDR_PHASE from Q102 pin 9.
2	2	+VDIMM	✅	Inductor output correctly connected to output voltage rail +VDIMM, which supplies 1.35V to the DIMM with maximum current of 7.1A.

L5 - 126-0004457 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is correctly connected to the +5VSB standby power rail, serving as the input to the ferrite bead filter.
2	2	DDR3L_VIN	✅	Pin 2 is correctly connected to the DDR3L_VIN net, providing filtered power to the DDR3L voltage regulator input stage.

L6 - 126-0004457 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	Pin 1 is correctly connected to the +5VSB standby power rail in parallel with L5, serving as the input to the ferrite bead filter.
2	2	DDR3L_VIN	✅	Pin 2 is correctly connected to the DDR3L_VIN net in parallel with L5, providing filtered power to the DDR3L voltage regulator input stage.

C129 - 123-0005035 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	P	+VDIMM	✅	Positive terminal correctly connected to +VDIMM output rail. This is the bulk output capacitor for the DDR memory power supply. However, the 2V voltage rating provides marginal derating for the 1.35V rail.
2	N	GND	✅	Negative terminal correctly connected to ground reference.

C361 - 2232-0012 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM_VTT	✅	Connected to +VDIMM_VTT rail. This pin provides bulk decoupling for the VTT termination voltage output from the RT8207 DDR power controller.
2	2	GND	✅	Connected to GND. This provides the return path for the VTT rail decoupling capacitor.

C362 - 2232-0012 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM_VTT	✅	Connected to +VDIMM_VTT rail in parallel with C361. This provides additional bulk decoupling capacitance and reduces ESR/ESL for the VTT termination voltage.
2	2	GND	✅	Connected to GND. This provides the return path for the VTT rail decoupling capacitor.

C359 - 2232-0012 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+VDIMM	✅	Output decoupling capacitor for +VDIMM rail. Pin 1 connects to +VDIMM, Pin 2 connects to GND.
2	2	GND	✅	Output decoupling capacitor for +VDIMM rail. Pin 1 connects to +VDIMM, Pin 2 connects to GND.

C140 - 123-0001176 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V).
2	2	+VDIMM	✅	Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V).

C137 - 123-0001176 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V).
2	2	+VDIMM	✅	Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V).

C141 - 123-0001176 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V).
2	2	+VDIMM	✅	Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V).

C126 - 123-0001176 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is connected to GND, providing the ground reference for this input decoupling capacitor.
2	2	DDR3L_VIN	✅	Pin 2 is connected to DDR3L_VIN, the input power rail for the DDR buck converter.

C127 - 123-0001176 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is connected to GND, providing the ground reference for this input decoupling capacitor.
2	2	DDR3L_VIN	✅	Pin 2 is connected to DDR3L_VIN, the input power rail for the DDR buck converter.

C128 - 123-0001176 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is connected to GND, providing the ground reference for this input decoupling capacitor.
2	2	DDR3L_VIN	✅	Pin 2 is connected to DDR3L_VIN, the input power rail for the DDR buck converter.

C328 - 123-0001176 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	Pin 1 is connected to GND, providing the ground reference for this input decoupling capacitor.
2	2	DDR3L_VIN	✅	Pin 2 is connected to DDR3L_VIN, the input power rail for the DDR buck converter.

R24 - 110-0002560 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	R24 (12.1K) is correctly configured as the upper resistor (R1) in the feedback divider for U21, connecting from +V1P8S to +V1P8S_FB.
2	2	+V1P8S_FB	✅	R24 (12.1K) is correctly configured as the upper resistor (R1) in the feedback divider for U21, connecting from +V1P8S to +V1P8S_FB.

R25 - 110-0004490 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	GND	✅	R25 (9.53K) is correctly configured as the lower resistor (R2) in the feedback divider for U21, connecting from +V1P8S_FB to GND.
2	2	+V1P8S_FB	✅	R25 (9.53K) is correctly configured as the lower resistor (R2) in the feedback divider for U21, connecting from +V1P8S_FB to GND.

R23 - 110-0002058 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8S	✅	R23 (4.7K) is correctly configured as a pull-up resistor for the power good signal, connecting from +V1P8S to +V1P8S_PGD.
2	2	+V1P8S_PGD	✅	R23 (4.7K) is correctly configured as a pull-up resistor for the power good signal, connecting from +V1P8S to +V1P8S_PGD.

R22 - 110-0001853 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	1P8V_EN	✅	R22 (0 ohm) is correctly configured as a jumper connecting the enable signal 1P8V_EN to +V1P8S_EN.
2	2	+V1P8S_EN	✅	R22 (0 ohm) is correctly configured as a jumper connecting the enable signal 1P8V_EN to +V1P8S_EN.

U21 - LDO_ULD_3A_SO8 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	PGOOD	+V1P8S_PGD	✅	PGOOD pin is correctly connected to +V1P8S_PGD net, which is pulled up to the output voltage through R23 (4.7K). This is a typical configuration for an open-drain power good output.
2	EN	+V1P8S_EN	✅	EN pin is correctly connected to +V1P8S_EN net, which is driven from 1P8V_EN through R22 (0 ohm jumper). The enable signal is pulled up to +VCC through R125 (4.7K), which will exceed the 1.1V enable threshold.
3	VIN	+PS_3VSB	✅	VIN pin is correctly connected to +PS_3VSB, the input power supply rail. Multiple input capacitors (C3, C6, C19, C156, C18) are present for filtering and stability.
4	VDD	+PS_3VSB	✅	VDD pin is correctly connected to +PS_3VSB, the same as VIN. This is typical for LDOs where VDD supplies the control circuitry.
5	NC		✅	NC pin has no connection, which is correct as this pin is designated as no connect.
6	VOUT	+V1P8S	✅	VOUT pin is correctly connected to +V1P8S output rail. Multiple output capacitors (C8, C4, C7) provide filtering and stability. The output voltage is approximately 1.816V based on the feedback divider.
7	ADJ	+V1P8S_FB	✅	ADJ pin is correctly connected to +V1P8S_FB feedback node. The feedback divider consists of R24 (12.1K) to VOUT and R25 (9.53K) to GND, which sets the output voltage to approximately 1.816V using the formula Vout = 0.8(1 + R1/R2).
8	GND1	GND	✅	GND1 pin is correctly connected to the GND net, providing the ground reference for the regulator.
9	GND2	GND	✅	GND2 pin is correctly connected to the GND net. Having two ground pins improves thermal and electrical performance.

R320 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	VCNTL_V1P0S	✅	10 ohm resistor connects VCNTL pin of U38 LDO to +VCC supply rail, with 1uF capacitor to ground forming RC filter. Connection purpose cannot be definitively verified without U38 datasheet.
2	2	+VCC	✅	10 ohm resistor connects VCNTL pin of U38 LDO to +VCC supply rail, with 1uF capacitor to ground forming RC filter. Connection purpose cannot be definitively verified without U38 datasheet.

U38 - LDO_ULD_5A_SO8 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	GND	GND	✅	Ground pin correctly connected to GND net.
2	FB	FB_V1P0S	✅	Feedback pin correctly connected to resistive divider network formed by R136 (40.2K to output) and R135 (143K to ground).
3	VOUT-2	+V1P0S	✅	Output pins correctly connected together to +V1P0S rail with appropriate decoupling capacitors. However, the total load current of 4.9A (1.3A + 3.6A per text notes) leaves only 2% margin below the 5A maximum rating, which is insufficient for robust design.
4	VOUT-1	+V1P0S	✅	Output pins correctly connected together to +V1P0S rail with appropriate decoupling capacitors. However, the total load current of 4.9A (1.3A + 3.6A per text notes) leaves only 2% margin below the 5A maximum rating, which is insufficient for robust design.
5	VIN-2	+VDIMM	✅	Input pins correctly connected together to +VDIMM supply rail with appropriate input capacitors.
9	VIN-1	+VDIMM	✅	Input pins correctly connected together to +VDIMM supply rail with appropriate input capacitors.
6	VCNTL	VCNTL_V1P0S	✅	VCNTL pin connected to +VCC through R320 (10 ohm) with C117 (1uF) to ground. Without datasheet, cannot verify if this configuration is correct for the VCNTL function.
7	POK	V1P0S_PG	✅	Power good output pin correctly connected to V1P0S_PG net with pullup resistor R319 (10K to +VCC) and driving enable signal for downstream regulator through R134.
8	EN	1P0V_EN	✅	Enable input pin correctly connected to 1P0V_EN net, which is controlled by VCORE_GFX_PG through R306 (0 ohm jumper).

R150 - 110-0002560 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	Upper feedback resistor correctly connected between the SENSE/ADJ pin and VOUT to set the output voltage.
2	2	+V1P8A	✅	Upper feedback resistor correctly connected between the SENSE/ADJ pin and VOUT to set the output voltage.

U20 - NCP606 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	VIN1	+PS_3VSB	✅	VIN1 is correctly connected to the +PS_3VSB input power rail with appropriate decoupling capacitors nearby.
2	GND	GND	✅	GND pin is correctly connected to the ground plane.
3	EN	+V1P8A_EN	✅	EN pin is correctly connected to the power sequencing enable signal from U24 through R151, with appropriate filtering capacitor C158.
4	VOUT	+V1P8A	✅	VOUT pin is correctly connected to the +V1P8A output rail with adequate decoupling capacitor C151.
5	SENSE/ADJ	+V1P8A_FB	✅	SENSE/ADJ pin is correctly connected to a resistor divider network (R150 and R153) that sets the output voltage to approximately 1.8V.
6	VIN2	+PS_3VSB	✅	VIN2 is correctly connected to +PS_3VSB, matching VIN1 as required by the datasheet.
7	GND_PAD	GND	✅	GND_PAD (exposed pad) is correctly connected to ground for thermal management.

R153 - 110-0002726 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P8A_FB	✅	Lower feedback resistor correctly connected between the SENSE/ADJ pin and ground to set the output voltage.
2	2	GND	✅	Lower feedback resistor correctly connected between the SENSE/ADJ pin and ground to set the output voltage.

R151 - 110-0001853 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_PWRGD	✅	Zero-ohm resistor correctly passes the power good signal from U24 to enable U20, creating proper power sequencing.
2	2	+V1P8A_EN	✅	Zero-ohm resistor correctly passes the power good signal from U24 to enable U20, creating proper power sequencing.

U24 - LDO_ULD_3A_SO8 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	PGOOD	+V1P0A_PWRGD	✅	PGOOD pin is correctly connected to +V1P0A_PWRGD net with pull-up resistor R33 to +PS_3VSB. This provides an open-drain power good output signal for sequencing.
2	EN	+V1P0A_ENABLE	✅	EN pin is correctly connected to +V1P0A_ENABLE net with pull-up resistor R32 from +5VSB. The enable threshold requirement of >1.1V is satisfied by the +5VSB pull-up.
3	VIN	+PS_3VSB	✅	VIN pin is correctly connected to +PS_3VSB, which is the 3.3V standby input supply for the LDO.
4	VDD	+PS_3VSB	✅	VDD pin is correctly connected to +PS_3VSB, providing power to the internal control circuitry of the LDO.
5	NC		✅	NC pin is correctly left unconnected as specified by the component definition.
6	VOUT	+V1P0A	✅	VOUT pin is correctly connected to +V1P0A net with appropriate decoupling capacitors. The output provides 1.0V analog supply.
7	ADJ	+V1P0A_FB	✅	ADJ pin is correctly connected to the feedback network consisting of R34 (6.04K) and R35 (23.7K), which sets the output voltage to approximately 1.0V.
8	GND1	GND	✅	GND1 and GND2 pins are correctly connected to the GND net. Dual ground pins are typical for LDOs to improve thermal and electrical performance.
9	GND2	GND	✅	GND1 and GND2 pins are correctly connected to the GND net. Dual ground pins are typical for LDOs to improve thermal and electrical performance.

R32 - 4.7K ohm 1% 1/10W 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+5VSB	✅	R32 is a pull-up resistor correctly connected between +5VSB and the enable pin of U24, ensuring the enable signal is above the 1.1V threshold when active.
2	2	+V1P0A_ENABLE	✅	R32 is a pull-up resistor correctly connected between +5VSB and the enable pin of U24, ensuring the enable signal is above the 1.1V threshold when active.

R35 - 23.7K ohm 1% 1/4W 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	R35 is the bottom resistor (R2) in the feedback divider network for U24, correctly connected between the ADJ pin and GND to set the output voltage to 1.0V.
2	2	GND	✅	R35 is the bottom resistor (R2) in the feedback divider network for U24, correctly connected between the ADJ pin and GND to set the output voltage to 1.0V.

R33 - 4.7K ohm 1% 1/10W 0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+PS_3VSB	✅	R33 is a pull-up resistor correctly connected between +PS_3VSB and the power good output of U24, providing proper open-drain operation.
2	2	+V1P0A_PWRGD	✅	R33 is a pull-up resistor correctly connected between +PS_3VSB and the power good output of U24, providing proper open-drain operation.

R34 - 6.04K ohm 1% 1/16W 0402 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_FB	✅	R34 is the top resistor (R1) in the feedback divider network for U24, correctly connected between the ADJ pin and VOUT to set the output voltage to 1.0V.
2	2	+V1P0A	✅	R34 is the top resistor (R1) in the feedback divider network for U24, correctly connected between the ADJ pin and VOUT to set the output voltage to 1.0V.

R120 - 10K0 resistor ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P35S	✅	Connected to +V1P35S output voltage from Q5 source for power good sensing.
2	2	1P35V_PWG	✅	Connected to 1P35V_PWG which drives the base of Q3 to generate power good signaling for downstream sequencing.

Q5 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
D	DRAIN	+VDIMM	✅	Drain is correctly connected to +VDIMM input voltage with appropriate decoupling capacitors for a high-side switch configuration.
G	GATE	1P35V_EN	✅	Gate is driven from V1P0S_PG through R134 (1kΩ) to enable the MOSFET when V1P0S power is good. The gate voltage depends on the +VCC rail voltage, which must provide sufficient VGS to fully enhance the MOSFET.
S	SOURCE	+V1P35S	✅	Source is correctly connected to +V1P35S output with decoupling capacitors and power good sensing through R120. The configuration is appropriate for a high-side switch.

R134 - RES_1Kohm_1%_1/10W_0402 ✅

DRCY found no issues in this component 🎉

ℹ️ DRCY didn't use a Datasheet for this component.

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	V1P0S_PG	✅	Connected to V1P0S_PG power good signal from U38 LDO, which controls the enable signal for Q5 gate drive.
2	2	1P35V_EN	✅	Connected to 1P35V_EN which drives the gate of Q5 through appropriate current limiting.

Q1 - XSTR_NPN_DUAL_40V_SOT-363 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	E1	GND	✅	Emitter 1 of first NPN transistor, correctly connected to ground.
2	B1	PSGOOD	✅	Base 1 of first NPN transistor, correctly connected to PSGOOD signal which controls the transistor switching.
3	C2	SYS_PWRGD	✅	Collector 2 of second NPN transistor, correctly connected to SYS_PWRGD output signal.
4	E2	GND	✅	Emitter 2 of second NPN transistor, correctly connected to ground.
5	B2	PSPUP	✅	Base 2 and Collector 1 are both connected to PSPUP, creating a feedback path where Q1A controls Q1B. This is correct for the power sequencing logic.
6	C1	PSPUP	✅	Base 2 and Collector 1 are both connected to PSPUP, creating a feedback path where Q1A controls Q1B. This is correct for the power sequencing logic.

Q3 - XSTR_NPN_DUAL_40V_SOT-363 ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	E1	GND	✅	Emitter 1 of first NPN transistor, correctly connected to ground.
2	B1	1P35V_PWG	✅	Base 1 of first NPN transistor, correctly connected to 1P35V_PWG signal which indicates the 1.35V rail is good.
3	C2	1P8V_EN	✅	Collector 2 of second NPN transistor, correctly connected to 1P8V_EN signal which enables the 1.8V regulator.
4	E2	GND	✅	Emitter 2 of second NPN transistor, correctly connected to ground.
5	B2	1P5V_EN_B	✅	Base 2 and Collector 1 are both connected to 1P5V_EN_B, creating a feedback path where Q3A controls Q3B. This is correct for the power sequencing logic.
6	C1	1P5V_EN_B	✅	Base 2 and Collector 1 are both connected to 1P5V_EN_B, creating a feedback path where Q3A controls Q3B. This is correct for the power sequencing logic.

D11 - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅

DRCY found no issues in this component 🎉

⚠️ DRCY couldn't retrieve a Datasheet for this component. 📤 Upload a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	1	+V1P0A_PWRGD	✅	Dual Schottky diode configured to combine power good signals. Pin assignment needs verification as datasheet is not available.
2	2	SLP_S3_L	✅	Dual Schottky diode configured to combine power good signals. Pin assignment needs verification as datasheet is not available.
3	3	PSGOOD	✅	Dual Schottky diode configured to combine power good signals. Pin assignment needs verification as datasheet is not available.

📤 Upload Missing Datasheets

DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews.

R127, R128, R129, R130, R192, R216, R243, R261, R293, R300, R302, R354, R41, R42, R43, R46, R48, R51, R72, R73, R74, R809 (110-0001853): 📤 Upload a datasheet
R147, R50 (110-0001859): 📤 Upload a datasheet
R102, R116, R124, R183, R190, R191, R2, R209, R210, R211, R220, R221, R260, R268, R28, R29, R30, R400, R71, R810 (110-0001875): 📤 Upload a datasheet
R186, R187, R208, R233, R234, R259, R401 (110-0001923): 📤 Upload a datasheet
R206, R812 (110-0001951): 📤 Upload a datasheet
R60, R61 (110-0001957): 📤 Upload a datasheet
R179 (110-0001960): 📤 Upload a datasheet
R11, R12, R269, R270 (110-0001967): 📤 Upload a datasheet
R171, R172, R257, R52 (110-0001984): 📤 Upload a datasheet
R819 (110-0002000): 📤 Upload a datasheet
R136 (110-0002029): 📤 Upload a datasheet
R152, R222, R265, R275 (110-0002124): 📤 Upload a datasheet
R150, R24 (110-0002560): 📤 Upload a datasheet
R213, R38, R39 (110-0002631): 📤 Upload a datasheet
R153 (110-0002726): 📤 Upload a datasheet
R240, R241, R242, R258 (110-0003059): 📤 Upload a datasheet
R34 (110-0003781): 📤 Upload a datasheet
R813 (110-0004466): 📤 Upload a datasheet
R298 (110-0004467): 📤 Upload a datasheet
R185, R77 (110-0004472): 📤 Upload a datasheet
R255 (110-0004474): 📤 Upload a datasheet
R217, R218, R239 (110-0004476): 📤 Upload a datasheet
R212 (110-0004478): 📤 Upload a datasheet
R25 (110-0004490): 📤 Upload a datasheet
R35 (110-0004494): 📤 Upload a datasheet
R135 (110-0004498): 📤 Upload a datasheet
R40 (110-0004695): 📤 Upload a datasheet
R832, R833, R834, R835 (1120-0003): 📤 Upload a datasheet
R837, R838, R839 (1120-0010): 📤 Upload a datasheet
R815, R820, R821, R822, R823, R824, R825, R826, R827, R828, R829, R830, R831 (1120-0011): 📤 Upload a datasheet
R836 (1120-0018): 📤 Upload a datasheet
R320 (1120-0022): 📤 Upload a datasheet
R847 (1120-0032): 📤 Upload a datasheet
R801, R802, R803, R804, R805, R806, R807, R808 (1120-0119): 📤 Upload a datasheet
R816 (1120-0149): 📤 Upload a datasheet
R814 (1120-0187): 📤 Upload a datasheet
R843, R844 (1120-0203): 📤 Upload a datasheet
R817 (1120-0267): 📤 Upload a datasheet
R848 (1120-0359): 📤 Upload a datasheet
R840, R841, R842 (1121-0001): 📤 Upload a datasheet
C10, C11, C12, C13, C177, C178, C179, C180 (123-0001038): 📤 Upload a datasheet
C191, C192, C205, C206, C207, C208 (123-0001056): 📤 Upload a datasheet
C252, C253 (123-0001107): 📤 Upload a datasheet
C103, C126, C127, C128, C137, C140, C141, C328, C91 (123-0001176): 📤 Upload a datasheet
C148 (123-0004408): 📤 Upload a datasheet
C129, C76, C77, C87 (123-0005035): 📤 Upload a datasheet
L11 (125-0004454): 📤 Upload a datasheet
L3 (125-0004501): 📤 Upload a datasheet
FB3 (126-0001423): 📤 Upload a datasheet
FB1, FB11, FB4, FB5, L12, L13, L5, L6 (126-0004457): 📤 Upload a datasheet
D11 (130-0004403): 📤 Upload a datasheet
U38 (140-0004525): 📤 Upload a datasheet
U21, U24 (140-0004526): 📤 Upload a datasheet
Y1 (145-0004789): 📤 Upload a datasheet
X1, Y2 (145-0004792): 📤 Upload a datasheet
P1 (158-0004513): 📤 Upload a datasheet
J10 (158-0004534): 📤 Upload a datasheet
C429, C430, C431 (2220-0039): 📤 Upload a datasheet
C382 (2220-0047): 📤 Upload a datasheet
C425 (2221-0017): 📤 Upload a datasheet
C428 (2222-0014): 📤 Upload a datasheet
C426, C427 (2222-0016): 📤 Upload a datasheet
C359, C361, C362, C419, C420, C421, C422, C423, C424 (2232-0012): 📤 Upload a datasheet
C66, C67, C68, C78, C79, C80, C81 (2242-0014): 📤 Upload a datasheet
J5, J6, J7 (258-0002513): 📤 Upload a datasheet
USB1 (258-0004503): 📤 Upload a datasheet
J2 (258-0004524): 📤 Upload a datasheet
J1 (258-0004612): 📤 Upload a datasheet
J4 (258-0004869): 📤 Upload a datasheet
JP1 (258-0005019): 📤 Upload a datasheet
FB12 (3044-0010): 📤 Upload a datasheet
FB13 (3044-0012): 📤 Upload a datasheet
L8 (3120-0183): 📤 Upload a datasheet
L18, L4 (3120-0266): 📤 Upload a datasheet
CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17 (3142-0014): 📤 Upload a datasheet
J11 (3362-0042): 📤 Upload a datasheet
J8 (3430-0212): 📤 Upload a datasheet
BH1 (353-0003073): 📤 Upload a datasheet
FL1 (3750-0010): 📤 Upload a datasheet
SW1 (3770-0026): 📤 Upload a datasheet
TH1, TH2, TH3, TH4 (3880-0004): 📤 Upload a datasheet
U42 (4300-0071): 📤 Upload a datasheet
U5, U6 (4327-0009): 📤 Upload a datasheet
D1, D2 (4560-0045): 📤 Upload a datasheet
D13 (4620-0026): 📤 Upload a datasheet
TP11, TP12 (999-0000002): 📤 Upload a datasheet
TP1, TP17, TP18, TP2 (999-0000003): 📤 Upload a datasheet
SP1, SP2 (999-0000005): 📤 Upload a datasheet
D3, D4, D6 (BAT54A-S): 📤 Upload a datasheet
D10, D5, D8 (BAT754C): 📤 Upload a datasheet
Q2, Q9 (BAV99-7-F-S-X): 📤 Upload a datasheet
L1, L2 (BKP2125HS221-T): 📤 Upload a datasheet
U33 (M24C02-WMN6TP-X): 📤 Upload a datasheet
U25, U26 (NCP81109GMNTXG): 📤 Upload a datasheet
U35 (NCT3012S-X): 📤 Upload a datasheet
U18 (NTB0104GU12): 📤 Upload a datasheet
U4, U7 (NTS0102GT): 📤 Upload a datasheet
U10, U14, U15, U16, U17, U19 (NTS0104GU12): 📤 Upload a datasheet
P2 (SCHA5B0200): 📤 Upload a datasheet
U29 (TPD4USB30): 📤 Upload a datasheet

_{^{Note: DRCY uses AI. Please verify the outputs.}}

# DRCY Connections Checker Review DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 374 component(s) to review, and found 12 potential issue(s) in 14 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below. <details> <summary>Component Details</summary> DRCY selected and reviewed all connections from the following components of the schematic: <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 2 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | BC1 | VGA_DDCCLK | CRT_CLK | ❌ | <details><summary>VGA_DDCCLK and VGA_DDCDATA pins incorrectly connected through 150-ohm resistors to GND. DDC uses I2C protocol which requires pull-up resistors, not pull-downs.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="55.34,40.37,62.84,47.87" aspect-ratio="1.29" } <ul><li>Pin BC1 is named VGA_DDCCLK and connects to net CRT_CLK (from schematic)</li><li>Pin BC2 is named VGA_DDCDATA and connects to net CRT_DAT (from schematic)</li><li>R39 (150 ohm) connects CRT_CLK pin 1 to GND pin 2 (from schematic)</li><li>R38 (150 ohm) connects CRT_DAT pin 1 to GND pin 2 (from schematic)</li><li>DDC (Display Data Channel) is an I2C-based protocol used for monitor communication and identification (reasoning)</li><li>I2C protocol requires pull-up resistors on both SDA and SCL lines because they are open-drain signals (reasoning)</li><li>Typical I2C pull-up resistor values range from 2.2K to 10K ohms connected to a positive voltage rail (typically 3.3V or 5V) (reasoning)</li><li>Pull-down resistors on I2C lines prevent proper communication by holding the lines low, making it impossible for devices to drive the lines high (reasoning)</li><li>The 150-ohm value is too low for I2C pull-ups and would draw excessive current even if connected to the correct rail (reasoning)</li><li>These resistors should be changed to pull-up resistors connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) with values in the 2.2K-10K range (reasoning)</li></ul></details> | | BC2 | VGA_DDCDATA | CRT_DAT | ❌ | <details><summary>VGA_DDCCLK and VGA_DDCDATA pins incorrectly connected through 150-ohm resistors to GND. DDC uses I2C protocol which requires pull-up resistors, not pull-downs.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="55.34,40.96,62.84,48.46" aspect-ratio="1.29" } <ul><li>Pin BC1 is named VGA_DDCCLK and connects to net CRT_CLK (from schematic)</li><li>Pin BC2 is named VGA_DDCDATA and connects to net CRT_DAT (from schematic)</li><li>R39 (150 ohm) connects CRT_CLK pin 1 to GND pin 2 (from schematic)</li><li>R38 (150 ohm) connects CRT_DAT pin 1 to GND pin 2 (from schematic)</li><li>DDC (Display Data Channel) is an I2C-based protocol used for monitor communication and identification (reasoning)</li><li>I2C protocol requires pull-up resistors on both SDA and SCL lines because they are open-drain signals (reasoning)</li><li>Typical I2C pull-up resistor values range from 2.2K to 10K ohms connected to a positive voltage rail (typically 3.3V or 5V) (reasoning)</li><li>Pull-down resistors on I2C lines prevent proper communication by holding the lines low, making it impossible for devices to drive the lines high (reasoning)</li><li>The 150-ohm value is too low for I2C pull-ups and would draw excessive current even if connected to the correct rail (reasoning)</li><li>These resistors should be changed to pull-up resistors connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) with values in the 2.2K-10K range (reasoning)</li></ul></details> | | AK12 | DDI0_RCOMP_P | DDI_RCOMP_N | ❌ | <details><summary>DDI RCOMP pins appear to be swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative) connects to DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P) connects to DDI_RCOMP_N. The pin naming convention suggests these connections are reversed.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,31.55,45.57,39.05" aspect-ratio="1.29" } <ul><li>Pin AK13 is named D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating active-low or negative signal (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</li><li>Pin AK12 is named DDI0_RCOMP_P with _P suffix indicating positive signal (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</li><li>In the schematic, pin AK13 connects to net DDI_RCOMP_P (from schematic)</li><li>In the schematic, pin AK12 connects to net DDI_RCOMP_N (from schematic)</li><li>The overline notation in pin names typically indicates the complement or negative signal in differential pairs (reasoning)</li><li>The _P suffix typically indicates the positive signal in differential pairs (reasoning)</li><li>Based on naming convention, AK13 should connect to the negative net and AK12 to the positive net (reasoning)</li><li>R217 (402 ohm) is connected between DDI_RCOMP_N and DDI_RCOMP_P as a compensation resistor (from schematic)</li><li>The connections should be corrected: AK13 to DDI_RCOMP_N and AK12 to DDI_RCOMP_P (reasoning)</li></ul></details> | | AK13 | ~DDI0_RCOMP | DDI_RCOMP_P | ❌ | <details><summary>DDI RCOMP pins appear to be swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative) connects to DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P) connects to DDI_RCOMP_N. The pin naming convention suggests these connections are reversed.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,38.46" aspect-ratio="1.29" } <ul><li>Pin AK13 is named D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating active-low or negative signal (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</li><li>Pin AK12 is named DDI0_RCOMP_P with _P suffix indicating positive signal (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</li><li>In the schematic, pin AK13 connects to net DDI_RCOMP_P (from schematic)</li><li>In the schematic, pin AK12 connects to net DDI_RCOMP_N (from schematic)</li><li>The overline notation in pin names typically indicates the complement or negative signal in differential pairs (reasoning)</li><li>The _P suffix typically indicates the positive signal in differential pairs (reasoning)</li><li>Based on naming convention, AK13 should connect to the negative net and AK12 to the positive net (reasoning)</li><li>R217 (402 ohm) is connected between DDI_RCOMP_N and DDI_RCOMP_P as a compensation resistor (from schematic)</li><li>The connections should be corrected: AK13 to DDI_RCOMP_N and AK12 to DDI_RCOMP_P (reasoning)</li></ul></details> | | A29 | RESERVED_A29 | GPIO_NC13 | ✅ | RESERVED_A29 pin connected to GPIO_NC13 net with 10K pull-down resistor R102 to ground. This configuration is appropriate for an unused or reserved GPIO pin. | | B26 | DDI0_BKLTCTL | | ✅ | DDI0_BKLTCTL (backlight control) pin is unconnected. For HDMI output, backlight control is not needed. | | B28 | DDI0_VDDEN | | ✅ | DDI0_VDDEN (VDD enable) pin is unconnected. For HDMI output, this control signal is not needed. | | B30 | GPIO_S0_NC12 | $3N566 | ✅ | GPIO_S0_NC12 pin connected to test point TP15 (marked DNI). This provides a test point for this GPIO signal. | | C26 | DDI0_DDCDATA | HDMI_DDCDAT | ✅ | DDI0_DDCDATA (HDMI DDC data) correctly connected to HDMI_DDCDAT net for HDMI monitor communication. | | C27 | DDI0_BKLTEN | | ✅ | DDI0_BKLTEN (backlight enable) pin is unconnected. For HDMI output, backlight enable is not needed. | | C28 | DDI0_DDCCLK | HDMI_DDCCLK | ✅ | DDI0_DDCCLK (HDMI DDC clock) correctly connected to HDMI_DDCCLK net for HDMI monitor communication. | | D27 | DDI0_HPD | HDMI_HPD_B | ✅ | DDI0_HPD (HDMI hot plug detect) correctly connected to HDMI_HPD_B through inverter U39. | | D28 | RESERVED_D28 | | ✅ | MIPI CSI GPIO pins with no connections shown. Appropriate if camera interface is not used in this design. | | F28 | RESERVED_F28 | | ✅ | MIPI CSI GPIO pins with no connections shown. Appropriate if camera interface is not used in this design. | | F32 | RESERVED_F32 | | ✅ | MIPI CSI GPIO pins with no connections shown. Appropriate if camera interface is not used in this design. | | F34 | RESERVED_F34 | | ✅ | MIPI CSI GPIO pins with no connections shown. Appropriate if camera interface is not used in this design. | | G30 | DDI1_DDCCLK | GND | ✅ | DDI1_DDCCLK pin connected to GND. This is intentional as DDI1 port is disabled per the 'Bay Trail-M Remove eDP Port' note. | | J30 | DDI1_BKLTEN | | ✅ | DDI1_BKLTEN pin is unconnected, consistent with disabled DDI1 port. | | K30 | DDI1_HPD | GND | ✅ | DDI1_HPD pin connected to GND. This is intentional as DDI1 port is disabled. | | M30 | DDI1_BKLTCTL | | ✅ | DDI1_BKLTCTL pin is unconnected, consistent with disabled DDI1 port. | | N30 | DDI1_VDDEN | | ✅ | DDI1_VDDEN pin is unconnected, consistent with disabled DDI1 port. | | P14 | RESERVED_P14 | MCSI_RCOMP | ✅ | RESERVED_P14 pin connected to MCSI_RCOMP with 150 ohm resistor R213 to GND. This provides compensation for the MIPI CSI interface. | | P30 | DDI1_DDCDATA | DDI1_DDCDAT | ✅ | DDI1_DDCDATA pin connected through 2.2K resistor R257 to GND. This provides pull-down for the unused DDI1 DDC data line. | | BA1 | VGA_GREEN | | ✅ | VGA_GREEN pin is unconnected. If VGA output is not used, this is acceptable. | | AB2 | RESERVED_AB2 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AB3 | RESERVED_AB3 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AB7 | RESERVED_AB7 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AB9 | RESERVED_AB9 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AB12 | RESERVED_AB12 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AB13 | RESERVED_AB13 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AB14 | RESERVED_AB14 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AD4 | RESERVED_AD4 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AD6 | RESERVED_AD6 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AF13 | RESERVED_AF13 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AF14 | RESERVED_AF14 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AH13 | RESERVED_AH13 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AH14 | RESERVED_AH14 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AM13 | RESERVED_AM13 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | AM14 | RESERVED_AM14 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | C29 | RESERVED_C29 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | C30 | RESERVED_C30 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | D32 | RESERVED_D32 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | D34 | RESERVED_D34 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | J28 | RESERVED_J28 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | J34 | RESERVED_J34 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | K28 | RESERVED_K28 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | K34 | RESERVED_K34 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | M32 | RESERVED_M32 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | N32 | RESERVED_N32 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | R1 | RESERVED_R1 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | R3 | RESERVED_R3 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | T2 | RESERVED_T2 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | T3 | RESERVED_T3 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | T4 | RESERVED_T4 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | T6 | RESERVED_T6 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | T7 | RESERVED_T7 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | T9 | RESERVED_T9 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | T10 | RESERVED_T10 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | T12 | RESERVED_T12 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | T13 | RESERVED_T13 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | T14 | RESERVED_T14 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | V2 | RESERVED_V2 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | V3 | RESERVED_V3 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | V4 | RESERVED_V4 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | V6 | RESERVED_V6 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | V9 | RESERVED_V9 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | V10 | RESERVED_V10 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | V13 | RESERVED_V13 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | V14 | RESERVED_V14 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | W1 | RESERVED_W1 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | W3 | RESERVED_W3 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | Y2 | RESERVED_Y2 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | Y3 | RESERVED_Y3 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | Y4 | RESERVED_Y4 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | Y6 | RESERVED_Y6 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | Y12 | RESERVED_Y12 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | Y13 | RESERVED_Y13 | | ✅ | Reserved pins with no connections shown in schematic. Appropriate to leave unconnected unless datasheet specifies otherwise. | | BA3 | VGA_RED | | ✅ | VGA_RED pin is unconnected. If VGA output is not used, this is acceptable. | | AC1 | DDI1_TXN_3 | | ✅ | DDI1_TXN_3 pin is unconnected. This is consistent with DDI1 port being disabled as indicated by the 'Bay Trail-M Remove eDP Port' note. | | AC3 | DDI1_TXP_3 | | ✅ | DDI1_TXP_3 pin is unconnected. This is consistent with DDI1 port being disabled. | | AD2 | DDI1_TXN_2 | | ✅ | DDI1_TXN_2 pin is unconnected, consistent with disabled DDI1 port. | | AD3 | DDI1_TXP_2 | | ✅ | DDI1_TXP_2 pin is unconnected, consistent with disabled DDI1 port. | | BD2 | VGA_HSYNC | | ✅ | VGA_HSYNC pin is unconnected. If VGA output is not used, this is acceptable. | | AF2 | DDI1_TXN_1 | | ✅ | DDI1_TXN_1 pin is unconnected, consistent with disabled DDI1 port. | | AF3 | DDI1_TXP_1 | | ✅ | DDI1_TXP_1 pin is unconnected, consistent with disabled DDI1 port. | | AG1 | DDI1_TXN_0 | | ✅ | DDI1_TXN_0 pin is unconnected, consistent with disabled DDI1 port. | | BF2 | VGA_VSYNC | | ✅ | VGA_VSYNC pin is unconnected. If VGA output is not used, this is acceptable. | | AG3 | DDI1_TXP_0 | | ✅ | DDI1_TXP_0 pin is unconnected, consistent with disabled DDI1 port. | | AH2 | RESERVED_VSS3 | $3N554 | ✅ | RESERVED_VSS3 pin connected through 0-ohm resistor R43 to GND. This is appropriate for a reserved ground pin. | | AH3 | RESERVED_VSS2 | $3N552 | ✅ | RESERVED_VSS2 pin connected through 0-ohm resistor R46 to GND. This is appropriate for a reserved ground pin. | | AK2 | DDI1_AUXN | | ✅ | DDI1_AUXN pin is unconnected, consistent with disabled DDI1 port. | | AK3 | DDI1_AUXP | | ✅ | DDI1_AUXP pin is unconnected, consistent with disabled DDI1 port. | | AL1 | DDI0_AUXN | | ✅ | DDI0_AUXN pin is unconnected. For HDMI operation, the AUX channel is not required, so this is acceptable. | | AL3 | DDI0_AUXP | | ✅ | DDI0_AUXP pin is unconnected. For HDMI operation, the AUX channel is not required, so this is acceptable. | | AM2 | RESERVED_VSS1 | $3N589 | ✅ | RESERVED_VSS1 pin connected through 0-ohm resistor R41 to GND. This is appropriate for a reserved ground pin. | | AM3 | RESERVED_VSS0 | $3N579 | ✅ | RESERVED_VSS0 pin connected through 0-ohm resistor R42 to GND. This is appropriate for a reserved ground pin. | | AP2 | DDI0_TXN_3 | HDMI_CLK_DN | ✅ | DDI0_TXN_3 (HDMI clock negative) correctly connected to HDMI_CLK_DN net for HDMI output. | | AP3 | DDI0_TXP_3 | HDMI_CLK_DP | ✅ | DDI0_TXP_3 (HDMI clock positive) correctly connected to HDMI_CLK_DP net for HDMI output. | | AR1 | DDI0_TXN_2 | HDMI_TX0_DN | ✅ | DDI0_TXN_2 (HDMI data lane 0 negative) correctly connected to HDMI_TX0_DN net. | | AR3 | DDI0_TXP_2 | HDMI_TX0_DP | ✅ | DDI0_TXP_2 (HDMI data lane 0 positive) correctly connected to HDMI_TX0_DP net. | | AT2 | DDI0_TXP_1 | HDMI_TX1_DP | ✅ | DDI0_TXP_1 (HDMI data lane 1 positive) correctly connected to HDMI_TX1_DP net. | | AT3 | DDI0_TXN_1 | HDMI_TX1_DN | ✅ | DDI0_TXN_1 (HDMI data lane 1 negative) correctly connected to HDMI_TX1_DN net. | | AV2 | DDI0_TXN_0 | HDMI_TX2_DN | ✅ | DDI0_TXN_0 (HDMI data lane 2 negative) correctly connected to HDMI_TX2_DN net. | | AV3 | DDI0_TXP_0 | HDMI_TX2_DP | ✅ | DDI0_TXP_0 (HDMI data lane 2 positive) correctly connected to HDMI_TX2_DP net. | | AW1 | VGA_IREF | $3N548 | ✅ | VGA_IREF pin correctly connected through 357 ohm resistor R40 to GND to set the VGA DAC reference current. | | AY2 | VGA_BLUE | | ✅ | VGA_BLUE pin is unconnected. If VGA output is not used, this is acceptable. | | AY3 | VGA_IRTN | GND | ✅ | VGA_IRTN (VGA current return) correctly connected to GND. | </details> <details> <summary>U39 - SN74LVC1G14DCKR ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/lit/ds/symlink/sn74lvc1g14.pdf?ts=1753365169590&ref_url=https%25253A%25252F%25252Fwww.ti.com%25252Fproduct%25252FSN74LVC1G14) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/SN74LVC1G14DCKR) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | NC pin is left unconnected, which is acceptable per datasheet. | | 2 | A | HDMI_HPD | ✅ | Input pin A receives HDMI_HPD signal for Schmitt-trigger inversion and noise immunity. | | 3 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 4 | Y | HDMI_HPD_B | ✅ | Output pin Y drives HDMI_HPD_B signal (inverted hot plug detect) to CPU1 DDI0_HPD input. | | 5 | VCC | +V1P8S | ✅ | VCC pin is correctly powered from +V1P8S (1.8V) with nearby decoupling capacitor C375. | </details> <details> <summary>R38 - 110-0002631 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CRT_DAT | ❌ | <details><summary>Pull-down resistor on VGA DDC data line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="68.52,40.96,76.02,48.46" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net CRT_DAT (from schematic)</li><li>Pin 2 is connected to GND (from schematic)</li><li>Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) (from schematic)</li><li>This resistor acts as a pull-down on the VGA DDC data line (reasoning)</li><li>DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning)</li><li>I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning)</li><li>Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning)</li><li>If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning)</li><li>If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning)</li><li>The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)</li></ul></details> | | 2 | 2 | GND | ❌ | <details><summary>Pull-down resistor on VGA DDC data line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="69.43,40.96,76.93,48.46" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net CRT_DAT (from schematic)</li><li>Pin 2 is connected to GND (from schematic)</li><li>Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) (from schematic)</li><li>This resistor acts as a pull-down on the VGA DDC data line (reasoning)</li><li>DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning)</li><li>I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning)</li><li>Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning)</li><li>If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning)</li><li>If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning)</li><li>The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)</li></ul></details> | </details> <details> <summary>R39 - 110-0002631 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CRT_CLK | ❌ | <details><summary>Pull-down resistor on VGA DDC clock line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="68.52,39.19,76.02,46.69" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net CRT_CLK (from schematic)</li><li>Pin 2 is connected to GND (from schematic)</li><li>Net CRT_CLK connects to CPU1 pin BC1 (VGA_DDCCLK) (from schematic)</li><li>This resistor acts as a pull-down on the VGA DDC clock line (reasoning)</li><li>DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning)</li><li>I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning)</li><li>Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning)</li><li>If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning)</li><li>If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning)</li><li>The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)</li></ul></details> | | 2 | 2 | GND | ❌ | <details><summary>Pull-down resistor on VGA DDC clock line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="69.43,39.19,76.93,46.69" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net CRT_CLK (from schematic)</li><li>Pin 2 is connected to GND (from schematic)</li><li>Net CRT_CLK connects to CPU1 pin BC1 (VGA_DDCCLK) (from schematic)</li><li>This resistor acts as a pull-down on the VGA DDC clock line (reasoning)</li><li>DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning)</li><li>I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning)</li><li>Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning)</li><li>If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning)</li><li>If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning)</li><li>The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)</li></ul></details> | </details> <details> <summary>R213 - 150 ohm 1% 1/16W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002631) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | MCSI_RCOMP | ✅ | 150 ohm resistor connected between CPU1 pin P14 (RESERVED_P14/MCSI_RCOMP) and GND, providing compensation for MIPI CSI interface. | | 2 | 2 | GND | ✅ | 150 ohm resistor connected between CPU1 pin P14 (RESERVED_P14/MCSI_RCOMP) and GND, providing compensation for MIPI CSI interface. | </details> <details> <summary>R41 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0-ohm resistor connecting CPU1 RESERVED_VSS1 pin to ground, providing a separate ground connection for debugging and measurement. | | 2 | 2 | $3N589 | ✅ | 0-ohm resistor connecting CPU1 RESERVED_VSS1 pin to ground, providing a separate ground connection for debugging and measurement. | </details> <details> <summary>R42 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0-ohm resistor connecting CPU1 RESERVED_VSS0 pin to ground, providing a separate ground connection for debugging and measurement. | | 2 | 2 | $3N579 | ✅ | 0-ohm resistor connecting CPU1 RESERVED_VSS0 pin to ground, providing a separate ground connection for debugging and measurement. | </details> <details> <summary>R43 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $3N554 | ✅ | 0-ohm resistor connecting CPU1 RESERVED_VSS3 pin to ground, providing a separate ground connection for debugging and measurement. | | 2 | 2 | GND | ✅ | 0-ohm resistor connecting CPU1 RESERVED_VSS3 pin to ground, providing a separate ground connection for debugging and measurement. | </details> <details> <summary>R46 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $3N552 | ✅ | 0-ohm resistor connecting CPU1 RESERVED_VSS2 pin to ground, providing a separate ground connection for debugging and measurement. | | 2 | 2 | GND | ✅ | 0-ohm resistor connecting CPU1 RESERVED_VSS2 pin to ground, providing a separate ground connection for debugging and measurement. | </details> <details> <summary>R257 - 2.2K ohm 1% 1/10W 0402 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDI1_DDCDAT | ❌ | <details><summary>Connected to DDI1_DDCDATA (CPU1 pin P30) with pull-down to ground. This implements an incorrect method for disabling the DDI1 interface - I2C data lines should not have pull-down resistors.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="64.43,26.26,71.93,33.76" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net DDI1_DDCDAT (from schematic)</li><li>Net DDI1_DDCDAT connects to CPU1 pin P30 (DDI1_DDCDATA) (from schematic)</li><li>R257 pin 2 connects to GND, making this a pull-down resistor (from schematic)</li><li>DDI1_DDCDATA is the Display Data Channel data line for Display Port 1, which uses I2C protocol (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</li><li>Other DDI1 pins are grounded: G30 (DDI1_DDCCLK) and K30 (DDI1_HPD) connect directly to GND (from schematic)</li><li>Schematic note 'Bay Trail-M Remove eDP Port' indicates DDI1 is intentionally disabled (from schematic)</li><li>I2C interfaces require pull-up resistors on clock and data lines for proper operation, not pull-down resistors (reasoning)</li><li>A pull-down resistor on an I2C data line prevents proper I2C communication (reasoning)</li><li>The datasheet recommends that unused I/O signals should be tri-stated (output driver disabled) and input receiver disabled through software configuration (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf">140-0004628</a>)</li><li>Using external pull-down resistors is not the recommended method for disabling unused display ports per the datasheet (reasoning)</li><li>If the port is properly disabled in software with tri-stated pins, external resistors are unnecessary (reasoning)</li><li>The correct approach is to configure the pins as tri-stated in software and leave them unconnected or with appropriate termination per datasheet recommendations (reasoning)</li></ul></details> | | 2 | 2 | GND | ✅ | Correctly connected to ground. | </details> <details> <summary>R102 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Resistor pin 1 correctly connected to GND to provide pull-down function. | | 2 | 2 | GPIO_NC13 | ✅ | Resistor pin 2 correctly connected to GPIO_NC13 net, providing 10K pull-down for CPU1 pin A29. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | C24 | ~PROCHOT | VR_HOT_L | ✅ | PROCHOT thermal alert signal with 73.2Ω series resistor to 1.0V supply, configured for bidirectional operation. | | N34 | RESERVED_N34 | | ✅ | Reserved pin with no connection shown on this schematic page. | | P34 | RESERVED_P34 | | ✅ | Reserved pin with no connection shown on this schematic page. | | BA12 | SATA_GP0 | SATA_GP0 | ✅ | SATA general purpose I/O 0, correctly pulled down with 10KΩ resistor. | | BA16 | SATA_RXN_1 | SATA1_RXN | ✅ | SATA port 1 receive negative signal, correctly AC-coupled for mSATA interface. | | BA18 | SD2_CLK | | ✅ | SD2 interface clock signal, no connection shown on this page. | | BA20 | SD2_D2 | | ✅ | SD2 interface data bit 2, no connection shown on this page. | | BA24 | ~MMC1_RST | | ✅ | eMMC reset signal, no connection shown on this page. | | BA26 | SD3_D3 | SD3_D3 | ✅ | SD card data bit 3, no connection shown on this page. | | BA30 | LPE_I2S2_FRM | LPE_I2S_FRM | ✅ | LPE I2S frame sync signal with 10KΩ pullup, used for audio interface. | | BB3 | RESERVED_BB3 | | ✅ | Reserved pin with no connection shown on this schematic page. | | BB4 | RESERVED_BB4 | | ✅ | Reserved pin with no connection shown on this schematic page. | | BB5 | RESERVED_VSS6 | RESERVED_VSS6 | ✅ | Reserved VSS pin connected to ground through 0Ω resistor, platform-specific configuration. | | BB7 | RESERVED_VSS7 | RESERVED_VSS7 | ✅ | Reserved VSS pin connected to ground through 0Ω resistor, platform-specific configuration. | | BB10 | RESERVED_VSS4 | ICLK_SATA_TERMP | ✅ | Reserved VSS pin connected to ground through 0Ω resistor via ICLK_SATA_TERMP net, Bay Trail-I specific configuration. | | BC10 | RESERVED_VSS5 | ICLK_SATA_TERMN | ✅ | Reserved VSS pin connected to ground through 0Ω resistor via ICLK_SATA_TERMN net, Bay Trail-I specific configuration. | | BC18 | SD2_CMD | | ✅ | SD2 interface command signal, no connection shown on this page. | | BC24 | SD3_CD# | SD3_CD# | ✅ | SD card detect signal connected to write protect pin via 0Ω resistor, platform-specific configuration. | | BC30 | LPE_I2S2_DATAOUT | LPE_I2S_DATOUT | ✅ | LPE I2S data output signal with optional pulldown and strap resistor, used for hardware configuration. | | BD5 | SD3_WP_BD5 | SD3_WP | ✅ | SD card write protect signal connected to card detect via 0Ω resistor, Bay Trail-I specific configuration. | | BD7 | ~PCIE_CLKREQ_1 | CLKREQ1_B | ✅ | PCIe clock request 1 signal with 10KΩ pullup to 1.8V, correctly configured. | | BD10 | SATA_TXP1 | SATA1_TXP | ✅ | SATA port 1 transmit positive signal, correctly AC-coupled for mSATA interface. | | BD18 | ~SD2_D3_CD | | ✅ | SD2 interface data bit 3 / card detect signal, no connection shown on this page. | | BD20 | SD2_D1 | | ✅ | SD2 interface data bit 1, no connection shown on this page. | | BD22 | ~SD3_PWREN | /SD3+PWREN | ✅ | SD card power enable signal connected to test point, no active connection shown. | | BD26 | SD3_D1 | SD3_D1 | ✅ | SD card data bit 1, no connection shown on this page. | | BD28 | LPE_I2S2_DATAIN | LPE_I2S_DATIN | ✅ | LPE I2S data input signal, no connection shown on this page. | | BE3 | ~PCIE_CLKREQ_3 | mPCIe_CLKREQ3_B | ✅ | PCIe clock request 3 signal with 10KΩ pullup to 1.8V for mPCIe slot, correctly configured. | | BF6 | SATA_TXP_0 | SATA0_TXP | ✅ | SATA port 0 transmit positive signal, correctly AC-coupled to SATA connector. | | BF10 | SATA_TXN_1 | SATA1_TXN | ✅ | SATA port 1 transmit negative signal, correctly AC-coupled for mSATA interface. | | BF20 | HDA_LPE_RCOMP | HDA_RCOMP | ✅ | HD Audio / LPE compensation resistor, correctly connected to 49.9Ω resistor to ground. | | BF22 | SD3_1P8EN | SD3_1P8EN | ✅ | SD card 1.8V enable signal connected to test point, no active connection shown. | | BF26 | SD3_RCOMP | SD3_RCOMP | ✅ | SD card compensation resistor, correctly connected to 49.9Ω resistor to ground. | | BF28 | LPE_I2S2_CLK | LPE_I2S_CLK | ✅ | LPE I2S clock signal with 10KΩ pullup, used for audio interface. | | BG3 | ~PCIE_CLKREQ_0 | CLKREQ0_B | ✅ | PCIe clock request 0 signal with 10KΩ pullup to 1.8V, correctly configured. | | BG5 | ~PCIE_CLKREQ_2 | LAN_CLKREQ2_B | ✅ | PCIe clock request 2 signal with 10KΩ pullup to 1.8V for LAN controller, correctly configured. | | BG7 | SATA_TXN_0 | SATA0_TXN | ✅ | SATA port 0 transmit negative signal, correctly AC-coupled to SATA connector. | | BG18 | GPIO_S0_SC_15 | | ✅ | General purpose I/O pin, no connection shown on this page. | | BG19 | HDA_SDI0 | | ✅ | HD Audio serial data input 0, no connection shown on this page. | | BG20 | HDA_SDO | | ✅ | HD Audio serial data output, no connection shown on this page. | | BG21 | HDA_SDI1 | | ✅ | HD Audio serial data input 1, no connection shown on this page. | | BG22 | ~HDA_RST | | ✅ | HD Audio reset signal, no connection shown on this page. | | BH18 | GPIO_S0_SC_14 | | ✅ | General purpose I/O pin, no connection shown on this page. | | BH20 | HDA_SYNC | | ✅ | HD Audio sync signal, no connection shown on this page. | | AK7 | RESERVED_AK7 | | ✅ | Reserved pin with no connection shown on this schematic page. | | AK9 | RESERVED_AK9 | | ✅ | Reserved pin with no connection shown on this schematic page. | | BJ21 | HDA_CLK | | ✅ | HD Audio clock signal, no connection shown on this page. | | AP4 | PCIE_TXN_3 | mPCIE_TX_N | ✅ | PCIe lane 3 transmit negative signal for mPCIe slot, no connection shown on this page. | | AP6 | PCIE_TXP_3 | mPCIE_TX_P | ✅ | PCIe lane 3 transmit positive signal for mPCIe slot, no connection shown on this page. | | AP7 | PCIE_RXN_3 | mPCIE_RX_N | ✅ | PCIe lane 3 receive negative signal for mPCIe slot, no connection shown on this page. | | AP9 | PCIE_RXP_3 | mPCIE_RX_P | ✅ | PCIe lane 3 receive positive signal for mPCIe slot, no connection shown on this page. | | AP10 | PCIE_RXN_2 | PCIE_RXN2 | ✅ | PCIe lane 2 receive negative signal for LAN controller, no connection shown on this page. | | AP12 | PCIE_RXP_2 | PCIE_RXP2 | ✅ | PCIe lane 2 receive positive signal for LAN controller, no connection shown on this page. | | AP13 | PCIE_RCOMP_N_AP13_AP13 | PCIE_RCOMP_N | ✅ | PCIe compensation resistor negative terminal, correctly connected to 402Ω resistor. | | AP14 | PCIE_RCOMP_P_AP14_AP14 | PCIE_RCOMP_P | ✅ | PCIe compensation resistor positive terminal, correctly connected to 402Ω resistor. | | AT6 | PCIE_TXN_2 | PCIE_TXN2 | ✅ | PCIe lane 2 transmit negative signal for LAN controller, no connection shown on this page. | | AT7 | PCIE_TXP_2 | PCIE_TXP2 | ✅ | PCIe lane 2 transmit positive signal for LAN controller, no connection shown on this page. | | AT9 | PCIE_RXN_1 | | ✅ | PCIe lane 1 receive negative signal, no connection shown on this page. | | AT10 | PCIE_RXP_1 | | ✅ | PCIe lane 1 receive positive signal, no connection shown on this page. | | AT13 | PCIE_RXN_0 | | ✅ | PCIe lane 0 receive negative signal, no connection shown on this page. | | AT14 | PCIE_RXP_0 | | ✅ | PCIe lane 0 receive positive signal, no connection shown on this page. | | AT18 | SATA_RCOMP_N_AT18 | SATA_RCOMP_N | ✅ | SATA compensation resistor negative terminal, correctly connected to 402Ω resistor. | | AT20 | MMC1_D3 | | ✅ | eMMC data bit 3, no connection shown on this page. | | AT22 | MMC1_CLK | | ✅ | eMMC clock signal, no connection shown on this page. | | AT26 | MMC1_D6 | | ✅ | eMMC data bit 6, no connection shown on this page. | | AT28 | SD3_D0 | SD3_D0 | ✅ | SD card data bit 0, no connection shown on this page. | | AU16 | SATA_RXP_0 | SATA0_RXP | ✅ | SATA port 0 receive positive signal, correctly AC-coupled to SATA connector. | | AU18 | SATA_RCOMP_P_AU18 | SATA_RCOMP_P | ✅ | SATA compensation resistor positive terminal, correctly connected to 402Ω resistor. | | AU20 | MMC1_D7 | | ✅ | eMMC data bit 7, no connection shown on this page. | | AU22 | MMC1_D1 | | ✅ | eMMC data bit 1, no connection shown on this page. | | AU26 | MMC1_D5 | | ✅ | eMMC data bit 5, no connection shown on this page. | | AU28 | SD3_D2 | SD3_D2 | ✅ | SD card data bit 2, no connection shown on this page. | | AV4 | PCIE_TXN_1 | | ✅ | PCIe lane 1 transmit negative signal, no connection shown on this page. | | AV6 | PCIE_TXP_1 | | ✅ | PCIe lane 1 transmit positive signal, no connection shown on this page. | | AV9 | RESERVED_AV9 | | ✅ | Reserved pin with no connection shown on this schematic page. | | AV10 | RESERVED_AV10 | | ✅ | Reserved pin with no connection shown on this schematic page. | | AV16 | SATA_RXN_0 | SATA0_RXN | ✅ | SATA port 0 receive negative signal, correctly AC-coupled to SATA connector. | | AV20 | MMC1_D0 | | ✅ | eMMC data bit 0, no connection shown on this page. | | AV22 | MMC1_D2 | | ✅ | eMMC data bit 2, no connection shown on this page. | | AV26 | MMC1_CMD | | ✅ | eMMC command signal, no connection shown on this page. | | AV28 | SD3_CMD | SD3_CMD | ✅ | SD card command signal, no connection shown on this page. | | AY6 | PCIE_TXN_0 | | ✅ | PCIe lane 0 transmit negative signal, no connection shown on this page. | | AY7 | PCIE_TXP_0 | | ✅ | PCIe lane 0 transmit positive signal, no connection shown on this page. | | AY12 | ~SATA_LED | SATA_LED_B | ✅ | SATA LED output signal, correctly connected through current-limiting resistor to LED jumper. | | AY14 | SATA_GP1 | SATA_GP1 | ✅ | SATA general purpose I/O 1, correctly pulled down with 10KΩ resistor. | | AY16 | SATA_RXP_1 | SATA1_RXP | ✅ | SATA port 1 receive positive signal, correctly AC-coupled for mSATA interface. | | AY18 | MMC1_RCOMP | MMC1_RCOMP | ✅ | eMMC compensation resistor, correctly connected to 49.9Ω resistor to ground. | | AY20 | SD2_D0 | | ✅ | SD2 interface data bit 0, no connection shown on this page. | | AY24 | MMC1_D4 | | ✅ | eMMC data bit 4, no connection shown on this page. | | AY26 | SD3_CLK | SD3_CLK | ✅ | SD card clock signal, no connection shown on this page. | </details> <details> <summary>J3 - HDR_7POS_SER_GOLD_SATA_R/A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.molex.com/pdm_docs/ps/PS-67490-001.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0003610) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND net, providing signal return path for SATA differential pairs. | | 2 | 2 | SATA0_TXP_C | ✅ | Transmit positive signal correctly connected through AC coupling capacitor C10 to CPU SATA0_TXP output. | | 3 | 3 | SATA0_TXN_C | ✅ | Transmit negative signal correctly connected through AC coupling capacitor C11 to CPU SATA0_TXN output. | | 4 | 4 | GND | ✅ | Ground pin correctly connected to GND net, providing isolation between TX and RX differential pairs. | | 5 | 5 | SATA0_RXN_C | ✅ | Receive negative signal correctly connected through AC coupling capacitor C12 to CPU SATA0_RXN input. | | 6 | 6 | SATA0_RXP_C | ✅ | Receive positive signal correctly connected through AC coupling capacitor C13 to CPU SATA0_RXP input. | | 7 | 7 | GND | ✅ | Ground pin correctly connected to GND net, completing the ground structure for the SATA interface. | | 8 | MH1 | GND_EARTH | ✅ | Mounting hole correctly connected to GND_EARTH for chassis grounding and EMI shielding. | | 9 | MH2 | GND_EARTH | ✅ | Mounting hole correctly connected to GND_EARTH for chassis grounding and EMI shielding. | </details> <details> <summary>C10 - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_TXP_C | ✅ | AC coupling capacitor correctly placed on SATA transmit positive line between CPU and connector. | | 2 | 2 | SATA0_TXP | ✅ | AC coupling capacitor correctly placed on SATA transmit positive line between CPU and connector. | </details> <details> <summary>C11 - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_TXN_C | ✅ | AC coupling capacitor correctly placed on SATA transmit negative line between CPU and connector. | | 2 | 2 | SATA0_TXN | ✅ | AC coupling capacitor correctly placed on SATA transmit negative line between CPU and connector. | </details> <details> <summary>C12 - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_RXN_C | ✅ | AC coupling capacitor correctly placed on SATA receive negative line between connector and CPU. | | 2 | 2 | SATA0_RXN | ✅ | AC coupling capacitor correctly placed on SATA receive negative line between connector and CPU. | </details> <details> <summary>C13 - 0.01uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA0_RXP_C | ✅ | AC coupling capacitor correctly placed on SATA receive positive line between connector and CPU. | | 2 | 2 | SATA0_RXP | ✅ | AC coupling capacitor correctly placed on SATA receive positive line between connector and CPU. | </details> <details> <summary>R239 - 402 ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA_RCOMP_N | ✅ | RCOMP resistor correctly connected between SATA_RCOMP_P and SATA_RCOMP_N for PHY impedance calibration. | | 2 | 2 | SATA_RCOMP_P | ✅ | RCOMP resistor correctly connected between SATA_RCOMP_P and SATA_RCOMP_N for PHY impedance calibration. | </details> <details> <summary>C148 - 8200pF 10% 1KV 1808 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0004408) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND_EARTH | ✅ | NOVA safety capacitor marked DNI, providing optional isolation between chassis ground and signal ground for EMI/safety compliance. | | 2 | 2 | GND | ✅ | NOVA safety capacitor marked DNI, providing optional isolation between chassis ground and signal ground for EMI/safety compliance. | </details> <details> <summary>C177 - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_N | ✅ | AC coupling capacitor for SATA1 receive negative differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component. | | 2 | 2 | SATA1_RXN | ✅ | AC coupling capacitor for SATA1 receive negative differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component. | </details> <details> <summary>C179 - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_P | ✅ | AC coupling capacitor for SATA1 transmit positive differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component. | | 2 | 2 | SATA1_TXP | ✅ | AC coupling capacitor for SATA1 transmit positive differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component. | </details> <details> <summary>C178 - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_RX_P | ✅ | AC coupling capacitor for SATA1 receive positive differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component. | | 2 | 2 | SATA1_RXP | ✅ | AC coupling capacitor for SATA1 receive positive differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component. | </details> <details> <summary>C180 - 123-0001038 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001038) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mSATA_TX_N | ✅ | AC coupling capacitor for SATA1 transmit negative differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component. | | 2 | 2 | SATA1_TXN | ✅ | AC coupling capacitor for SATA1 transmit negative differential signal between CPU and mSATA interface. The capacitor blocks DC while passing the high-speed AC signal component. | </details> <details> <summary>R179 - 110-0001960 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001960) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SATA_LED_B | ✅ | Connected to SATA_LED_B net from CPU1 pin AY12, which is the active-low SATA LED output signal. | | 2 | 2 | SATA_LED_R | ✅ | Connected to SATA_LED_R net, which routes to jumper J6 pin 2 for optional pull-up configuration. | </details> <details> <summary>J6 - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S supply rail, providing 1.8V pull-up voltage when jumper is installed. | | 2 | 2 | SATA_LED_R | ✅ | Connected to SATA_LED_R net from R179, completing the jumper-selectable pull-up circuit. | </details> <details> <summary>R220 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the ground reference for the pull-down resistor. | | 2 | 2 | SATA_GP0 | ✅ | Connected to SATA_GP0 net from CPU1 pin BA12, providing pull-down for SATA general purpose pin. | </details> <details> <summary>R221 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, providing the ground reference for the pull-down resistor. | | 2 | 2 | SATA_GP1 | ✅ | Connected to SATA_GP1 net from CPU1 pin AY14, providing pull-down for SATA general purpose pin. | </details> <details> <summary>R218 - 110-0004476 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004476) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PCIE_RCOMP_P | ✅ | 402 ohm resistor connected between PCIE_RCOMP_P (pin 1) and PCIE_RCOMP_N (pin 2), serving as the PCIe compensation resistor for the CPU. | | 2 | 2 | PCIE_RCOMP_N | ✅ | 402 ohm resistor connected between PCIE_RCOMP_P (pin 1) and PCIE_RCOMP_N (pin 2), serving as the PCIe compensation resistor for the CPU. | </details> <details> <summary>R72 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS6 | ✅ | 0 ohm resistor connecting RESERVED_VSS6 (pin 1) to GND (pin 2), providing a ground connection for a reserved VSS pin on the CPU. | | 2 | 2 | GND | ✅ | 0 ohm resistor connecting RESERVED_VSS6 (pin 1) to GND (pin 2), providing a ground connection for a reserved VSS pin on the CPU. | </details> <details> <summary>R192 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | RESERVED_VSS7 | ✅ | 0 ohm resistor connecting RESERVED_VSS7 (pin 1) to GND (pin 2), providing a ground connection for another reserved VSS pin on the CPU. | | 2 | 2 | GND | ✅ | 0 ohm resistor connecting RESERVED_VSS7 (pin 1) to GND (pin 2), providing a ground connection for another reserved VSS pin on the CPU. | </details> <details> <summary>R73 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0 ohm resistor connecting GND (pin 1) to ICLK_SATA_TERMP (pin 2), providing termination for the SATA interface on the CPU. | | 2 | 2 | ICLK_SATA_TERMP | ✅ | 0 ohm resistor connecting GND (pin 1) to ICLK_SATA_TERMP (pin 2), providing termination for the SATA interface on the CPU. | </details> <details> <summary>R74 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 0 ohm resistor connecting GND (pin 1) to ICLK_SATA_TERMN (pin 2), providing termination for the SATA interface on the CPU. | | 2 | 2 | ICLK_SATA_TERMN | ✅ | 0 ohm resistor connecting GND (pin 1) to ICLK_SATA_TERMN (pin 2), providing termination for the SATA interface on the CPU. | </details> <details> <summary>R190 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ1_B | ✅ | Connected to CLKREQ1_B signal from CPU1 pin BD7. This is a pull-up resistor for the PCIe clock request signal. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply rail, providing pull-up voltage for the CLKREQ1_B signal. | </details> <details> <summary>R2 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | mPCIe_CLKREQ3_B | ✅ | Connected to mPCIe_CLKREQ3_B signal from CPU1 pin BE3. This is a pull-up resistor for the PCIe clock request signal used by the mini-PCIe slot. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply rail, providing pull-up voltage for the mPCIe_CLKREQ3_B signal. | </details> <details> <summary>R191 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | CLKREQ0_B | ✅ | Connected to CLKREQ0_B signal from CPU1 pin BG3. This is a pull-up resistor for the PCIe clock request signal. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply rail, providing pull-up voltage for the CLKREQ0_B signal. | </details> <details> <summary>R71 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_CLKREQ2_B | ✅ | Connected to LAN_CLKREQ2_B signal from CPU1 pin BG5. This is a pull-up resistor for the PCIe clock request signal used by the LAN controller. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply rail, providing pull-up voltage for the LAN_CLKREQ2_B signal. | </details> <details> <summary>R354 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SD3_WP | ❌ | <details><summary>This 0-ohm resistor ties SD3_WP (write protect) to SD3_CD# (card detect), which is unusual and likely incorrect. These signals should typically be independent to allow separate detection of card presence and write protection status.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="be0367a8ed73ec923161" diff-visibility="full" variant="default" view-coords="38.52,43.90,46.02,51.40" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net SD3_WP (from schematic)</li><li>Pin 2 is connected to net SD3_CD# (from schematic)</li><li>SD3_WP connects to CPU1 pin BD5 labeled SD3_WP_BD5 (from schematic)</li><li>SD3_CD# connects to CPU1 pin BC24 labeled SD3_CD# (from schematic)</li><li>R354 is a 0-ohm resistor that directly connects these two signals together (from schematic)</li><li>SD3_WP is typically an input to detect if an SD card's write protect switch is enabled, with active-low polarity where low indicates write-protected (reasoning)</li><li>SD3_CD# is typically an active-low input to detect if an SD card is physically present in the slot, where low indicates card present (reasoning)</li><li>Tying these signals together forces them to always have the same logic level, preventing independent detection of card presence and write protection status (reasoning)</li><li>With both signals tied together, when a card is present CD# goes low, which also forces WP low, indicating the card is write-protected regardless of the actual WP switch state (reasoning)</li><li>In typical SD card interface designs, card detect and write protect are separate signals with independent functionality (reasoning)</li><li>If write protect detection is not needed, the WP pin should typically be pulled to a fixed state such as high for write-enabled, rather than tied to card detect (reasoning)</li><li>This connection could cause all inserted cards to appear write-protected, preventing write operations even when the card's WP switch is off (reasoning)</li><li>Recommendation: Separate these signals and either connect WP to its own detection circuit or pull it to an appropriate fixed state if write protect detection is not required (reasoning)</li></ul></details> | | 2 | 2 | SD3_CD# | ❌ | <details><summary>This 0-ohm resistor ties SD3_WP (write protect) to SD3_CD# (card detect), which is unusual and likely incorrect. These signals should typically be independent to allow separate detection of card presence and write protection status.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="be0367a8ed73ec923161" diff-visibility="full" variant="default" view-coords="39.43,43.90,46.93,51.40" aspect-ratio="1.29" } <ul><li>Pin 1 is connected to net SD3_WP (from schematic)</li><li>Pin 2 is connected to net SD3_CD# (from schematic)</li><li>SD3_WP connects to CPU1 pin BD5 labeled SD3_WP_BD5 (from schematic)</li><li>SD3_CD# connects to CPU1 pin BC24 labeled SD3_CD# (from schematic)</li><li>R354 is a 0-ohm resistor that directly connects these two signals together (from schematic)</li><li>SD3_WP is typically an input to detect if an SD card's write protect switch is enabled, with active-low polarity where low indicates write-protected (reasoning)</li><li>SD3_CD# is typically an active-low input to detect if an SD card is physically present in the slot, where low indicates card present (reasoning)</li><li>Tying these signals together forces them to always have the same logic level, preventing independent detection of card presence and write protection status (reasoning)</li><li>With both signals tied together, when a card is present CD# goes low, which also forces WP low, indicating the card is write-protected regardless of the actual WP switch state (reasoning)</li><li>In typical SD card interface designs, card detect and write protect are separate signals with independent functionality (reasoning)</li><li>If write protect detection is not needed, the WP pin should typically be pulled to a fixed state such as high for write-enabled, rather than tied to card detect (reasoning)</li><li>This connection could cause all inserted cards to appear write-protected, preventing write operations even when the card's WP switch is off (reasoning)</li><li>Recommendation: Separate these signals and either connect WP to its own detection circuit or pull it to an appropriate fixed state if write protect detection is not required (reasoning)</li></ul></details> | </details> <details> <summary>R240 - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, providing the ground reference for the RCOMP resistor. | | 2 | 2 | MMC1_RCOMP | ✅ | Pin 2 is connected to MMC1_RCOMP on the CPU, providing impedance calibration reference for the MMC1 interface. | </details> <details> <summary>R242 - 110-0003059 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDA_RCOMP | ✅ | Connected to HDA_LPE_RCOMP pin (BF20) of CPU1. This provides impedance compensation for the High Definition Audio interface. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the HDA RCOMP resistor. | </details> <details> <summary>R233 - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP1 | ✅ | DNI 1K pull-down resistor for BOM_OP1 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'. | | 2 | 2 | GND | ✅ | DNI 1K pull-down resistor for BOM_OP1 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'. | </details> <details> <summary>R211 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 10K pull-up resistor for BOM_OP1 hardware identification bit. Pulls BOM_OP1 to logic HIGH as part of '1001' hardware ID pattern. | | 2 | 2 | BOM_OP1 | ✅ | 10K pull-up resistor for BOM_OP1 hardware identification bit. Pulls BOM_OP1 to logic HIGH as part of '1001' hardware ID pattern. | </details> <details> <summary>R208 - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP2 | ✅ | 1K pull-down resistor for BOM_OP2 hardware identification bit. Pulls BOM_OP2 to logic LOW as part of '1001' hardware ID pattern. | | 2 | 2 | GND | ✅ | 1K pull-down resistor for BOM_OP2 hardware identification bit. Pulls BOM_OP2 to logic LOW as part of '1001' hardware ID pattern. | </details> <details> <summary>R209 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | DNI 10K pull-up resistor for BOM_OP2 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'. | | 2 | 2 | BOM_OP2 | ✅ | DNI 10K pull-up resistor for BOM_OP2 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'. | </details> <details> <summary>R234 - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP3 | ✅ | 1K pull-down resistor for BOM_OP3 hardware identification bit. Pulls BOM_OP3 to logic LOW as part of '1001' hardware ID pattern. | | 2 | 2 | GND | ✅ | 1K pull-down resistor for BOM_OP3 hardware identification bit. Pulls BOM_OP3 to logic LOW as part of '1001' hardware ID pattern. | </details> <details> <summary>R210 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | DNI 10K pull-up resistor for BOM_OP3 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'. | | 2 | 2 | BOM_OP3 | ✅ | DNI 10K pull-up resistor for BOM_OP3 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'. | </details> <details> <summary>R401 - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BOM_OP4 | ✅ | DNI 1K pull-down resistor for BOM_OP4 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'. | | 2 | 2 | GND | ✅ | DNI 1K pull-down resistor for BOM_OP4 hardware identification bit. Part of a hardware ID scheme producing pattern '1001'. | </details> <details> <summary>R400 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 10K pull-up resistor for BOM_OP4 hardware identification bit. Pulls BOM_OP4 to logic HIGH as part of '1001' hardware ID pattern. | | 2 | 2 | BOM_OP4 | ✅ | 10K pull-up resistor for BOM_OP4 hardware identification bit. Pulls BOM_OP4 to logic HIGH as part of '1001' hardware ID pattern. | </details> <details> <summary>R259 - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_10_UNLOCK | ✅ | Pin 1 connects to GPIO_S5_10_UNLOCK net. This pin is part of a series resistor used for hardware strap isolation. | | 2 | 2 | LPE_I2S_DATOUT | ✅ | Pin 2 connects to LPE_I2S_DATOUT net, which connects to CPU1 pin BC30 (LPE_I2S2_DATAOUT). This is a hardware strap pin for Security Flash Descriptors configuration. | </details> <details> <summary>R268 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPE_I2S_FRM | ✅ | Pin 1 connects to LPE_I2S_FRM net, which connects to CPU1 pin BA30 (LPE_I2S2_FRM). This is a hardware strap pin for BIOS Boot Selection. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S (1.8V supply). This pull-up resistor sets the BIOS Boot Selection strap to SPI mode. | </details> <details> <summary>R260 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPE_I2S_DATOUT | ✅ | Pin 1 connects to LPE_I2S_DATOUT net. This is part of an optional pull-down resistor marked DNI. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND. This is part of an optional pull-down resistor marked DNI. | </details> <details> <summary>R255 - 110-0004474 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004474) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR_HOT_L | ✅ | Pin 1 connects to VR_HOT_L net, which is the PROCHOT (processor hot) signal from CPU1 pin C24. This is an active-low thermal management signal. | | 2 | 2 | +V1P0S | ✅ | Pin 2 connects to +V1P0S (1.0V supply), providing a pull-up for the PROCHOT signal. The 73.2 ohm value is unusually low for a typical pull-up but appears intentional. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A9 | ILB_RTC_X2 | BRTCX2 | ✅ | ILB_RTC_X2 is correctly connected to the 32.768 kHz RTC crystal output with appropriate load capacitance and feedback resistor. | | A13 | GPIO_S5_9 | SOC_USB_HOST_EN1 | ✅ | GPIO_S5_9 is correctly connected to SOC_USB_HOST_EN1 for USB host port enable control. | | A17 | GPIO_S5_3 | mPCIE_WAKEB | ✅ | GPIO_S5_3 is correctly connected to mPCIE_WAKEB with optional pull-up resistor for PCIe wake signaling. | | A21 | PCU_SPI_MOSI | SOC_SPI_MOSI | ✅ | PCU_SPI_MOSI is correctly connected through a 0-ohm series resistor to the SPI flash interface. | | A25 | SVID_DATA | SVID_DATA | ✅ | SVID_DATA is correctly connected through a 16.9 ohm series resistor for impedance matching in the IMVP7 voltage regulator interface. | | B7 | PMC_CORE_PWROK | PMC_CORE_PWROK | ✅ | PMC_CORE_PWROK is correctly connected through a 0-ohm resistor to SYS_PWRGD with optional decoupling capacitor. | | B8 | ILB_RTC_EXTPAD | BVCCRTC_EXTPAD | ✅ | ILB_RTC_EXTPAD is correctly connected with decoupling capacitor for RTC power supply. | | B10 | ~PMC_RSMRST | PMC_RSMRST | ✅ | PMC_RSMRST# is correctly connected with an RC network for signal conditioning. The 10us timing requirement is met by the external power management controller, not by this local RC network. | | B14 | GPIO_S5_6 | BOM_OP2 | ✅ | GPIO_S5_6 is correctly connected to BOM_OP2 for board configuration options. | | B16 | GPIO_S5_1 | SOC_GPIO_S5_1 | ✅ | GPIO_S5_1 is correctly connected to SOC_GPIO_S5_1 for general purpose I/O. | | B18 | GPIO_S5_0 | SOC_GPIO_S5_0 | ✅ | GPIO_S5_0 is correctly connected to SOC_GPIO_S5_0 for general purpose I/O. | | B22 | PCU_SPI_MISO | SOC_SPI_MISO | ✅ | PCU_SPI_MISO is correctly connected through a 0-ohm series resistor to the SPI flash interface. | | B24 | ~SVID_ALERT | SVID_ALERT | ✅ | SVID_ALERT is correctly connected through series resistor and pull-up for the IMVP7 voltage regulator alert signal. | | C9 | ILB_RTC_X1 | BRTCX1 | ✅ | ILB_RTC_X1 is correctly connected to the 32.768 kHz RTC crystal input with appropriate load capacitance and feedback resistor. | | C11 | ~ILB_RTC_TEST | ILB_RTC_TESTB | ✅ | ILB_RTC_TEST is correctly connected to ILB_RTC_TESTB for RTC test mode control. | | C12 | ~ILB_RTC_RST | RTCRST_L | ✅ | ILB_RTC_RST is correctly connected with pull-up resistor and decoupling capacitor for RTC reset functionality. | | C13 | GPIO_S5_8 | SOC_USB_HOST_EN0 | ✅ | GPIO_S5_8 is correctly connected to SOC_USB_HOST_EN0 for USB host port enable control. | | C15 | GPIO_S5_7 | BOM_OP3 | ✅ | GPIO_S5_7 is correctly connected to BOM_OP3 for board configuration options. | | C16 | GPIO_S5_5 | BOM_OP1 | ✅ | GPIO_S5_5 is correctly connected to BOM_OP1 for board configuration options. | | C17 | GPIO_S5_4 | BOM_OP4 | ✅ | GPIO_S5_4 is correctly connected to BOM_OP4 for board configuration options. | | C18 | GPIO_S5_2 | SOC_GPIO_S5_2 | ✅ | GPIO_S5_2 is correctly connected to SOC_GPIO_S5_2 for general purpose I/O. | | C19 | GPIO_S5_10 | GPIO_S5_10_UNLOCK | ✅ | GPIO_S5_10 is correctly connected to GPIO_S5_10_UNLOCK for general purpose I/O. | | C21 | ~PCU_SPI_CS_11 | SOC_SPI_CS1B | ✅ | PCU_SPI_CS_11 is correctly connected through a DNI 0-ohm resistor, indicating SPI CS1 is not used in this design. | | C22 | PCU_SPI_CLK | SOC_SPI_CLK | ✅ | PCU_SPI_CLK is correctly connected through a 0-ohm series resistor to the SPI flash interface with optional filtering capacitor. | | C23 | ~PCU_SPI_CS_00 | SOC_SPI_CS0B | ✅ | PCU_SPI_CS_00 is correctly connected through a 0-ohm series resistor to the SPI flash interface. | | C25 | SVID_CLK | SVID_CLK-R | ✅ | SVID_CLK is correctly connected to provide 25 MHz clock for the IMVP7 voltage regulator interface. | | D14 | TAP_TCK | XDP_H_TCK | ✅ | TAP_TCK is correctly connected to the JTAG test clock with 51 ohm pull-down termination. | | D18 | ~TAP_PRDY | XDP_H_PRDYB | ✅ | TAP_PRDY is correctly connected to the JTAG probe ready signal. | | D20 | PMC_ACPRESENT | PMC_ACPRESENT | ✅ | PMC_ACPRESENT is correctly connected with 2.2K pull-up resistor for AC power detection. | | D22 | ~PMC_SLP_S3 | PMC_SLP_S3_L | ✅ | PMC_SLP_S3 is correctly connected through level shifter U19 to translate from 1.8V to 3.3V domain. | | D26 | PMC_SUSPWRDNACK | SUSPWRDNACK | ✅ | PMC_SUSPWRDNACK is correctly connected with 10K pull-up resistor and test point. | | F12 | TAP_TDI | XDP_H_TDI | ✅ | TAP_TDI is correctly connected to the JTAG test data in with 51 ohm pull-up termination. | | F14 | TAP_TMS | XDP_H_TMS | ✅ | TAP_TMS is correctly connected to the JTAG test mode select with 51 ohm pull-up termination. | | F16 | ~TAP_PREQ | XDP_H_PREQB | ✅ | TAP_PREQ is correctly connected to the JTAG probe request signal. | | F18 | ~PMC_SLP_S0IX | PMC_SLP_S0IX | ✅ | PMC_SLP_S0IX is correctly connected with test point for monitoring S0ix sleep state. | | F20 | ~PMC_PLTRST | PMC_PLTRST_R_V1P8 | ✅ | PMC_PLTRST is correctly connected through level shifter U19 to translate from 1.8V to 3.3V domain. | | F22 | ~PMC_SLP_S4 | PMC_SLP_S4_L | ✅ | PMC_SLP_S4 is correctly connected through level shifter U19 to translate from 1.8V to 3.3V domain. | | F26 | ~PMC_WAKE_PCIE_0 | PMC_PCIE_WAKE_R | ✅ | PMC_WAKE_PCIE_0 is correctly connected through diode OR circuit with 1K pull-up for PCIe wake signaling. | | G12 | ~TAP_TRST | XDP_H_TRSTB | ✅ | TAP_TRST is correctly connected to the JTAG test reset with 51 ohm pull-down termination. | | G16 | TAP_TDO | XDP_H_TDO | ✅ | TAP_TDO is correctly connected to the JTAG test data out. | | G18 | ~PMC_SUS_STAT | LPCPD_L | ✅ | PMC_SUS_STAT is correctly connected with test point for monitoring suspend status. | | G24 | PMC_SUSCLK0_G24 | PMC_SUSCLK0 | ✅ | PMC_SUSCLK0_G24 is correctly connected through level shifter U19 with optional pull-up to translate suspend clock from 1.8V to 3.3V domain. | | J18 | GPIO_S5_25 | XDP_H_OBSDATA_A2 | ✅ | GPIO_S5_25 is correctly connected to XDP_H_OBSDATA_A2 for debug observation data. | | J20 | GPIO_S5_14 | GPIO_S514_J20 | ✅ | GPIO_S5_14 is correctly connected to GPIO_S514_J20 with 10K pull-up resistor. | | J24 | GPIO_S5_17 | GPIO_S5_17 | ✅ | GPIO_S5_17 is correctly connected with jumper to GND and 10K pull-up for configuration option. | | J26 | ~PMC_PWRBTN | PMC_PWRBTN | ✅ | PMC_PWRBTN is correctly connected through dual diode OR circuit for power button functionality. | | K18 | GPIO_S5_27 | EXP_GPIO1 | ✅ | GPIO_S5_27 is correctly connected to EXP_GPIO1 for expansion bus GPIO. | | K20 | GPIO_S5_28 | EXP_GPIO2 | ✅ | GPIO_S5_28 is correctly connected to EXP_GPIO2 for expansion bus GPIO. | | K24 | GPIO_S5_22 | GPIO_D2_LED_CTRL | ✅ | GPIO_S5_22 is correctly connected to GPIO_D2_LED_CTRL for LED control. | | K26 | ~PMC_BATLOW | PMC_BATLOW | ✅ | PMC_BATLOW is correctly connected with 20K pull-up resistor for battery low detection. | | M18 | GPIO_S5_26 | XDP_H_OBSDATA_A3 | ✅ | GPIO_S5_26 is correctly connected to XDP_H_OBSDATA_A3 for debug observation data. | | M20 | GPIO_S5_24 | XDP_H_OBSDATA_A1 | ✅ | GPIO_S5_24 is correctly connected to XDP_H_OBSDATA_A1 for debug observation data. | | M22 | GPIO_S5_29 | EXP_GPIO3 | ✅ | GPIO_S5_29 is correctly connected to EXP_GPIO3 for expansion bus GPIO. | | M24 | GPIO_S5_30 | EXP_GPIO4 | ✅ | GPIO_S5_30 is correctly connected to EXP_GPIO4 for expansion bus GPIO. | | N24 | GPIO_S5_23 | XDP_H_OBSDATA_A0 | ✅ | GPIO_S5_23 is correctly connected to XDP_H_OBSDATA_A0 for debug observation data. | | N26 | GPIO_RCOMP | GPIO_RCOMP | ✅ | GPIO_RCOMP is correctly connected to a 49.9 ohm compensation resistor to ground. | | BA28 | SIO_SPI_MISO | SOC_SIO_SPI_MISO | ✅ | SIO_SPI_MISO is correctly connected to SOC_SIO_SPI_MISO for SPI master in slave out. | | BA34 | ~SIO_UART1_RTS | SIO_UART1_RTSB | ✅ | SIO_UART1_RTS is correctly connected to SIO_UART1_RTSB for UART1 request to send flow control. | | AD9 | RESERVED_AD9 | | ✅ | Reserved pins are correctly left unconnected as specified by the datasheet. | | AD10 | RESERVED_AD10 | | ✅ | Reserved pins are correctly left unconnected as specified by the datasheet. | | AD12 | RESERVED_AD12 | | ✅ | Reserved pins are correctly left unconnected as specified by the datasheet. | | AD13 | ICLK_RCOMP | ICLK_RCOMP | ✅ | ICLK_RCOMP is correctly connected to a 47.5 ohm compensation resistor to ground for integrated clock operation. | | AD14 | ICLK_ICOMP | ICLK_ICOMP | ✅ | ICLK_ICOMP is correctly connected to a 4.02K ohm compensation resistor to ground for integrated clock operation. | | BD32 | ~SIO_UART2_RTS | | ✅ | SIO_UART2_RTS is correctly left unconnected as UART2 flow control is not used in this design. | | BD34 | SIO_UART2_TXD | SIO_UART2_TXD | ✅ | SIO_UART2_TXD is correctly connected for UART2 transmit data. | | AF4 | PCIE_CLKP_00 | | ✅ | PCIE_CLKP_00 and PCIE_CLKN_00 are correctly left unconnected as these PCIe clock outputs are not used in this design. | | AF6 | PCIE_CLKN_00 | | ✅ | PCIE_CLKP_00 and PCIE_CLKN_00 are correctly left unconnected as these PCIe clock outputs are not used in this design. | | AF7 | PCIE_CLKP_11 | | ✅ | PCIE_CLKP_11 and PCIE_CLKN_11 are correctly left unconnected as these PCIe clock outputs are not used in this design. | | AF9 | PCIE_CLKN_11 | | ✅ | PCIE_CLKP_11 and PCIE_CLKN_11 are correctly left unconnected as these PCIe clock outputs are not used in this design. | | BF32 | ~SIO_UART2_CTS | | ✅ | SIO_UART2_CTS is correctly left unconnected as UART2 flow control is not used in this design. | | BF34 | SIO_UART2_RXD | SIO_UART2_RXD | ✅ | SIO_UART2_RXD is correctly connected for UART2 receive data. | | BG9 | ~PMC_RSTBTN | PMC_RSTBTN | ✅ | PMC_RSTBTN is correctly connected to the reset button input. | | AH10 | ICLK_OSCOUT | XTAL25_OUT | ✅ | ICLK_OSCOUT is correctly connected to the 25 MHz crystal output with appropriate load capacitance and feedback resistor. | | AH12 | ICLK_OSCIN | XTAL25_IN | ✅ | ICLK_OSCIN is correctly connected to the 25 MHz crystal input with appropriate load capacitance and feedback resistor. | | BH4 | PMC_PLT_CLK_22 | | ✅ | PMC_PLT_CLK_22 is correctly left unconnected as this platform clock output is not used in this design. | | BH5 | PMC_PLT_CLK_11 | | ✅ | PMC_PLT_CLK_11 is correctly left unconnected as this platform clock output is not used in this design. | | BH6 | PMC_PLT_CLK_44 | | ✅ | PMC_PLT_CLK_44 is correctly left unconnected as this platform clock output is not used in this design. | | BH7 | PMC_PLT_CLK_00 | | ✅ | PMC_PLT_CLK_00 is correctly left unconnected as this platform clock output is not used in this design. | | BH8 | PMC_PLT_CLK_33 | I2S_MCLK | ✅ | PMC_PLT_CLK_33 is correctly connected to I2S_MCLK for audio master clock. | | AK4 | PCIE_CLKN_22 | PCIE_CLK-N2 | ✅ | PCIE_CLKN_22 and PCIE_CLKP_22 are correctly connected to provide 100 MHz differential clock for PCIe interface. | | AK6 | PCIE_CLKP_22 | PCIE_CLK-P2 | ✅ | PCIE_CLKN_22 and PCIE_CLKP_22 are correctly connected to provide 100 MHz differential clock for PCIe interface. | | BJ9 | PMC_PLT_CLK_55 | | ✅ | PMC_PLT_CLK_55 is correctly left unconnected as this platform clock output is not used in this design. | | AM4 | PCIE_CLKN_33 | mPCIE_REFCLK_N | ✅ | PCIE_CLKN_33 and PCIE_CLKP_33 are correctly connected to provide 100 MHz differential clock for the mPCIE slot. | | AM6 | PCIE_CLKP_33 | mPCIE_REFCLK_P | ✅ | PCIE_CLKN_33 and PCIE_CLKP_33 are correctly connected to provide 100 MHz differential clock for the mPCIE slot. | | AM9 | RESERVED_AM9 | | ✅ | Reserved pins are correctly left unconnected as specified by the datasheet. | | AM10 | RESERVED_AM10 | | ✅ | Reserved pins are correctly left unconnected as specified by the datasheet. | | AT32 | SIO_PWM_11 | SOC_PWM1 | ✅ | SIO_PWM_11 is correctly connected to SOC_PWM1 for PWM output functionality. | | AT34 | RESERVED | | ✅ | Reserved pin is correctly left unconnected as specified by the datasheet. | | AU32 | SIO_PWM_00 | SOC_PWM0 | ✅ | SIO_PWM_00 is correctly connected to SOC_PWM0 for PWM output functionality. | | AU34 | SIO_UART1_RXD | SIO_UART1_RXD | ✅ | SIO_UART1_RXD is correctly connected for UART1 receive data. | | AV32 | ~SIO_SPI_CS | SOC_SIO_SPI_CS1 | ✅ | SIO_SPI_CS is correctly connected to SOC_SIO_SPI_CS1 for SPI chip select. | | AV34 | SIO_UART1_TXD | SIO_UART1_TXD | ✅ | SIO_UART1_TXD is correctly connected for UART1 transmit data. | | AY28 | SIO_SPI_MOSI | SOC_SIO_SPI_MOSI | ✅ | SIO_SPI_MOSI is correctly connected to SOC_SIO_SPI_MOSI for SPI master out slave in. | | AY30 | SIO_SPI_CLK | SOC_SIO_SPI_CLK | ✅ | SIO_SPI_CLK is correctly connected to SOC_SIO_SPI_CLK for SPI clock. | | AY34 | ~SIO_UART1_CTS | SIO_UART1_CTSB | ✅ | SIO_UART1_CTS is correctly connected to SIO_UART1_CTSB for UART1 clear to send flow control. | </details> <details> <summary>U19 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA is correctly connected to +V1P8A, providing the 1.8V supply for the A-side of the level shifter. | | 2 | A1 | PMC_PLTRST_R_V1P8 | ✅ | A1 is correctly connected to PMC_PLTRST_R_V1P8 from CPU1 pin F20, translating the platform reset signal to 3.3V on B1. | | 3 | A2 | PMC_SUSCLK0 | ✅ | A2 is correctly connected to PMC_SUSCLK0 from CPU1 pin G24, translating the suspend clock signal to 3.3V on B2. | | 4 | A3 | PMC_SLP_S4_L | ✅ | A3 is correctly connected to PMC_SLP_S4_L from CPU1 pin F22, translating the S4 sleep state signal to 3.3V on B3. | | 5 | A4 | PMC_SLP_S3_L | ✅ | A4 is correctly connected to PMC_SLP_S3_L from CPU1 pin D22, translating the S3 sleep state signal to 3.3V on B4. | | 6 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 7 | B4 | SLP_S3_L | ✅ | B4 is correctly connected to SLP_S3_L, providing the 3.3V translated version of the S3 sleep state signal from A4. | | 8 | B3 | SLP_S4_L | ✅ | B3 is correctly connected to SLP_S4_L, providing the 3.3V translated version of the S4 sleep state signal from A3. | | 9 | B2 | SUSCLK_3P3 | ✅ | B2 is correctly connected to SUSCLK_3P3, providing the 3.3V translated version of the suspend clock signal from A2. | | 10 | B1 | PMC_PLTRST_L | ✅ | B1 is correctly connected to PMC_PLTRST_L, providing the 3.3V translated version of the platform reset signal from A1. | | 11 | VCCB | PWR_BUF1 | ✅ | VCCB is correctly connected to PWR_BUF1 which provides 3.3V standby power through R26 from +3VSB. | | 12 | OE | PMC_OE | ✅ | OE is correctly connected to PMC_OE with a 2.2K pull-up resistor to +V1P8A, enabling the level shifter by default. | </details> <details> <summary>D5 - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAT754C) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | +PS_3VSB | ✅ | Anode 1 connected to +PS_3VSB (3.3V standby rail), forming one input of the battery backup OR-ing circuit. | | A2 | A2 | +VBAT_R | ✅ | Anode 2 connected to +VBAT_R (battery voltage through 1K resistor), forming the second input of the battery backup OR-ing circuit. | | C | C | +RTCVCC | ✅ | Common cathode output connected to +RTCVCC, which powers the RTC section of the CPU from whichever source (standby or battery) has higher voltage. | </details> <details> <summary>BH1 - 353-0003073 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/353-0003073) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +VBAT | ✅ | Positive battery terminal connected to +VBAT net, which feeds through 1K resistor R278 to the battery backup OR-ing circuit. | | 2 | P2 | +VBAT | ✅ | Second positive battery terminal connected in parallel with pin 1 to +VBAT net for mechanical stability and redundant electrical connection. | | 3 | N | GND | ✅ | Negative battery terminal connected to ground. | </details> <details> <summary>Y1 - 145-0004789 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/145-0004789) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BRTCX2 | ✅ | Crystal pin connected to CPU1 RTC oscillator pin ILB_RTC_X2 (BRTCX2) with 18pF load capacitor C42 to ground and 10M feedback resistor R76 to pin 2. | | 2 | 2 | BRTCX1 | ✅ | Crystal pin connected to CPU1 RTC oscillator pin ILB_RTC_X1 (BRTCX1) with 18pF load capacitor C43 to ground and 10M feedback resistor R76 to pin 1. | </details> <details> <summary>Y2 - 145-0004792 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XTAL25_IN | ✅ | Crystal input terminal connected to CPU1 ICLK_OSCIN (pin AH12) with 27pF load capacitor C175 and 1M feedback resistor R188 to pin 3. This is a standard crystal oscillator input configuration. | | 2 | 2 | GND | ✅ | Ground pin correctly connected to GND net. Standard configuration for 4-pin crystal packages. | | 3 | 3 | XTAL25_OUT | ✅ | Crystal output terminal connected to CPU1 ICLK_OSCOUT (pin AH10) with 27pF load capacitor C176 and 1M feedback resistor R188 to pin 1. This is a standard crystal oscillator output configuration. | | 4 | 4 | GND | ✅ | Ground pin correctly connected to GND net. Standard configuration for 4-pin crystal packages. | </details> <details> <summary>D3 - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_PCIE_WAKE | ✅ | Both pins are connected to PMC_PCIE_WAKE net, which is pulled up to +3VSB (3.3V) through R27 (2.2K). This configuration suggests both pins are anodes tied together, likely for a dual diode configuration. | | 2 | 2 | PMC_PCIE_WAKE | ✅ | Both pins are connected to PMC_PCIE_WAKE net, which is pulled up to +3VSB (3.3V) through R27 (2.2K). This configuration suggests both pins are anodes tied together, likely for a dual diode configuration. | | 3 | 3 | PMC_PCIE_WAKE_R | ✅ | Pin 3 is connected to PMC_PCIE_WAKE_R, which goes to CPU1 pin F26 and is pulled up to +V1P8A (1.8V) through R253 (1K). This appears to be the cathode of the diode, forming a level shifter from 3.3V to 1.8V logic. | </details> <details> <summary>D10 - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAT754C) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | 3VSB_OK | ✅ | Pin A1 (Anode 1) is connected to 3VSB_OK, which is pulled up to +3VSB (3.3V) through R162 (1K). This is one input to the diode OR gate. | | A2 | A2 | PMC_PWRBTN | ✅ | Pin A2 (Anode 2) is connected to PMC_PWRBTN, which goes to CPU1 pin J26 (active-low power button signal). This is the second input to the diode OR gate. | | C | C | PS_OUT_L | ✅ | Pin C (Common Cathode) is connected to PS_OUT_L, which is the output of the diode OR gate. This output will be low if either 3VSB_OK or PMC_PWRBTN is low. | </details> <details> <summary>J7 - HDR_2POS_DUAL_TIN ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GPIO_S5_17 | ✅ | Connected to GPIO_S5_17 from the SoC, allowing the jumper to control the GPIO state. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for pulling the GPIO low when the jumper is installed. | </details> <details> <summary>R183 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | Connected to +V1P8S to provide pull-up voltage for the GPIO. | | 2 | 2 | GPIO_S5_17 | ✅ | Connected to GPIO_S5_17, pulling the GPIO high through the 10K resistor when jumper J7 is not installed. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A7 | USB_HSIC_RCOMP | USB_HSIC0_RCOMP | ✅ | USB_HSIC_RCOMP is correctly connected to a 45.3 ohm resistor to ground for USB HSIC impedance compensation. | | B4 | USB_HSIC0_DATA | | ✅ | USB_HSIC0_DATA is unconnected, indicating USB HSIC port 0 is not used in this design. | | B5 | USB_HSIC0_STROBE | | ✅ | USB_HSIC0_STROBE is unconnected, indicating USB HSIC port 0 is not used in this design. | | B12 | GPIO_S5_43 | | ✅ | GPIO_S5_43 is unconnected. This pin can be muxed to USB_ULPI_REFCLK but is not used in this design. | | B20 | ~USB_OC_11 | SOC_USB_HOST_OC1 | ✅ | USB_OC_11 (USB overcurrent detect 1) is correctly connected with a 10K pull-up resistor to +V1P8A for active-low operation. | | C7 | USB_RCOMPI | USB_RCOMP | ✅ | USB_RCOMPI and USB_RCOMPO are correctly connected together with a 45.3 ohm resistor to ground for USB 2.0 impedance compensation. | | D6 | USB_RCOMPO | USB_RCOMP | ✅ | USB_RCOMPI and USB_RCOMPO are correctly connected together with a 45.3 ohm resistor to ground for USB 2.0 impedance compensation. | | C20 | ~USB_OC_00 | SOC_USB_HOST_OC0 | ✅ | USB_OC_00 (USB overcurrent detect 0) is correctly connected with a 10K pull-up resistor to +V1P8A for active-low operation. | | D2 | USB_HSIC1_STROBE | | ✅ | USB_HSIC1_STROBE is unconnected, indicating USB HSIC port 1 is not used in this design. | | D4 | USB3_RXP0 | USB3_RXP0 | ✅ | USB3_RXP0 is connected for USB 3.0 receive positive differential signal. | | D10 | ICLK_USB_TERM_1 | ICLK_USB_TERM_0 | ✅ | ICLK_USB_TERM pins have swapped net names. Pin D10 (ICLK_USB_TERM[1]) connects to net ICLK_USB_TERM_0, and pin F10 (ICLK_USB_TERM[0]) connects to net ICLK_USB_TERM_1. Both are correctly terminated with 1K resistors to ground, so this is functionally correct but the net naming is confusing. | | F10 | ICLK_USB_TERMN | ICLK_USB_TERM_1 | ✅ | ICLK_USB_TERM pins have swapped net names. Pin D10 (ICLK_USB_TERM[1]) connects to net ICLK_USB_TERM_0, and pin F10 (ICLK_USB_TERM[0]) connects to net ICLK_USB_TERM_1. Both are correctly terminated with 1K resistors to ground, so this is functionally correct but the net naming is confusing. | | E2 | USB_HSIC1_DATA | | ✅ | USB_HSIC1_DATA is unconnected, indicating USB HSIC port 1 is not used in this design. | | E3 | USB3_RXN0 | USB3_RXN0 | ✅ | USB3_RXN0 is connected for USB 3.0 receive negative differential signal. | | G2 | GPIO_S5_31 | | ✅ | GPIO_S5_31 is unconnected. This pin can be muxed to USB_ULPI_CLK but is not used in this design. | | G14 | USB_DN1 | USB_DN1 | ✅ | USB_DN1 is connected for USB 2.0 port 1 data negative signal. | | H3 | GPIO_S5_42 | | ✅ | GPIO_S5_42 is unconnected. This pin can be muxed to USB_ULPI_STP but is not used in this design. | | H4 | RESERVED_H4 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | H5 | RESERVED_H5 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | H7 | RESERVED_H7 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | H8 | RESERVED_H8 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | H10 | USB_DN3 | | ✅ | USB_DN3 is unconnected, indicating USB port 3 is not used in this design. | | J3 | GPIO_S5_40 | | ✅ | GPIO_S5_40 is unconnected, indicating this GPIO is not used in this design. | | J12 | USB_DN2 | USB_HOST_DN | ✅ | USB_DN2 is connected for USB 2.0 port 2 data negative signal to USB host interface. | | J14 | USB_DP1 | USB_DP1 | ✅ | USB_DP1 is connected for USB 2.0 port 1 data positive signal. | | K2 | GPIO_S5_34 | | ✅ | GPIO_S5_34 is unconnected, indicating this GPIO is not used in this design. | | K3 | GPIO_S5_35 | | ✅ | GPIO_S5_35 is unconnected, indicating this GPIO is not used in this design. | | K6 | USB3_TXP0 | USB3_TXP0 | ✅ | USB3_TXP0 is connected for USB 3.0 transmit positive differential signal. | | K7 | USB3_TXN0 | USB3_TXN0 | ✅ | USB3_TXN0 is connected for USB 3.0 transmit negative differential signal. | | K10 | USB_DP3 | | ✅ | USB_DP3 is unconnected, indicating USB port 3 is not used in this design. | | K12 | USB_DP2 | USB_HOST_DP | ✅ | USB_DP2 is connected for USB 2.0 port 2 data positive signal to USB host interface. | | K16 | USB_DN0 | USB_DN0 | ✅ | USB_DN0 is connected for USB 2.0 port 0 data negative signal. | | L1 | GPIO_S5_33 | | ✅ | GPIO_S5_33 is unconnected, indicating this GPIO is not used in this design. | | L3 | GPIO_S5_39 | | ✅ | GPIO_S5_39 is unconnected, indicating this GPIO is not used in this design. | | M2 | GPIO_S5_36 | | ✅ | GPIO_S5_36 is unconnected, indicating this GPIO is not used in this design. | | M3 | GPIO_S5_32 | | ✅ | GPIO_S5_32 is unconnected, indicating this GPIO is not used in this design. | | M4 | RESERVED_M4 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | M6 | RESERVED_M6 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | M7 | RESERVED_M7 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | M9 | RESERVED_M9 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | M10 | RESERVED_M10 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | M12 | USB3_REXT0 | USB3_REXT0 | ✅ | USB3_REXT0 is correctly connected to a 1.24K ohm resistor to ground for USB 3.0 external reference. | | M13 | USB_PLL_MON | USB_PLL_MON | ✅ | USB_PLL_MON is connected to a DNI test point for monitoring USB PLL operation. | | M16 | USB_DP0 | USB_DP0 | ✅ | USB_DP0 is connected for USB 2.0 port 0 data positive signal. | | N3 | GPIO_S5_37 | | ✅ | GPIO_S5_37 is unconnected, indicating this GPIO is not used in this design. | | P2 | GPIO_S5_38 | | ✅ | GPIO_S5_38 is unconnected, indicating this GPIO is not used in this design. | | P3 | GPIO_S5_41 | | ✅ | GPIO_S5_41 is unconnected, indicating this GPIO is not used in this design. | | P6 | RESERVED_P6 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | P7 | RESERVED_P7 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | P10 | RESERVED_P10 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | P12 | RESERVED_P12 | | ✅ | RESERVED pins are unconnected as expected for reserved pins. | | BC12 | GPIO_S0_SC_56 | GPIO_S0_SC_56 | ✅ | GPIO_S0_SC_56 is connected to an unspecified net, likely used for a board-specific function. | | BC14 | GPIO_S0_SC_58 | HDMI_CEC | ✅ | GPIO_S0_SC_58 is connected to HDMI_CEC signal for HDMI Consumer Electronics Control. | | BC16 | GPIO_S0_SC_61 | PCU_UART3_RXD | ✅ | GPIO_S0_SC_61 is correctly configured as UART3 RX with level shifting from 1.8V to 3.3V through U6. | | BD12 | GPIO_S0_SC_55 | GPIO_S0_SC_55 | ✅ | GPIO_S0_SC_55 is connected to a DNI test point for debug access. | | BD14 | GPIO_S0_SC_57 | PCU_UART3_TXD | ✅ | GPIO_S0_SC_57 is correctly configured as UART3 TX with level shifting from 1.8V to 3.3V through U6. | | BD16 | GPIO_S0_SC_60 | | ✅ | GPIO_S0_SC_60 is unconnected, indicating this GPIO is not used in this design. | | BF14 | GPIO_S0_SC_59 | | ✅ | GPIO_S0_SC_59 is unconnected, indicating this GPIO is not used in this design. | | BF18 | LPC_RCOMP | LPC_RCOMP | ✅ | LPC_RCOMP is correctly connected to a 49.9 ohm resistor to ground for LPC bus impedance compensation. | | BF27 | SIO_I2C4_DATA | | ✅ | SIO_I2C4_DATA is unconnected, indicating I2C port 4 is not used in this design. | | BG11 | ~PCU_SMB_ALERT | PCU_SMB_ALERT | ✅ | PCU_SMB_ALERT is correctly connected with a 10K pull-up to +V1P8S and routed to LAN-SMB-ALERT# through a 0 ohm jumper. | | BG12 | PCU_SMB_DATA | PCU_SMB_DATA | ✅ | PCU_SMB_DATA is correctly connected with a 2.2K pull-up to +V1P8S and level-shifted to DDR_SMB_DATA through U5. | | BG13 | ILB_LPC_SERIRQ | | ✅ | ILB_LPC_SERIRQ is unconnected, indicating the LPC serial IRQ is not used in this design. | | BG14 | ILB_LPC_AD_33 | | ✅ | ILB_LPC_AD_33 is unconnected, indicating the LPC interface is not used in this design. | | BG15 | ILB_LPC_CLK_00 | | ✅ | ILB_LPC_CLK_00 is unconnected, indicating the LPC interface is not used in this design. | | BG16 | ~ILB_LPC_CLKRUN | | ✅ | ILB_LPC_CLKRUN is unconnected, indicating the LPC interface is not used in this design. | | BG17 | ~ILB_LPC_FRAME | | ✅ | ILB_LPC_FRAME is unconnected, indicating the LPC interface is not used in this design. | | BG23 | SIO_I2C0_CLK | | ✅ | SIO_I2C0_CLK is unconnected, indicating I2C port 0 is not used in this design. | | BG24 | SIO_I2C1_DATA | SIO_I2C1_SDA | ✅ | SIO_I2C1_DATA is connected to a DNI test point for debug access to I2C1 data line. | | BG25 | SIO_I2C2_DATA | | ✅ | SIO_I2C2_DATA is unconnected, indicating I2C port 2 is not used in this design. | | BG26 | SIO_I2C3_DATA | | ✅ | SIO_I2C3_DATA is unconnected, indicating I2C port 3 is not used in this design. | | BG27 | SIO_I2C4_CLK | | ✅ | SIO_I2C4_CLK is unconnected, indicating I2C port 4 is not used in this design. | | BG28 | SIO_I2C5_CLK | SI0_I2C5_SCL | ✅ | SIO_I2C5_CLK is correctly connected through a 22 ohm series resistor to I2C5_SCL for signal integrity. | | BG29 | SIO_I2C6_CLK | SI0_I2C6_SCL | ✅ | SIO_I2C6_CLK is correctly connected through a 22 ohm series resistor to I2C6_SCL for signal integrity. | | BG30 | GPIO_S0_SC_093 | TP10_NET | ✅ | GPIO_S0_SC_093 is intentionally grounded through a 0 ohm resistor, likely to disable a specific function. | | BH10 | PCU_SMB_CLK | PCU_SMB_CLK | ✅ | PCU_SMB_CLK is correctly connected with a 2.2K pull-up to +V1P8S and level-shifted to DDR_SMB_CLK through U5. | | BH12 | ILB_8254_SPKR | ILB_8254_SPKR | ✅ | ILB_8254_SPKR is connected to a speaker output signal. | | BH14 | ILB_LPC_CLK_11 | | ✅ | ILB_LPC_CLK_11 is unconnected, indicating the LPC interface is not used in this design. | | BH16 | ILB_LPC_AD_00 | | ✅ | ILB_LPC_AD_00 is unconnected, indicating the LPC interface is not used in this design. | | BH22 | SIO_I2C0_DATA | | ✅ | SIO_I2C0_DATA is unconnected, indicating I2C port 0 is not used in this design. | | BH24 | SIO_I2C1_CLK | SIO_I2C1_SCL | ✅ | SIO_I2C1_CLK is connected to a DNI test point for debug access to I2C1 clock line. | | BH26 | SIO_I2C3_CLK | | ✅ | SIO_I2C3_CLK is unconnected, indicating I2C port 3 is not used in this design. | | BH28 | SIO_I2C5_DATA | SI0_I2C5_SDA | ✅ | SIO_I2C5_DATA is correctly connected through a 22 ohm series resistor to I2C5_SDA for signal integrity. | | BH30 | GPIO_S0_SC_092 | TP9_NET | ✅ | GPIO_S0_SC_092 is intentionally grounded through a 0 ohm resistor, likely to disable a specific function. | | BJ13 | ILB_LPC_AD_22 | | ✅ | ILB_LPC_AD_22 is unconnected, indicating the LPC interface is not used in this design. | | BJ17 | ILB_LPC_AD_11 | | ✅ | ILB_LPC_AD_11 is unconnected, indicating the LPC interface is not used in this design. | | BJ25 | SIO_I2C2_CLK | | ✅ | SIO_I2C2_CLK is unconnected, indicating I2C port 2 is not used in this design. | | BJ29 | SIO_I2C6_DATA | SI0_I2C6_SDA | ✅ | SIO_I2C6_DATA is correctly connected through a 22 ohm series resistor to I2C6_SDA for signal integrity. | </details> <details> <summary>J4 - SIP6_RA ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0004869) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pin correctly connected to GND, providing the reference voltage for the UART serial communication. | | 2 | 2 | | ✅ | Pins 2, 3, and 6 are intentionally left unconnected as they are not required for this UART application. | | 3 | 3 | | ✅ | Pins 2, 3, and 6 are intentionally left unconnected as they are not required for this UART application. | | 6 | 6 | | ✅ | Pins 2, 3, and 6 are intentionally left unconnected as they are not required for this UART application. | | 4 | 4 | DBG_UART3_RXD | ✅ | Pin 4 correctly connected to DBG_UART3_RXD, which receives data from the external cable (cable TX to CPU RX). | | 5 | 5 | DBG_UART3_TXD_R | ✅ | Pin 5 correctly connected to DBG_UART3_TXD_R, which transmits data to the external cable (CPU TX to cable RX). | </details> <details> <summary>U6 - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DBG_UART3_TXD | ✅ | B2 pin connects to DBG_UART3_TXD, translating the CPU's UART transmit signal from 1.8V to 3.3V for the debug connector. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the reference for the level shifter. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin is correctly connected to +V1P8S (1.8V) with appropriate bypass capacitor C30 (0.1uF), providing power for the A-side of the level shifter. | | 4 | A2 | PCU_UART3_TXD | ✅ | A2 pin connects to PCU_UART3_TXD from the CPU, receiving the 1.8V UART transmit signal for level translation. | | 5 | A1 | PCU_UART3_RXD | ✅ | A1 pin connects to PCU_UART3_RXD, routing the received UART signal from the B-side to the CPU at 1.8V. | | 6 | OE | LSENB | ✅ | OE pin is connected to LSENB, which is pulled high to +V1P8S through R52 (2.2K), keeping the level shifter permanently enabled. | | 7 | VCCB | BUF3_PWR | ✅ | VCCB pin is correctly connected to BUF3_PWR, which supplies 3.3V from +3VSB through R51 (0 ohm), with bypass capacitor C31 (0.1uF). | | 8 | B1 | DBG_UART3_RXD | ✅ | B1 pin connects to DBG_UART3_RXD, receiving the 3.3V UART signal from the debug connector for translation to 1.8V. | </details> <details> <summary>U5 - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4327-0009) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | DDR_SMB_CLK | ✅ | B2 pin connects to DDR_SMB_CLK, which is the high-voltage side (3.3V) of the SMBus clock channel 2. This signal routes through R841 to LAN-SMB-CLK. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground net, providing the common ground reference for the level translator. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin is connected to +V1P8S (1.8V supply), providing power for the low-voltage side of the level translator. | | 4 | A2 | PCU_SMB_CLK | ✅ | A2 pin connects to PCU_SMB_CLK, which is the low-voltage side (1.8V) of the SMBus clock channel 2 from the CPU. | | 5 | A1 | PCU_SMB_DATA | ✅ | A1 pin connects to PCU_SMB_DATA, which is the low-voltage side (1.8V) of the SMBus data channel 1 from the CPU. | | 6 | OE | PCU_SMB_BUFF_ENB | ✅ | OE pin connects to PCU_SMB_BUFF_ENB with a 10K pull-up to +V1P8S, controlling the enable state of the level translator. | | 7 | VCCB | BUF2_PWR | ✅ | VCCB pin is connected to BUF2_PWR, which is +VCC3 (3.3V) through R48 (0 ohm), providing power for the high-voltage side of the level translator. | | 8 | B1 | DDR_SMB_DATA | ✅ | B1 pin connects to DDR_SMB_DATA, which is the high-voltage side (3.3V) of the SMBus data channel 1. This signal routes through R840 to LAN-SMB-DATA. | </details> <details> <summary>R840 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_DATA | ✅ | Pin 1 connects to DDR_SMB_DATA from the level translator's high-voltage side. | | 2 | 2 | LAN-SMB-DATA | ✅ | Pin 2 connects to LAN-SMB-DATA, routing the translated SMBus data signal to the LAN interface. | </details> <details> <summary>R841 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_SMB_CLK | ✅ | Pin 1 connects to DDR_SMB_CLK from the level translator's high-voltage side. | | 2 | 2 | LAN-SMB-CLK | ✅ | Pin 2 connects to LAN-SMB-CLK, routing the translated SMBus clock signal to the LAN interface. | </details> <details> <summary>R842 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1121-0001) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-SMB-ALERT# | ✅ | Pin 1 connects to LAN-SMB-ALERT#, the active-low alert signal from the LAN interface. | | 2 | 2 | PCU_SMB_ALERT | ✅ | Pin 2 connects to PCU_SMB_ALERT, routing the alert signal directly to the CPU without level translation. | </details> <details> <summary>R77 - 45.3 ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004472) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. This is the ground side of the USB HSIC RCOMP resistor. | | 2 | 2 | USB_HSIC0_RCOMP | ✅ | Connected to USB_HSIC0_RCOMP (CPU1 pin A7). This provides the 45.3 ohm compensation resistance for the USB HSIC interface. | </details> <details> <summary>R212 - 1.24K ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004478) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_REXT0 | ✅ | Connected to USB3_REXT0 (CPU1 pin M12). This provides the 1.24K external reference resistance for the USB 3.0 interface. | | 2 | 2 | GND | ✅ | Connected to GND. This is the ground side of the USB 3.0 REXT resistor. | </details> <details> <summary>R185 - 45.3 ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004472) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. This is the ground side of the USB 2.0 RCOMP resistor. | | 2 | 2 | USB_RCOMP | ✅ | Connected to USB_RCOMP (CPU1 pins D6 and C7). This provides the 45.3 ohm compensation resistance for the USB 2.0 interface. | </details> <details> <summary>R187 - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. This is the ground side of the USB clock termination resistor. | | 2 | 2 | ICLK_USB_TERM_0 | ✅ | Connected to ICLK_USB_TERM_0 (CPU1 pin D10). This provides 1K pull-down termination for the USB clock signal. | </details> <details> <summary>R186 - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001923) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. This is the ground side of the USB clock termination resistor. | | 2 | 2 | ICLK_USB_TERM_1 | ✅ | Connected to ICLK_USB_TERM_1 (CPU1 pin F10, ICLK_USB_TERMN). This provides 1K pull-down termination for the USB clock signal. | </details> <details> <summary>R241 - 49.9 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0003059) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LPC_RCOMP | ✅ | Connected to CPU1 pin BF18 (LPC_RCOMP) for LPC interface impedance calibration. This connection is correct. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the RCOMP calibration resistor. This connection is correct. | </details> <details> <summary>R48 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | BUF2_PWR | ✅ | Pin 1 connects to BUF2_PWR, which supplies power to the VCCB pin of level shifter U5. This 0-ohm resistor acts as a jumper to provide +VCC3 power to the high-voltage side of the level shifter. | | 2 | 2 | +VCC3 | ✅ | Pin 2 connects to +VCC3 power rail, sourcing 3.3V power through the 0-ohm resistor to BUF2_PWR. This provides the appropriate voltage level for the DDR_SMB interface side of the level shifter. | </details> <details> <summary>R243 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TP9_NET | ✅ | Pin 1 connects to TP9_NET, which is tied to CPU GPIO_S0_SC_092 (pin BH30). This 0-ohm resistor grounds the unused GPIO pin, as indicated by schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the GPIO pin being terminated through this 0-ohm resistor. | </details> <details> <summary>R261 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | TP10_NET | ✅ | Pin 1 connects to TP10_NET, which is tied to CPU GPIO_S0_SC_093 (pin BG30). This 0-ohm resistor grounds the unused GPIO pin, as indicated by schematic notes stating 'GROUNDING THESE PINS THROUGH 0 OHM RESISTORS'. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the GPIO pin being terminated through this 0-ohm resistor. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A48 | DRAM_VDD_S4 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | AK38 | DRAM_VDD_S4_AK38 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | AM38 | DRAM_VDD_S4_AM38 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | AV41 | DRAM_VDD_S4_AV41 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | AV42 | DRAM_VDD_S4_AV42 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | BB46 | DRAM_VDD_S4_BB46 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | BD49 | DRAM_VDD_S4_BD49 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | BD52 | DRAM_VDD_S4_BD52 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | BD53 | DRAM_VDD_S4_BD53 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | BF44 | DRAM_VDD_S4_BF44 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | BG51 | DRAM_VDD_S4_BG51 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | BJ48 | DRAM_VDD_S4_BJ48 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | C51 | DRAM_VDD_S4_C51 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | D44 | DRAM_VDD_S4_D44 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | F49 | DRAM_VDD_S4_F49 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | F52 | DRAM_VDD_S4_F52 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | F53 | DRAM_VDD_S4_F53 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | H46 | DRAM_VDD_S4_H46 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | M41 | DRAM_VDD_S4_M41 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | M42 | DRAM_VDD_S4_M42 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | V38 | DRAM_VDD_S4_V38 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | Y38 | DRAM_VDD_S4_Y38 | +VDIMM | ✅ | DRAM power supply pins connected to +VDIMM rail providing 1.35V DDR3L power. These pins supply power to the memory controller and DRAM interface in S4 and active states. | | N28 | CORE_VSS_SENSE_N28 | VSS_SENSE | ✅ | Core ground sense pin for voltage regulator feedback. Connected to VSS_SENSE net for remote sensing of the ground reference. | | P28 | CORE_VCC_SENSE_P28 | VCC_SENSE | ✅ | Core voltage sense pin for voltage regulator feedback. Connected to VCC_SENSE net for remote sensing of the VCC supply voltage. | | AA22 | TP2_CORE_VCC_S0IX | $9N615 | ✅ | Test point pin for monitoring core VCC voltage in S0IX state. Connected to test point TP2 which is marked DNI (Do Not Install). | | AA24 | UNCORE_VNN_S3_AA24 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AC22 | UNCORE_VNN_S3_AC22 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AC24 | UNCORE_VNN_S3_AC24 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AD22 | UNCORE_VNN_S3_AD22 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AD24 | UNCORE_VNN_S3_AD24 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AF22 | UNCORE_VNN_S3_AF22 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AF24 | UNCORE_VNN_S3_AF24 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AG22 | UNCORE_VNN_S3_AG22 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AG24 | UNCORE_VNN_S3_AG24 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AJ22 | UNCORE_VNN_S3_AJ22 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AJ24 | UNCORE_VNN_S3_AJ24 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AK22 | UNCORE_VNN_S3_AK22 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AK24 | UNCORE_VNN_S3_AK24 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AK25 | UNCORE_VNN_S3_AK25 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AK27 | UNCORE_VNN_S3_AK27 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AK29 | UNCORE_VNN_S3_AK29 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AK30 | UNCORE_VNN_S3_AK30 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AK32 | UNCORE_VNN_S3_AK32 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AM22 | UNCORE_VNN_S3_AM22 | +VGFX | ✅ | Uncore/graphics power supply pins connected to +VGFX rail. These pins provide variable voltage (0.50-1.05V) controlled via SVID interface for the graphics and uncore logic. | | AA27 | CORE_VCC_S0IX_AA27 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AA29 | CORE_VCC_S0IX_AA29 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AA30 | CORE_VCC_S0IX_AA30 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AC27 | CORE_VCC_S0IX_AC27 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AC29 | CORE_VCC_S0IX_AC29 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AC30 | CORE_VCC_S0IX_AC30 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AD27 | CORE_VCC_S0IX_AD27 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AD29 | CORE_VCC_S0IX_AD29 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AD30 | CORE_VCC_S0IX_AD30 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AF27 | CORE_VCC_S0IX_AF27 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AF29 | CORE_VCC_S0IX_AF29 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AG27 | CORE_VCC_S0IX_AG27 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AG29 | CORE_VCC_S0IX_AG29 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | AG30 | CORE_VCC_S0IX_AG30 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | P26 | CORE_VCC_S0IX_P26 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | P27 | CORE_VCC_S0IX_P27 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | U27 | CORE_VCC_S0IX_U27 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | U29 | CORE_VCC_S0IX_U29 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | V27 | CORE_VCC_S0IX_V27 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | V29 | CORE_VCC_S0IX_V29 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | V30 | CORE_VCC_S0IX_V30 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | Y27 | CORE_VCC_S0IX_Y27 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | Y29 | CORE_VCC_S0IX_Y29 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | Y30 | CORE_VCC_S0IX_Y30 | +VCORE | ✅ | Core processor power supply pins connected to +VCORE rail. These pins provide variable voltage (0.40-1.0V) controlled via SVID interface for the processor cores. | | BB8 | UNCORE_VNN_SENSE | VCCGT_SENSE | ✅ | Uncore/graphics voltage sense pin for voltage regulator feedback. Connected to VCCGT_SENSE net for remote sensing of the VNN supply voltage. | | AD38 | DRAM_VDD_S4_AD38 | DRAM_VDD_CLK | ✅ | DRAM clock power supply pins connected to DRAM_VDD_CLK rail. This rail is derived from +VDIMM through 0-ohm resistor R275 to provide filtered power for the DRAM clock circuitry. | | AF38 | DRAM_VDD_S4_AF38 | DRAM_VDD_CLK | ✅ | DRAM clock power supply pins connected to DRAM_VDD_CLK rail. This rail is derived from +VDIMM through 0-ohm resistor R275 to provide filtered power for the DRAM clock circuitry. | | AF30 | TP_CORE_V1P05_S4 | $9N613 | ✅ | Test point pin for monitoring 1.05V core supply in S4 state. Connected to test point TP1 which is marked DNI (Do Not Install). | </details> <details> <summary>R275 - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | 0-ohm jumper connecting +VDIMM (1.35V DDR3L supply) to DRAM_VDD_CLK net, providing a separate power domain for DRAM clock circuitry with dedicated decoupling. | | 2 | 2 | DRAM_VDD_CLK | ✅ | 0-ohm jumper connecting +VDIMM (1.35V DDR3L supply) to DRAM_VDD_CLK net, providing a separate power domain for DRAM clock circuitry with dedicated decoupling. | </details> <details> <summary>TP1 - TEST_POINT_0.040_SMT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/999-0000003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $9N613 | ✅ | Test point connected to CPU1 pin AF30 (TP_CORE_V1P05_S4) for monitoring the 1.05V core voltage supply in S4 power state. Component is marked DNI (Do Not Install), which is standard practice for debug test points. | </details> <details> <summary>TP2 - TEST_POINT_0.040_SMT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/999-0000003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $9N615 | ✅ | Test point connected to CPU1 pin AA22 (TP2_CORE_VCC_S0IX) for monitoring the variable core VCC voltage in S0IX low-power idle state. Component is marked DNI (Do Not Install), which is standard practice for debug test points. | </details> <details> <summary>CPU1 - INTEL_ATOM_E3825_SOC ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | AC32 | CORE_V1P05_S3_AC32 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,41.55,44.21,49.05" aspect-ratio="1.29" } <ul><li>These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic)</li><li>All pins are connected to the +V1P0S net (from schematic)</li><li>The +V1P0S net name suggests 1.0V nominal voltage (from schematic)</li><li>Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic)</li><li>V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic)</li><li>Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic)</li><li>Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning)</li><li>The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning)</li><li>Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning)</li><li>The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119-120">140-0004628</a>, page 119-120)</li><li>These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)</li></ul></details> | | Y32 | CORE_V1P05_S3_Y32 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,42.13,44.21,49.63" aspect-ratio="1.29" } <ul><li>These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic)</li><li>All pins are connected to the +V1P0S net (from schematic)</li><li>The +V1P0S net name suggests 1.0V nominal voltage (from schematic)</li><li>Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic)</li><li>V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic)</li><li>Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic)</li><li>Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning)</li><li>The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning)</li><li>Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning)</li><li>The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119-120">140-0004628</a>, page 119-120)</li><li>These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)</li></ul></details> | | AA33 | CORE_V1P05_S3_AA33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,33.31,44.21,40.81" aspect-ratio="1.29" } <ul><li>These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic)</li><li>All pins are connected to the +V1P0S net (from schematic)</li><li>The +V1P0S net name suggests 1.0V nominal voltage (from schematic)</li><li>Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic)</li><li>V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic)</li><li>Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic)</li><li>Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning)</li><li>The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning)</li><li>Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning)</li><li>The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119-120">140-0004628</a>, page 119-120)</li><li>These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)</li></ul></details> | | AF33 | CORE_V1P05_S3_AF33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,28.61,61.48,36.11" aspect-ratio="1.29" } <ul><li>These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic)</li><li>All pins are connected to the +V1P0S net (from schematic)</li><li>The +V1P0S net name suggests 1.0V nominal voltage (from schematic)</li><li>Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic)</li><li>V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic)</li><li>Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic)</li><li>Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning)</li><li>The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning)</li><li>Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning)</li><li>The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119-120">140-0004628</a>, page 119-120)</li><li>These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)</li></ul></details> | | AG33 | CORE_V1P05_S3_AG33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,29.20,61.48,36.70" aspect-ratio="1.29" } <ul><li>These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic)</li><li>All pins are connected to the +V1P0S net (from schematic)</li><li>The +V1P0S net name suggests 1.0V nominal voltage (from schematic)</li><li>Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic)</li><li>V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic)</li><li>Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic)</li><li>Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning)</li><li>The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning)</li><li>Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning)</li><li>The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119-120">140-0004628</a>, page 119-120)</li><li>These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)</li></ul></details> | | AG35 | CORE_V1P05_S3_AG35 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,29.79,61.48,37.29" aspect-ratio="1.29" } <ul><li>These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic)</li><li>All pins are connected to the +V1P0S net (from schematic)</li><li>The +V1P0S net name suggests 1.0V nominal voltage (from schematic)</li><li>Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic)</li><li>V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic)</li><li>Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic)</li><li>Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning)</li><li>The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning)</li><li>Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning)</li><li>The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119-120">140-0004628</a>, page 119-120)</li><li>These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)</li></ul></details> | | U33 | CORE_V1P05_S3_U33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,30.37,61.48,37.87" aspect-ratio="1.29" } <ul><li>These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic)</li><li>All pins are connected to the +V1P0S net (from schematic)</li><li>The +V1P0S net name suggests 1.0V nominal voltage (from schematic)</li><li>Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic)</li><li>V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic)</li><li>Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic)</li><li>Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning)</li><li>The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning)</li><li>Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning)</li><li>The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119-120">140-0004628</a>, page 119-120)</li><li>These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)</li></ul></details> | | U35 | CORE_V1P05_S3_U35 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,30.96,61.48,38.46" aspect-ratio="1.29" } <ul><li>These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic)</li><li>All pins are connected to the +V1P0S net (from schematic)</li><li>The +V1P0S net name suggests 1.0V nominal voltage (from schematic)</li><li>Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic)</li><li>V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic)</li><li>Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic)</li><li>Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning)</li><li>The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning)</li><li>Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning)</li><li>The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119-120">140-0004628</a>, page 119-120)</li><li>These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)</li></ul></details> | | V33 | CORE_V1P05_S3_V33 | +V1P0S | ❌ | <details><summary>CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="53.98,31.55,61.48,39.05" aspect-ratio="1.29" } <ul><li>These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic)</li><li>All pins are connected to the +V1P0S net (from schematic)</li><li>The +V1P0S net name suggests 1.0V nominal voltage (from schematic)</li><li>Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic)</li><li>V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119">140-0004628</a>, page 119)</li><li>CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120">140-0004628</a>, page 120)</li><li>Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic)</li><li>Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic)</li><li>Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning)</li><li>The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning)</li><li>Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning)</li><li>The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet <a href="https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119-120">140-0004628</a>, page 119-120)</li><li>These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)</li></ul></details> | | A3 | VSS_A3_A3 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | A5 | VSS_A5_A5 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | A6 | VSS_A6_A6 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | A49 | VSS_A49_A49 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | A51 | VSS_A51_A51 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | A52 | VSS_A52_A52 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | B2 | VSS_B2_B2 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | B52 | VSS_B52_B52 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | B53 | VSS_B53_B53 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BE1 | VSS_BE1_BE1 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BE53 | VSS_BE53_BE53 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BG1 | VSS_BG1_BG1 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BG53 | VSS_BG53_BG53 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BH1 | VSS_BH1_BH1 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BH2 | VSS_BH2_BH2 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BH52 | VSS_BH52_BH52 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BH53 | VSS_BH53_BH53 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BJ2 | VSS_BJ2_BJ2 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BJ3 | VSS_BJ3_BJ3 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BJ5 | VSS_BJ5_BJ5 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BJ49 | VSS_BJ49_BJ49 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BJ51 | VSS_BJ51_BJ51 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | BJ52 | VSS_BJ52_BJ52 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | C1 | VSS_C1_C1 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | C53 | VSS_C53_C53 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | E1 | VSS_E1_E1 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | E53 | VSS_E53_E53 | GND | ✅ | Ground pins correctly connected to GND net. These VSS pins provide ground reference for the SoC. | | B6 | UNCORE_V1P0_G3_B6 | +V1P0A | ✅ | UNCORE_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling. | | C5 | UNCORE_V1P0_G3_C5 | +V1P0A | ✅ | UNCORE_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling. | | U22 | UNCORE_V1P0_G3_U22 | +V1P0A | ✅ | UNCORE_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling. | | V22 | UNCORE_V1P0_G3_V22 | +V1P0A | ✅ | UNCORE_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling. | | C3 | USB3_V1P0_G3_C3 | +V1P0A | ✅ | USB3_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling. | | Y19 | USB3_V1P0_G3_Y19 | +V1P0A | ✅ | USB3_V1P0_G3 pins correctly connected to +V1P0A (1.0V) always-on rail with appropriate decoupling. | | F1 | RESERVED_F1 | $10N1595 | ✅ | RESERVED_F1 pin connected to test point TP4. This is acceptable for a reserved pin used for debug access. | | M14 | USB_V1P0_S3_M14 | +V1P0S | ✅ | USB_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | U18 | USB_V1P0_S3_U18 | +V1P0S | ✅ | USB_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | U19 | USB_V1P0_S3_U19 | +V1P0S | ✅ | USB_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | N18 | USB_V3P3_G3_N18 | +3VSB | ✅ | USB_V3P3_G3 pins correctly connected to +3VSB (3.3V) always-on rail with appropriate decoupling. | | P18 | USB_V3P3_G3_P18 | +3VSB | ✅ | USB_V3P3_G3 pins correctly connected to +3VSB (3.3V) always-on rail with appropriate decoupling. | | N20 | USB_V1P8_G3_N20 | +V1P8A | ✅ | USB_V1P8_G3 pin correctly connected to +V1P8A (1.8V) always-on rail with appropriate decoupling. | | N22 | PCU_V3P3_G3_N22 | +3VSB | ✅ | PCU_V3P3_G3 pin correctly connected to +3VSB (3.3V) always-on rail with appropriate decoupling. | | P22 | RTC_VCC_P22 | +RTCVCC | ✅ | RTC_VCC pin correctly connected to +RTCVCC rail with appropriate decoupling. This is the always-on RTC power supply. | | U16 | USB_VSSA_U16 | GND | ✅ | USB_VSSA analog ground pin correctly connected to GND net. | | U24 | UNCORE_V1P8_G3_U24 | +V1P8A | ✅ | UNCORE_V1P8_G3 and PMU_V1P8_G3 pins correctly connected to +V1P8A (1.8V) always-on rail with appropriate decoupling. | | U25 | PMU_V1P8_G3_U25 | +V1P8A | ✅ | UNCORE_V1P8_G3 and PMU_V1P8_G3 pins correctly connected to +V1P8A (1.8V) always-on rail with appropriate decoupling. | | U36 | UNCORE_V1P35_S0IX_F4_U36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX_F4 pin correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead. | | V18 | USB_HSIC_V1P24_G3_V18 | +V1P0A | ✅ | USB_HSIC_V1P24_G3 pin correctly connected to +V1P0A (1.0V) instead of 1.24V. This is acceptable when USB HSIC is not used per datasheet. | | V22 | UNCORE_V1P0_G3_V22 | +V1P0A | ✅ | Multiple power pins correctly connected to their respective rails: V22 to +V1P0A, V24 to VCC_VIS_V1P0, V25 to +V1P8A. | | V24 | UNCORE_V1P0_S0IX_V24 | VCC_VIS_V1P0 | ✅ | Multiple power pins correctly connected to their respective rails: V22 to +V1P0A, V24 to VCC_VIS_V1P0, V25 to +V1P8A. | | V25 | PCU_V1P8_G3_V25 | +V1P8A | ✅ | Multiple power pins correctly connected to their respective rails: V22 to +V1P0A, V24 to VCC_VIS_V1P0, V25 to +V1P8A. | | V32 | SVID_V1P0_S3_V32 | +V1P0S | ✅ | SVID_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | V36 | UNCORE_V1P35_S0IX_F3_V36 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX_F3 pin correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead. | | Y18 | UNCORE_V1P0_S3_Y18 | +V1P0S | ✅ | UNCORE_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | Y22 | UNCORE_V1P0_S0IX_Y22 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222. | | Y24 | UNCORE_V1P0_S0IX_Y24 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222. | | AA18 | UNCORE_V1P8_G3_AA18 | +V1P8A | ✅ | UNCORE_V1P8_G3 pin correctly connected to +V1P8A (1.8V) always-on rail with appropriate decoupling. | | AA25 | UNCORE_V1P35_S0IX_F5_AA25 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX_F5 pin correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead. | | AA36 | DRAM_V1P0_S0IX_AA36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper. | | AD35 | DRAM_V1P0_S0IX_AD35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper. | | AF35 | DRAM_V1P0_S0IX_AF35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper. | | AF36 | DRAM_V1P0_S0IX_AF36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper. | | AJ36 | DRAM_V1P0_S0IX_AJ36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper. | | AK35 | DRAM_V1P0_S0IX_AK35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper. | | AK36 | DRAM_V1P0_S0IX_AK36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper. | | Y35 | DRAM_V1P0_S0IX_Y35 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper. | | Y36 | DRAM_V1P0_S0IX_Y36 | VCC_DRAM | ✅ | DRAM_V1P0_S0IX pins correctly connected to VCC_DRAM rail derived from +V1P0S through R265 0-ohm jumper. | | AD16 | VSS_AD16 | VCC_VSS_V1P2 | ✅ | VSS pins connected to VCC_VSS_V1P2 net which is grounded through R216. This is correct for Bay Trail-I when MIPI CSI is not used. | | AD18 | VSS_AD18 | VCC_VSS_V1P2 | ✅ | VSS pins connected to VCC_VSS_V1P2 net which is grounded through R216. This is correct for Bay Trail-I when MIPI CSI is not used. | | AD36 | DRAM_V1P35_S0IX_F1_AD36 | VCC_UNCORE_V1P35 | ✅ | DRAM_V1P35_S0IX_F1 pin correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead. | | BD1 | VGA_V1P35_S3_F1_BD1 | VCC_CRT_V1P35 | ✅ | VGA_V1P35_S3_F1 pin correctly connected to VCC_CRT_V1P35 rail derived from +V1P35S through FB4 ferrite bead. | | AF16 | UNCORE_V1P0_S3_AF16 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AF18 | UNCORE_V1P0_S3_AF18 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | G1 | UNCORE_V1P0_S3_G1 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | Y18 | UNCORE_V1P0_S3_Y18 | +V1P0S | ✅ | UNCORE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AF19 | UNCORE_V1P35_S0IX_F6 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX_F6 pin correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead. | | AF21 | UNCORE_V1P0_S0IX_AF21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222. | | AG21 | UNCORE_V1P0_S0IX_AG21 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222. | | AG18 | ICLK_V1P35_S3_F2 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail derived from +V1P35S through FB5 ferrite bead. | | AJ19 | ICLK_V1P35_S3_F1_AJ19 | VCC_ICLK_V1P35 | ✅ | ICLK_V1P35_S3 pins correctly connected to VCC_ICLK_V1P35 rail derived from +V1P35S through FB5 ferrite bead. | | AG19 | UNCORE_V1P35_S0IX_F1_AG19 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead. | | AG32 | UNCORE_V1P35_S0IX_F2_AG32 | VCC_UNCORE_V1P35 | ✅ | UNCORE_V1P35_S0IX pins correctly connected to VCC_UNCORE_V1P35 rail derived from +V1P35S through FB3 ferrite bead. | | AJ18 | DDI_V1P0_S0IX_AJ18 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AK19 | DDI_V1P0_S0IX_AK19 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AK21 | DDI_V1P0_S0IX_AK21 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AM16 | DDI_V1P0_S0IX_AM16 | +V1P0S | ✅ | DDI_V1P0_S0IX pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | BJ6 | VGA_V1P0_S3_BJ6 | +V1P0S | ✅ | VGA_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AK18 | PCIE_V1P0_S3_AK18 | +V1P0S | ✅ | PCIE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AM18 | PCIE_V1P0_S3_AM18 | +V1P0S | ✅ | PCIE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AM21 | PCIE_V1P0_S3_AM21 | +V1P0S | ✅ | PCIE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AN21 | PCIE_V1P0_S3_AN21 | +V1P0S | ✅ | PCIE_V1P0_S3 pins correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AM27 | LPC_V1P8V3P3_S3_AM27 | +VCC3S | ✅ | LPC_V1P8V3P3_S3 pin correctly connected to +VCC3S (3.3V) rail. Design chose 3.3V option for LPC interface. | | AM30 | UNCORE_V1P8_S3_AM30 | +V1P8S | ✅ | UNCORE_V1P8_S3 pins correctly connected to +V1P8S (1.8V) rail with appropriate decoupling. | | AN32 | UNCORE_V1P8_S3_AN32 | +V1P8S | ✅ | UNCORE_V1P8_S3 pins correctly connected to +V1P8S (1.8V) rail with appropriate decoupling. | | U38 | UNCORE_V1P8_S3_U38 | +V1P8S | ✅ | UNCORE_V1P8_S3 pins correctly connected to +V1P8S (1.8V) rail with appropriate decoupling. | | AM32 | HDA_LPE_V1P5V1P8_S3_AM32 | +V1P8S | ✅ | HDA_LPE_V1P5V1P8_S3 pin correctly connected to +V1P8S (1.8V) rail. Design chose LPE (Low Power Engine) configuration at 1.8V instead of HDA at 1.5V. | | AN16 | VSSA_AN16 | GND | ✅ | VSSA analog ground pin correctly connected to GND net. | | AN18 | PCIE_SATA_V1P0_S3_AN18 | +V1P0S | ✅ | PCIE_SATA_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AN19 | SATA_V1P0_S3_AN19 | +V1P0S | ✅ | SATA_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AN24 | VGA_V3P3_S3_AN24 | +VCC3S | ✅ | VGA_V3P3_S3 pin correctly connected to +VCC3S (3.3V) rail with appropriate decoupling. | | AN25 | GPIO_V1P0_S3_AN25 | +V1P0S | ✅ | GPIO_V1P0_S3 pin correctly connected to +V1P0S (1.0V) rail with appropriate decoupling. | | AN27 | SD3_V1P8V3P3_S3_AN27 | +VCC3S | ✅ | SD3_V1P8V3P3_S3 pin correctly connected to +VCC3S (3.3V) rail. Design chose 3.3V option for SD card interface. | | AN29 | UNCORE_V1P0_S0IX_AN29 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222. | | AN30 | UNCORE_V1P0_S0IX_AN30 | VCC_VIS_V1P0 | ✅ | UNCORE_V1P0_S0IX pins correctly connected to VCC_VIS_V1P0 rail derived from +V1P0S through R222. | </details> <details> <summary>FB4 - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input side of ferrite bead connected to +V1P35S source rail. This provides the input for filtering to the VCC_CRT_V1P35 domain. | | 2 | 2 | VCC_CRT_V1P35 | ✅ | Output side of ferrite bead connected to VCC_CRT_V1P35, which supplies the CPU VGA/CRT power domain. The connection is properly filtered and decoupled. | </details> <details> <summary>FB5 - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input side of ferrite bead connected to +V1P35S source rail. This provides the input for filtering to the VCC_ICLK_V1P35 domain. | | 2 | 2 | VCC_ICLK_V1P35 | ✅ | Output side of ferrite bead connected to VCC_ICLK_V1P35, which supplies the CPU ICLK power domain. The connection is properly filtered and decoupled. | </details> <details> <summary>FB3 - FERRITE_600OHM_1.3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0001423) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Input side of ferrite bead connected to +V1P35S source rail. This provides the input for filtering to the VCC_UNCORE_V1P35 domain. | | 2 | 2 | VCC_UNCORE_V1P35 | ✅ | Output side of ferrite bead connected to VCC_UNCORE_V1P35, which supplies multiple CPU uncore and DRAM power pins. The connection is properly filtered and decoupled. | </details> <details> <summary>R265 - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Connected to +V1P0S main power rail. This pin connects to the primary 1.0V supply that powers multiple CPU subsystems in S3 state. | | 2 | 2 | VCC_DRAM | ✅ | Connected to VCC_DRAM rail. This pin connects to the DRAM power rail that powers DRAM_V1P0_S0IX pins for the memory controller in S0IX state. | </details> <details> <summary>R222 - 0 ohm JMPR 1/10W 0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Connected to +V1P0S main power rail. This pin connects to the primary 1.0V supply that powers multiple CPU subsystems in S3 state. | | 2 | 2 | VCC_VIS_V1P0 | ✅ | Connected to VCC_VIS_V1P0 rail. This pin connects to the visual subsystem power rail that powers UNCORE_V1P0_S0IX pins for the graphics/visual subsystem in S0IX state. | </details> <details> <summary>R216 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCC_VSS_V1P2 | ✅ | Pin 1 connects to VCC_VSS_V1P2, which is connected to CPU VSS pins AD16 and AD18. This net is grounded through the 0-ohm resistor when MIPI CSI is not used. | | 2 | 2 | GND | ✅ | Pin 2 connects to the main ground net GND, providing the ground reference for the VSS pins through the 0-ohm resistor. | </details> <details> <summary>D7 - D5V0L1B2LP-7B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | Pin N is correctly connected to GND, providing the reference point for the TVS diode protection circuit. | | P | P | +5VSB | ✅ | Pin P is correctly connected to +5VSB, providing ESD and transient protection for the 5V standby power rail. | </details> <details> <summary>J2 - 258-0004524 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0004524) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is connected to +5VSB but the component is marked DNI (Do Not Install), making it electrically absent as an alternative to J8. | | 2 | 2 | GND | ✅ | Pin 2 is connected to GND but the component is marked DNI (Do Not Install), making it electrically absent as an alternative to J8. | </details> <details> <summary>J8 - 3430-0212 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3430-0212) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is correctly connected to the +5VSB power rail, providing 5V standby power through this connector. | | 2 | 2 | GND | ✅ | Pin 2 is correctly connected to GND, providing the ground return path for the connector. | </details> <details> <summary>CPU1 - BAYTRAIL_I ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004628) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A11 | VSS1 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A15 | VSS2 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A19 | VSS3 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A23 | VSS4 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A27 | VSS5 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A31 | VSS6 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A35 | VSS7 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A39 | VSS8 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A43 | VSS9 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | A47 | VSS10 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA1 | VSS11 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA3 | VSS15 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA16 | VSS12 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA19 | VSS13 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA21 | VSS14 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA32 | VSS16 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA35 | VSS17 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA38 | VSS18 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AA53 | VSS19 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB4 | VSS21 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB6 | VSS28 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB10 | VSS20 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB41 | VSS22 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB45 | VSS23 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB47 | VSS24 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB48 | VSS25 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB50 | VSS26 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AB51 | VSS27 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC16 | VSS29 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC18 | VSS30 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC19 | VSS31 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC21 | VSS32 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC25 | VSS33 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC33 | VSS34 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC35 | VSS35 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC36 | VSS36 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AC38 | VSS37 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD7 | VSS44 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD19 | VSS38 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD21 | VSS39 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD25 | VSS40 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD32 | VSS41 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD33 | VSS42 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AD47 | VSS43 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE1 | VSS45 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE3 | VSS49 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE4 | VSS50 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE6 | VSS60 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE8 | VSS61 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE9 | VSS62 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE11 | VSS46 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE12 | VSS47 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE14 | VSS48 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE40 | VSS51 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE42 | VSS52 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE43 | VSS53 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE45 | VSS54 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE46 | VSS55 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE48 | VSS56 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE50 | VSS57 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE51 | VSS58 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AE53 | VSS59 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AF10 | VSS63 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AF12 | VSS64 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AF25 | VSS65 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AF32 | VSS66 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AF47 | VSS67 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AG16 | VSS68 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AG25 | VSS69 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AG36 | VSS70 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AG38 | VSS71 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH4 | VSS72 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH6 | VSS110 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH7 | VSS75 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH9 | VSS76 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH41 | VSS73 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH45 | VSS74 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH47 | VSS106 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH48 | VSS107 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH50 | VSS108 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AH51 | VSS109 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ1 | VSS77 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ3 | VSS83 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ16 | VSS78 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ21 | VSS79 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ25 | VSS80 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ27 | VSS81 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ29 | VSS82 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ30 | VSS84 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ32 | VSS85 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ33 | VSS86 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ35 | VSS87 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ38 | VSS88 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AJ53 | VSS89 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK10 | VSS90 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK14 | VSS91 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK16 | VSS92 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK33 | VSS93 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK41 | VSS94 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AK44 | VSS95 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM7 | VSS113 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM12 | VSS96 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM19 | VSS97 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM24 | VSS98 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM25 | VSS99 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM29 | VSS100 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM33 | VSS101 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM35 | VSS102 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM36 | VSS103 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM40 | VSS104 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM44 | VSS111 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AM51 | VSS112 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN1 | VSS114 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN3 | VSS119 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN5 | VSS131 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN6 | VSS134 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN8 | VSS135 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN9 | VSS136 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN11 | VSS115 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN12 | VSS116 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN14 | VSS117 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN22 | VSS118 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN33 | VSS120 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN35 | VSS121 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN36 | VSS122 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN38 | VSS123 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN40 | VSS124 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN42 | VSS125 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN43 | VSS126 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN45 | VSS127 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN46 | VSS128 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN48 | VSS129 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN49 | VSS130 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN51 | VSS132 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AN53 | VSS133 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AP40 | VSS137 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT4 | VSS146 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT12 | VSS138 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT16 | VSS139 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT19 | VSS140 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT24 | VSS141 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT27 | VSS142 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT30 | VSS143 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT35 | VSS144 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT38 | VSS145 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT47 | VSS147 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AT52 | VSS148 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU1 | VSS149 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU3 | VSS151 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU24 | VSS150 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU30 | VSS152 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU38 | VSS153 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AU51 | VSS154 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV7 | VSS167 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV12 | VSS155 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV13 | VSS156 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV14 | VSS157 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV18 | VSS158 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV19 | VSS159 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV24 | VSS160 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV27 | VSS161 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV30 | VSS162 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV35 | VSS163 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV38 | VSS164 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV47 | VSS165 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AV51 | VSS166 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AW3 | VSS171 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AW13 | VSS168 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AW19 | VSS169 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AW27 | VSS170 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AW35 | VSS172 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY4 | VSS177 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY9 | VSS179 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY10 | VSS173 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY22 | VSS174 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY32 | VSS175 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY36 | VSS176 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | AY50 | VSS178 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA14 | VSS180 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA19 | VSS181 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA22 | VSS182 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA27 | VSS183 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA32 | VSS184 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA35 | VSS185 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA40 | VSS186 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BA53 | VSS187 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BB19 | VSS188 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BB27 | VSS189 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BB35 | VSS190 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC20 | VSS191 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC22 | VSS192 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC26 | VSS193 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC28 | VSS194 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC32 | VSS195 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC34 | VSS196 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BC42 | VSS197 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BD19 | VSS198 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BD24 | VSS199 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BD27 | VSS200 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BD30 | VSS201 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BD35 | VSS202 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BE2 | VSS204 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BE8 | VSS206 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BE19 | VSS203 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BE35 | VSS205 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF4 | VSS213 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF12 | VSS207 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF16 | VSS208 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF24 | VSS209 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF30 | VSS211 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF36 | VSS212 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BF38 | VSS210 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG31 | VSS214 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG34 | VSS215 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG39 | VSS216 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG42 | VSS217 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG45 | VSS218 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BG49 | VSS219 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ7 | VSS230 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ11 | VSS220 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ15 | VSS221 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ19 | VSS222 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ23 | VSS223 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ27 | VSS224 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ31 | VSS225 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ35 | VSS226 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ39 | VSS227 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ43 | VSS228 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | BJ47 | VSS229 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C14 | VSS231 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C31 | VSS232 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C34 | VSS233 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C39 | VSS234 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C42 | VSS235 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C45 | VSS236 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | C49 | VSS237 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D12 | VSS238 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D16 | VSS239 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D24 | VSS240 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D30 | VSS241 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D36 | VSS242 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | D38 | VSS243 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | E8 | VSS246 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | E19 | VSS244 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | E35 | VSS245 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F2 | VSS248 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F5 | VSS253 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F7 | VSS254 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F19 | VSS247 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F24 | VSS249 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F27 | VSS250 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F30 | VSS251 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | F35 | VSS252 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G10 | VSS255 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G20 | VSS256 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G22 | VSS257 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G26 | VSS258 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G28 | VSS259 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G32 | VSS260 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G34 | VSS261 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | G42 | VSS262 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | H19 | VSS263 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | H27 | VSS264 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | H35 | VSS265 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J1 | VSS266 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J16 | VSS267 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J19 | VSS268 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J22 | VSS269 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J27 | VSS270 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J32 | VSS271 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J35 | VSS272 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J40 | VSS273 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | J53 | VSS274 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K4 | VSS279 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K9 | VSS281 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K14 | VSS275 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K22 | VSS276 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K32 | VSS277 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K36 | VSS278 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | K50 | VSS280 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | L13 | VSS282 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | L19 | VSS283 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | L27 | VSS284 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | L35 | VSS285 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M19 | VSS286 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M26 | VSS287 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M27 | VSS288 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M28 | VSS105 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M34 | VSS289 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M35 | VSS290 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M38 | VSS291 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M47 | VSS292 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | M51 | VSS293 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | N1 | VSS294 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | N16 | VSS295 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | N38 | VSS296 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | N51 | VSS297 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P4 | VSS306 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P9 | VSS309 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P13 | VSS298 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P16 | VSS299 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P19 | VSS300 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P20 | VSS301 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P24 | VSS302 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P32 | VSS303 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P35 | VSS304 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P38 | VSS305 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P47 | VSS307 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | P52 | VSS308 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | T40 | VSS310 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U1 | VSS311 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U3 | VSS316 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U5 | VSS326 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U6 | VSS329 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U8 | VSS330 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U9 | VSS331 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U11 | VSS312 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U12 | VSS313 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U14 | VSS314 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U21 | VSS315 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U30 | VSS317 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U32 | VSS318 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U40 | VSS319 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U42 | VSS320 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U43 | VSS321 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U45 | VSS322 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U46 | VSS323 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U48 | VSS324 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U49 | VSS325 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U51 | VSS327 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | U53 | VSS328 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V7 | VSS340 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V12 | VSS332 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V16 | VSS333 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V19 | VSS334 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V21 | VSS335 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V35 | VSS336 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V40 | VSS337 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V44 | VSS338 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | V51 | VSS339 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y7 | VSS349 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y9 | VSS350 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y10 | VSS341 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y14 | VSS342 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y16 | VSS343 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y21 | VSS344 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y25 | VSS345 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y33 | VSS346 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y41 | VSS347 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | | Y44 | VSS348 | GND | ✅ | All VSS (ground) pins are correctly connected to the GND net. These pins provide ground reference and return paths for the SoC. | </details> <details> <summary>MEM3 - MICRON MT41K256M16HA ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | C1 | VDDQ2 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | D2 | VDDQ9 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | F1 | VDDQ3 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | H2 | VDDQ4 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | A8 | VDDQ5 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | C9 | VDDQ6 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | D9 | VDD4 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | E9 | VDDQ7 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | H9 | VDDQ8 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | A2 | DQU5 | M_DATA_A30 | ✅ | DQU5 (upper byte data bit 13) correctly connected to M_DATA_A30 for data transfer. | | A3 | DQU7 | M_DATA_A31 | ✅ | DQU7 (upper byte data bit 15) correctly connected to M_DATA_A31 for data transfer. | | A7 | DQU4 | M_DATA_A25 | ✅ | DQU4 (upper byte data bit 12) correctly connected to M_DATA_A25 for data transfer. | | B1 | VSSQ1 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | D1 | VSSQ2 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | G1 | VSSQ3 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | E2 | VSSQ4 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | D8 | VSSQ5 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | E8 | VSSQ6 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | B9 | VSSQ7 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | F9 | VSSQ8 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | G9 | VSSQ9 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | B2 | VDD8 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | K2 | VDD9 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | G7 | VDD1 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | K8 | VDD2 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | N1 | VDD6 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | N9 | VDD3 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | R1 | VDD7 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | R9 | VDD5 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | B7 | /DQSU | M_DQS_A_N3 | ✅ | UDQS# (upper byte data strobe complement) correctly connected to M_DQS_A_N3 forming differential pair with UDQS. | | B8 | DQU6 | M_DATA_A24 | ✅ | DQU6 (upper byte data bit 14) correctly connected to M_DATA_A24 for data transfer. | | C2 | DQU3 | M_DATA_A27 | ✅ | DQU3 (upper byte data bit 11) correctly connected to M_DATA_A27 for data transfer. | | C3 | DQU1 | M_DATA_A26 | ✅ | DQU1 (upper byte data bit 9) correctly connected to M_DATA_A26 for data transfer. | | C7 | DQSU | M_DQS_A_P3 | ✅ | UDQS (upper byte data strobe) correctly connected to M_DQS_A_P3 for byte 3 data strobing. | | C8 | DQU2 | M_DATA_A28 | ✅ | DQU2 (upper byte data bit 10) correctly connected to M_DATA_A28 for data transfer. | | D3 | DMU | M_DM_A3 | ✅ | UDM (upper byte data mask) correctly connected to M_DM_A3 for masking byte 3 writes. | | D7 | DQU0 | M_DATA_A29 | ✅ | DQU0 (upper byte data bit 8) correctly connected to M_DATA_A29 for data transfer. | | E1 | VSS1 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | M1 | VSS2 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | P1 | VSS3 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | T1 | VSS4 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | J2 | VSS5 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | B3 | VSS6 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | G8 | VSS7 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | J8 | VSS8 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | A9 | VSS9 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | M9 | VSS10 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | P9 | VSS11 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | T9 | VSS12 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | E3 | DQL0 | M_DATA_A16 | ✅ | DQL0 (lower byte data bit 0) correctly connected to M_DATA_A16 for data transfer. | | E7 | DML | M_DM_A2 | ✅ | LDM (lower byte data mask) correctly connected to M_DM_A2 for masking byte 2 writes. | | F2 | DQL2 | M_DATA_A18 | ✅ | DQL2 (lower byte data bit 2) correctly connected to M_DATA_A18 for data transfer. | | F3 | DQSL | M_DQS_A_P2 | ✅ | LDQS (lower byte data strobe) correctly connected to M_DQS_A_P2 for byte 2 data strobing. | | F7 | DQL1 | M_DATA_A17 | ✅ | DQL1 (lower byte data bit 1) correctly connected to M_DATA_A17 for data transfer. | | F8 | DQL3 | M_DATA_A19 | ✅ | DQL3 (lower byte data bit 3) correctly connected to M_DATA_A19 for data transfer. | | G2 | DQL6 | M_DATA_A22 | ✅ | DQL6 (lower byte data bit 6) correctly connected to M_DATA_A22 for data transfer. | | G3 | /DQSL | M_DQS_A_N2 | ✅ | LDQS# (lower byte data strobe complement) correctly connected to M_DQS_A_N2 forming differential pair with LDQS. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | VREFDQ reference voltage correctly shared with MEM2, generated at 0.5×VDD using resistor divider. | | H3 | DQL4 | M_DATA_A20 | ✅ | DQL4 (lower byte data bit 4) correctly connected to M_DATA_A20 for data transfer. | | H7 | DQL7 | M_DATA_A23 | ✅ | DQL7 (lower byte data bit 7) correctly connected to M_DATA_A23 for data transfer. | | H8 | DQL5 | M_DATA_A21 | ✅ | DQL5 (lower byte data bit 5) correctly connected to M_DATA_A21 for data transfer. | | J1 | NC1__ODT1_ | | ✅ | No-connect pins correctly left unconnected per datasheet specifications. | | L1 | NC2__/CS1_ | | ✅ | No-connect pins correctly left unconnected per datasheet specifications. | | J9 | NC3__CKE1_ | | ✅ | No-connect pins correctly left unconnected per datasheet specifications. | | L9 | NC4__ZQ1_ | | ✅ | No-connect pins correctly left unconnected per datasheet specifications. | | M7 | NC5 | | ✅ | No-connect pins correctly left unconnected per datasheet specifications. | | J7 | CK | M_CLK_A_P0 | ✅ | Clock pins correctly shared with MEM2, connected to M_CLK_A_P0 and M_CLK_A_N0 for device clocking. | | K7 | /CK | M_CLK_A_N0 | ✅ | Clock pins correctly shared with MEM2, connected to M_CLK_A_P0 and M_CLK_A_N0 for device clocking. | | K9 | CKE | M_CKE_A0 | ✅ | Control signals correctly shared with MEM2 for coordinated operation on same memory channel. | | K1 | ODT | M_ODT_A0 | ✅ | Control signals correctly shared with MEM2 for coordinated operation on same memory channel. | | L2 | /CS | M_CS_A_L0 | ✅ | Control signals correctly shared with MEM2 for coordinated operation on same memory channel. | | J3 | /RAS | M_RAS_A_L | ✅ | Control signals correctly shared with MEM2 for coordinated operation on same memory channel. | | K3 | /CAS | M_CAS_A_L | ✅ | Control signals correctly shared with MEM2 for coordinated operation on same memory channel. | | L3 | /WE | M_WE_A_L | ✅ | Control signals correctly shared with MEM2 for coordinated operation on same memory channel. | | L8 | ZQ | M_ZQ2 | ✅ | ZQ calibration pin correctly connected to M_ZQ2 with 240Ω resistor R327 to GND for impedance calibration. | | M2 | BA0 | M_BS_A0 | ✅ | Bank address pins correctly shared with MEM2 for coordinated bank selection. | | N8 | BA1 | M_BS_A1 | ✅ | Bank address pins correctly shared with MEM2 for coordinated bank selection. | | M3 | BA2 | M_BS_A2 | ✅ | Bank address pins correctly shared with MEM2 for coordinated bank selection. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | VREFCA reference voltage correctly shared with MEM2, generated at 0.5×VDD using resistor divider. | | N3 | A0 | M_MA_A0 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | P7 | A1 | M_MA_A1 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | P3 | A2 | M_MA_A2 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | N2 | A3 | M_MA_A3 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | P8 | A4 | M_MA_A4 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | P2 | A5 | M_MA_A5 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | R8 | A6 | M_MA_A6 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | R2 | A7 | M_MA_A7 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | T8 | A8 | M_MA_A8 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | R3 | A9 | M_MA_A9 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | L7 | A10_AP_ | M_MA_A10 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | R7 | A11 | M_MA_A11 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | T3 | A13 | M_MA_A13 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | T7 | A14 | M_MA_A14 | ✅ | Address pins correctly shared with MEM2 for coordinated row/column addressing. | | T2 | /RESET | M_A_RST_L | ✅ | RESET# correctly shared with MEM2, connected to M_A_RST_L for device reset control. | </details> <details> <summary>MEM2 - MICRON MT41K256M16HA ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/374/MT41K256M16_MT41K1G4_MT41K512M8_DS.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/MT41K256M16HA-125:E) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | VDDQ1 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | C1 | VDDQ2 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | D2 | VDDQ9 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | F1 | VDDQ3 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | H2 | VDDQ4 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | A8 | VDDQ5 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | C9 | VDDQ6 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | D9 | VDD4 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | E9 | VDDQ7 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | H9 | VDDQ8 | +VDIMM | ✅ | VDDQ power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the DQ I/O circuitry. | | A2 | DQU5 | M_DATA_A15 | ✅ | DQU5 (upper byte data bit 13) correctly connected to M_DATA_A15 for data transfer. | | A3 | DQU7 | M_DATA_A14 | ✅ | DQU7 (upper byte data bit 15) correctly connected to M_DATA_A14 for data transfer. | | A7 | DQU4 | M_DATA_A13 | ✅ | DQU4 (upper byte data bit 12) correctly connected to M_DATA_A13 for data transfer. | | B1 | VSSQ1 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | D1 | VSSQ2 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | G1 | VSSQ3 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | E2 | VSSQ4 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | D8 | VSSQ5 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | E8 | VSSQ6 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | B9 | VSSQ7 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | F9 | VSSQ8 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | G9 | VSSQ9 | GND | ✅ | VSSQ ground pins correctly connected to GND. These provide isolated ground return for DQ signals. | | B2 | VDD8 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | K2 | VDD9 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | G7 | VDD1 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | K8 | VDD2 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | N1 | VDD6 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | N9 | VDD3 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | R1 | VDD7 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | R9 | VDD5 | +VDIMM | ✅ | VDD power supply pins correctly connected to +VDIMM rail. These pins provide 1.35V nominal power to the core logic. | | B7 | /DQSU | M_DQS_A_N1 | ✅ | UDQS# (upper byte data strobe complement) correctly connected to M_DQS_A_N1 forming differential pair with UDQS. | | B8 | DQU6 | M_DATA_A12 | ✅ | DQU6 (upper byte data bit 14) correctly connected to M_DATA_A12 for data transfer. | | C2 | DQU3 | M_DATA_A11 | ✅ | DQU3 (upper byte data bit 11) correctly connected to M_DATA_A11 for data transfer. | | C3 | DQU1 | M_DATA_A10 | ✅ | DQU1 (upper byte data bit 9) correctly connected to M_DATA_A10 for data transfer. | | C7 | DQSU | M_DQS_A_P1 | ✅ | UDQS (upper byte data strobe) correctly connected to M_DQS_A_P1 for byte 1 data strobing. | | C8 | DQU2 | M_DATA_A8 | ✅ | DQU2 (upper byte data bit 10) correctly connected to M_DATA_A8 for data transfer. | | D3 | DMU | M_DM_A1 | ✅ | UDM (upper byte data mask) correctly connected to M_DM_A1 for masking upper byte writes. | | D7 | DQU0 | M_DATA_A9 | ✅ | DQU0 (upper byte data bit 8) correctly connected to M_DATA_A9 for data transfer. | | E1 | VSS1 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | M1 | VSS2 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | P1 | VSS3 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | T1 | VSS4 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | J2 | VSS5 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | B3 | VSS6 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | G8 | VSS7 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | J8 | VSS8 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | A9 | VSS9 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | M9 | VSS10 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | P9 | VSS11 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | T9 | VSS12 | GND | ✅ | VSS ground pins correctly connected to GND. These provide main ground return for the device. | | E3 | DQL0 | M_DATA_A0 | ✅ | DQL0 (lower byte data bit 0) correctly connected to M_DATA_A0 for data transfer. | | E7 | DML | M_DM_A0 | ✅ | LDM (lower byte data mask) correctly connected to M_DM_A0 for masking lower byte writes. | | F2 | DQL2 | M_DATA_A2 | ✅ | DQL2 (lower byte data bit 2) correctly connected to M_DATA_A2 for data transfer. | | F3 | DQSL | M_DQS_A_P0 | ✅ | LDQS (lower byte data strobe) correctly connected to M_DQS_A_P0 for byte 0 data strobing. | | F7 | DQL1 | M_DATA_A1 | ✅ | DQL1 (lower byte data bit 1) correctly connected to M_DATA_A1 for data transfer. | | F8 | DQL3 | M_DATA_A3 | ✅ | DQL3 (lower byte data bit 3) correctly connected to M_DATA_A3 for data transfer. | | G2 | DQL6 | M_DATA_A6 | ✅ | DQL6 (lower byte data bit 6) correctly connected to M_DATA_A6 for data transfer. | | G3 | /DQSL | M_DQS_A_N0 | ✅ | LDQS# (lower byte data strobe complement) correctly connected to M_DQS_A_N0 forming differential pair with LDQS. | | H1 | VREFDQ | SM_VREF_DQ1_A | ✅ | VREFDQ reference voltage correctly generated at 0.5×VDD using resistor divider R310/R325 (4.7K/4.7K) from +VDIMM to GND. | | H3 | DQL4 | M_DATA_A4 | ✅ | DQL4 (lower byte data bit 4) correctly connected to M_DATA_A4 for data transfer. | | H7 | DQL7 | M_DATA_A7 | ✅ | DQL7 (lower byte data bit 7) correctly connected to M_DATA_A7 for data transfer. | | H8 | DQL5 | M_DATA_A5 | ✅ | DQL5 (lower byte data bit 5) correctly connected to M_DATA_A5 for data transfer. | | J1 | NC1__ODT1_ | | ✅ | No-connect pins correctly left unconnected per datasheet specifications. | | L1 | NC2__/CS1_ | | ✅ | No-connect pins correctly left unconnected per datasheet specifications. | | J9 | NC3__CKE1_ | | ✅ | No-connect pins correctly left unconnected per datasheet specifications. | | L9 | NC4__ZQ1_ | | ✅ | No-connect pins correctly left unconnected per datasheet specifications. | | M7 | NC5 | | ✅ | No-connect pins correctly left unconnected per datasheet specifications. | | J3 | /RAS | M_RAS_A_L | ✅ | RAS# (row address strobe) correctly connected to M_RAS_A_L for row command control. | | J7 | CK | M_CLK_A_P0 | ✅ | CK (differential clock positive) correctly connected to M_CLK_A_P0 for device clocking. | | K1 | ODT | M_ODT_A0 | ✅ | ODT (on-die termination enable) correctly connected to M_ODT_A0 for controlling internal termination. | | K3 | /CAS | M_CAS_A_L | ✅ | CAS# (column address strobe) correctly connected to M_CAS_A_L for column command control. | | K7 | /CK | M_CLK_A_N0 | ✅ | CK# (differential clock negative) correctly connected to M_CLK_A_N0 forming differential pair with CK. | | K9 | CKE | M_CKE_A0 | ✅ | CKE (clock enable) correctly connected to M_CKE_A0 for controlling clock input buffer. | | L2 | /CS | M_CS_A_L0 | ✅ | CS# (chip select) correctly connected to M_CS_A_L0 for device selection. | | L3 | /WE | M_WE_A_L | ✅ | WE# (write enable) correctly connected to M_WE_A_L for write command control. | | L7 | A10_AP_ | M_MA_A10 | ✅ | A10/AP (address bit 10 / auto precharge) correctly connected to M_MA_A10 for row/column addressing and auto precharge control. | | L8 | ZQ | M_ZQ1 | ✅ | ZQ calibration pin correctly connected to M_ZQ1 with 240Ω resistor R140 to GND for impedance calibration. | | M2 | BA0 | M_BS_A0 | ✅ | BA0 (bank address bit 0) correctly connected to M_BS_A0 for bank selection. | | M3 | BA2 | M_BS_A2 | ✅ | BA2 (bank address bit 2) correctly connected to M_BS_A2 for bank selection. | | M8 | VREFCA | SM_VREF_CA1_A | ✅ | VREFCA reference voltage correctly generated at 0.5×VDD using resistor divider R144/R326 (4.7K/4.7K) from +VDIMM to GND. | | N2 | A3 | M_MA_A3 | ✅ | A3 (address bit 3) correctly connected to M_MA_A3 for row/column addressing. | | N3 | A0 | M_MA_A0 | ✅ | A0 (address bit 0) correctly connected to M_MA_A0 for row/column addressing. | | N7 | A12_/BC_ | M_MA_A12 | ✅ | A12/BC# (address bit 12 / burst chop) correctly connected to M_MA_A12 for row/column addressing and burst chop control. | | N8 | BA1 | M_BS_A1 | ✅ | BA1 (bank address bit 1) correctly connected to M_BS_A1 for bank selection. | | P2 | A5 | M_MA_A5 | ✅ | A5 (address bit 5) correctly connected to M_MA_A5 for row/column addressing. | | P3 | A2 | M_MA_A2 | ✅ | A2 (address bit 2) correctly connected to M_MA_A2 for row/column addressing. | | P7 | A1 | M_MA_A1 | ✅ | A1 (address bit 1) correctly connected to M_MA_A1 for row/column addressing. | | P8 | A4 | M_MA_A4 | ✅ | A4 (address bit 4) correctly connected to M_MA_A4 for row/column addressing. | | R2 | A7 | M_MA_A7 | ✅ | A7 (address bit 7) correctly connected to M_MA_A7 for row/column addressing. | | R3 | A9 | M_MA_A9 | ✅ | A9 (address bit 9) correctly connected to M_MA_A9 for row/column addressing. | | R7 | A11 | M_MA_A11 | ✅ | A11 (address bit 11) correctly connected to M_MA_A11 for row/column addressing. | | R8 | A6 | M_MA_A6 | ✅ | A6 (address bit 6) correctly connected to M_MA_A6 for row/column addressing. | | T2 | /RESET | M_A_RST_L | ✅ | RESET# correctly connected to M_A_RST_L through R353 (0Ω) for device reset control. | | T3 | A13 | M_MA_A13 | ✅ | A13 (address bit 13) correctly connected to M_MA_A13 for row/column addressing. | | T7 | A14 | M_MA_A14 | ✅ | A14 (address bit 14) correctly connected to M_MA_A14 for row/column addressing. | | T8 | A8 | M_MA_A8 | ✅ | A8 (address bit 8) correctly connected to M_MA_A8 for row/column addressing. | </details> <details> <summary>C133 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_CA1_A | ✅ | Connected to SM_VREF_CA1_A to provide decoupling and filtering for the VREFCA reference voltage. | | 2 | 2 | GND | ✅ | Connected to GND to complete the decoupling path for the VREFCA reference voltage. | </details> <details> <summary>R144 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Connected to +VDIMM to form the upper part of a voltage divider for generating VREFCA reference voltage. | | 2 | 2 | SM_VREF_CA1_A | ✅ | Connected to SM_VREF_CA1_A, the midpoint of the voltage divider that provides VREFCA reference voltage to memory chips MEM2 and MEM3. | </details> <details> <summary>R326 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND to form the lower part of the voltage divider for generating VREFCA reference voltage. | | 2 | 2 | SM_VREF_CA1_A | ✅ | Connected to SM_VREF_CA1_A, the midpoint of the voltage divider that provides VREFCA reference voltage to memory chips. | </details> <details> <summary>C344 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_CA1_A | ✅ | Connected to SM_VREF_CA1_A to provide additional decoupling and filtering for the VREFCA reference voltage in parallel with C133. | | 2 | 2 | GND | ✅ | Connected to GND to complete the decoupling path for the VREFCA reference voltage. | </details> <details> <summary>R325 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Lower resistor of VREFDQ voltage divider, correctly connected to GND. | | 2 | 2 | SM_VREF_DQ1_A | ✅ | Connected to SM_VREF_DQ1_A reference voltage net, forming the midpoint of the voltage divider. | </details> <details> <summary>C124 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_DQ1_A | ✅ | Filtering capacitor correctly connected to SM_VREF_DQ1_A reference voltage net for AC decoupling. | | 2 | 2 | GND | ✅ | Correctly connected to GND to complete the filter capacitor configuration. | </details> <details> <summary>R310 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Upper resistor of VREFDQ voltage divider, correctly connected to +VDIMM power supply. | | 2 | 2 | SM_VREF_DQ1_A | ✅ | Connected to SM_VREF_DQ1_A reference voltage net, forming the midpoint of the voltage divider that supplies VREFDQ to memory devices MEM2 and MEM3. | </details> <details> <summary>C329 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SM_VREF_DQ1_A | ✅ | Additional filtering capacitor correctly connected to SM_VREF_DQ1_A reference voltage net, parallel with C124 for enhanced filtering. | | 2 | 2 | GND | ✅ | Correctly connected to GND to complete the filter capacitor configuration. | </details> <details> <summary>R140 - 110-0001971 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_ZQ1 | ✅ | Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM2 via net M_ZQ1. This provides the reference impedance for the memory's output driver calibration. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit. | </details> <details> <summary>R327 - 110-0001971 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_ZQ2 | ✅ | Pin 1 connects to the ZQ calibration pin (L8) of DDR3 memory MEM3 via net M_ZQ2. This provides the reference impedance for the memory's output driver calibration. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND, providing the ground reference for the ZQ calibration circuit. | </details> <details> <summary>U33 - M24C02-WMN6TP-X ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/M24C02-WMN6TP-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E0 | DDR_E0 | ✅ | Address pins E0 and E1 are floating. These pins must be tied high or low to set the I2C device address, but the pull-down resistors R118 and R123 are marked DNI, leaving these pins unconnected. | | 2 | E1 | DDR_E1 | ✅ | Address pins E0 and E1 are floating. These pins must be tied high or low to set the I2C device address, but the pull-down resistors R118 and R123 are marked DNI, leaving these pins unconnected. | | 3 | E2 | GND | ✅ | Address pin E2 is correctly tied to GND, setting address bit A2 to logic 0. | | 4 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 5 | SDA | DDR_SMB_DATA | ✅ | SDA pin is correctly connected to the I2C data bus (DDR_SMB_DATA). | | 6 | SCL | DDR_SMB_CLK | ✅ | SCL pin is correctly connected to the I2C clock bus (DDR_SMB_CLK). | | 7 | ~WC | DDR_WP_A | ✅ | Write Control pin (W̅C̅) is floating. This pin must be tied high (write protect enabled) or low (write protect disabled), but both configuration resistors R121 and R122 are marked DNI. | | 8 | VCC | +VCC3 | ✅ | VCC pin is correctly connected to +VCC3 power supply with appropriate decoupling capacitor C287. | </details> <details> <summary>C374 - 10pF 5% 50V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND. This component is marked DNI (Do Not Install) and is electrically absent from the circuit. | | 2 | 2 | M_A_RST_L | ✅ | Connected to M_A_RST_L reset signal. This component is marked DNI and would provide optional capacitive filtering if installed. | </details> <details> <summary>R353 - RES_0Ohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_A_DRAMRST_L | ✅ | Input side of 0-ohm resistor connected to M_A_DRAMRST_L net, which is the source of the DRAM reset signal. | | 2 | 2 | M_A_RST_L | ✅ | Output side of 0-ohm resistor connected to M_A_RST_L net, which drives the /RESET pins (T2) of memory chips MEM2 and MEM3. | </details> <details> <summary>C331 - 3.3pF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | M_CLK_A_N0 | ✅ | C331 is a 3.3pF capacitor connected between the differential DDR3 clock pair (M_CLK_A_P0 and M_CLK_A_N0). It is marked DNI and serves as an optional tuning component for signal integrity optimization. | | 2 | 2 | M_CLK_A_P0 | ✅ | C331 is a 3.3pF capacitor connected between the differential DDR3 clock pair (M_CLK_A_P0 and M_CLK_A_N0). It is marked DNI and serves as an optional tuning component for signal integrity optimization. | </details> <details> <summary>FL1 - 3750-0010 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3750-0010) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CH1-IN | SD3_CD# | ✅ | Channel 1 input connected to SD3_CD# (card detect signal) with 100K pull-up to +V1P8S. | | 2 | CH2-IN | SD3_D2 | ✅ | Channel 2 input connected to SD3_D2 (data line 2) with 100K pull-up to +VCC3. | | 3 | CH3-IN | SD3_D3 | ✅ | Channel 3 input connected to SD3_D3 (data line 3) with 100K pull-up to +VCC3. | | 4 | CH4-IN | SD3_CMD | ✅ | Channel 4 input connected to SD3_CMD (command line) with 100K pull-up to +VCC3. | | 5 | CH5-IN | SD3_CLK | ✅ | Channel 5 input connected to SD3_CLK (clock line) with 100K pull-up to +VCC3. | | 6 | CH6-IN | SD3_D0 | ✅ | Channel 6 input connected to SD3_D0 (data line 0) with 100K pull-up to +VCC3. | | 7 | CH7-IN | SD3_D1 | ✅ | Channel 7 input connected to SD3_D1 (data line 1) with 100K pull-up to +VCC3. | | 8 | CH8-IN | | ✅ | Channel 8 input is unconnected (unused channel). | | 9 | CH8-OUT | | ✅ | Channel 8 output is unconnected (unused channel). | | 10 | CH7-OUT | SD3_D1_R | ✅ | Channel 7 output connected to SD3_D1_R, routing filtered data line 1 to connector P2 pin 8. | | 11 | CH6-OUT | SD3_D0_R | ✅ | Channel 6 output connected to SD3_D0_R, routing filtered data line 0 to connector P2 pin 7. | | 12 | CH5-OUT | SD3_CLK_R | ✅ | Channel 5 output connected to SD3_CLK_R, routing filtered clock to connector P2 pin 5. | | 13 | CH4-OUT | SD3_CMD_R | ✅ | Channel 4 output connected to SD3_CMD_R, routing filtered command line to connector P2 pin 3. | | 14 | CH3-OUT | SD3_D3_R | ✅ | Channel 3 output connected to SD3_D3_R, routing filtered data line 3 to connector P2 pin 2. | | 15 | CH2-OUT | SD3_D2_R | ✅ | Channel 2 output connected to SD3_D2_R, routing filtered data line 2 to connector P2 pin 1. | | 16 | CH1-OUT | SD3_CD_R | ✅ | Channel 1 output connected to SD3_CD_R, routing filtered card detect to connector P2 pin 10. | | 17 | GND_PAD | GND | ✅ | Ground pad correctly connected to GND. | </details> <details> <summary>P2 - 158-0001269 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/SCHA5B0200) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DAT2 | SD3_D2_R | ✅ | DAT2 pin connected to SD3_D2_R, receiving filtered data line 2 from FL1 channel 2. | | 2 | CD/DAT3 | SD3_D3_R | ✅ | CD/DAT3 pin connected to SD3_D3_R, receiving filtered data line 3 from FL1 channel 3. | | 3 | CMD | SD3_CMD_R | ✅ | CMD pin connected to SD3_CMD_R, receiving filtered command line from FL1 channel 4. | | 4 | VDD | +VCC3 | ✅ | VDD pin connected to +VCC3 with proper decoupling capacitors C162 and C159. | | 5 | CLOCK | SD3_CLK_R | ✅ | CLOCK pin connected to SD3_CLK_R, receiving filtered clock from FL1 channel 5. | | 6 | VSS | GND | ✅ | VSS pin correctly connected to GND. | | 7 | DAT0 | SD3_D0_R | ✅ | DAT0 pin connected to SD3_D0_R, receiving filtered data line 0 from FL1 channel 6. | | 8 | DAT1 | SD3_D1_R | ✅ | DAT1 pin connected to SD3_D1_R, receiving filtered data line 1 from FL1 channel 7. | | 9 | GND | GND | ✅ | GND pin correctly connected to GND. | | 10 | CD | SD3_CD_R | ✅ | CD pin connected to SD3_CD_R, receiving filtered card detect from FL1 channel 1. Note: card detect has pull-up to +V1P8S while other signals use +VCC3. | | 11 | GND3 | FGND-uSD | ✅ | Frame ground pins GND3, GND4, GND7, GND8 connected to FGND-uSD. Intentionally separated from main GND per schematic note. | | 12 | GND4 | FGND-uSD | ✅ | Frame ground pins GND3, GND4, GND7, GND8 connected to FGND-uSD. Intentionally separated from main GND per schematic note. | | 15 | GND7 | FGND-uSD | ✅ | Frame ground pins GND3, GND4, GND7, GND8 connected to FGND-uSD. Intentionally separated from main GND per schematic note. | | 16 | GND8 | FGND-uSD | ✅ | Frame ground pins GND3, GND4, GND7, GND8 connected to FGND-uSD. Intentionally separated from main GND per schematic note. | | 13 | GND5 | FGND-uSD-Front | ✅ | Frame ground pins GND5 and GND6 connected to FGND-uSD-Front. Intentionally separated from main GND and uses different frame ground net than other shield pins. | | 14 | GND6 | FGND-uSD-Front | ✅ | Frame ground pins GND5 and GND6 connected to FGND-uSD-Front. Intentionally separated from main GND and uses different frame ground net than other shield pins. | </details> <details> <summary>U2 - TPD12S016PW ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd12s016) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004333) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 15 | CLK- | HDMI_OUT_CLK_DN | ❌ | <details><summary>All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,58.30,53.07,65.80" aspect-ratio="1.29" } <ul><li>Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic)</li><li>Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic)</li><li>Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic)</li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic)</li><li>Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic)</li><li>Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic)</li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic)</li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic)</li><li>According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</li><li>The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic)</li><li>The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning)</li><li>Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning)</li><li>All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning)</li><li>Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning)</li><li>The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)</li></ul></details> | | 16 | CLK+ | HDMI_OUT_CLK_DP | ❌ | <details><summary>All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,58.89,53.07,66.39" aspect-ratio="1.29" } <ul><li>Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic)</li><li>Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic)</li><li>Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic)</li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic)</li><li>Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic)</li><li>Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic)</li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic)</li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic)</li><li>According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</li><li>The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic)</li><li>The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning)</li><li>Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning)</li><li>All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning)</li><li>Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning)</li><li>The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)</li></ul></details> | | 17 | D0- | HDMI_OUT_TX0_DN | ❌ | <details><summary>All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,59.48,53.07,66.98" aspect-ratio="1.29" } <ul><li>Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic)</li><li>Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic)</li><li>Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic)</li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic)</li><li>Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic)</li><li>Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic)</li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic)</li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic)</li><li>According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</li><li>The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic)</li><li>The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning)</li><li>Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning)</li><li>All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning)</li><li>Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning)</li><li>The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)</li></ul></details> | | 18 | D0+ | HDMI_OUT_TX0_DP | ❌ | <details><summary>All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,60.07,53.07,67.57" aspect-ratio="1.29" } <ul><li>Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic)</li><li>Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic)</li><li>Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic)</li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic)</li><li>Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic)</li><li>Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic)</li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic)</li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic)</li><li>According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</li><li>The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic)</li><li>The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning)</li><li>Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning)</li><li>All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning)</li><li>Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning)</li><li>The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)</li></ul></details> | | 20 | D1- | HDMI_OUT_TX1_DN | ❌ | <details><summary>All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,60.66,53.07,68.16" aspect-ratio="1.29" } <ul><li>Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic)</li><li>Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic)</li><li>Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic)</li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic)</li><li>Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic)</li><li>Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic)</li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic)</li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic)</li><li>According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</li><li>The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic)</li><li>The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning)</li><li>Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning)</li><li>All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning)</li><li>Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning)</li><li>The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)</li></ul></details> | | 21 | D1+ | HDMI_OUT_TX1_DP | ❌ | <details><summary>All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,61.24,53.07,68.74" aspect-ratio="1.29" } <ul><li>Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic)</li><li>Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic)</li><li>Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic)</li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic)</li><li>Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic)</li><li>Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic)</li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic)</li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic)</li><li>According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</li><li>The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic)</li><li>The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning)</li><li>Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning)</li><li>All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning)</li><li>Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning)</li><li>The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)</li></ul></details> | | 22 | D2- | HDMI_OUT_TX2_DN | ❌ | <details><summary>All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,61.83,53.07,69.33" aspect-ratio="1.29" } <ul><li>Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic)</li><li>Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic)</li><li>Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic)</li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic)</li><li>Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic)</li><li>Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic)</li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic)</li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic)</li><li>According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</li><li>The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic)</li><li>The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning)</li><li>Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning)</li><li>All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning)</li><li>Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning)</li><li>The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)</li></ul></details> | | 23 | D2+ | HDMI_OUT_TX2_DP | ❌ | <details><summary>All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,62.42,53.07,69.92" aspect-ratio="1.29" } <ul><li>Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic)</li><li>Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic)</li><li>Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic)</li><li>Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic)</li><li>Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic)</li><li>Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic)</li><li>Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic)</li><li>Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic)</li><li>According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet <a href="https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4">140-0004333</a>, page 4)</li><li>The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic)</li><li>The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning)</li><li>Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning)</li><li>All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning)</li><li>Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning)</li><li>The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)</li></ul></details> | | 1 | CEC_A | HDMI_CEC | ✅ | CEC_A pin connects to HDMI_CEC net with 10kΩ pullup to +V1P8S. This is the HDMI controller side CEC signal. | | 2 | SCL_A | HDMI_DDCCLK | ✅ | SCL_A pin connects to HDMI_DDCCLK net with 10kΩ pullup to +V1P8S. This is the HDMI controller side I2C clock signal. | | 3 | SDA_A | HDMI_DDCDAT | ✅ | SDA_A pin connects to HDMI_DDCDAT net with 10kΩ pullup to +V1P8S. This is the HDMI controller side I2C data signal. | | 4 | HPD_A | HDMI_HPD | ✅ | HPD_A pin connects to HDMI_HPD net. This is the hot plug detect output to the HDMI controller. | | 5 | LS_OE | LS_OE | ✅ | LS_OE pin connects to LS_OE net with 2.2kΩ pullup to +V1P8S. This enables the level shifters by default. | | 6 | GND1 | GND | ✅ | Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net. | | 14 | GND2 | GND | ✅ | Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net. | | 19 | GND3 | GND | ✅ | Ground pins GND1, GND2, and GND3 are all correctly connected to the GND net. | | 7 | CEC_B | C_HDMI_CEC | ✅ | CEC_B pin connects to C_HDMI_CEC net which goes to the HDMI connector CEC pin. This is the HDMI connector side CEC signal. | | 8 | SCL_B | C_HDMI_SCL | ✅ | SCL_B pin connects to C_HDMI_SCL net which goes to the HDMI connector SCL pin. This is the HDMI connector side I2C clock signal. | | 9 | SDA_B | C_HDMI_SDA | ✅ | SDA_B pin connects to C_HDMI_SDA net which goes to the HDMI connector SDA pin. This is the HDMI connector side I2C data signal. | | 10 | HPD_B | C_HDMI_HPD | ✅ | HPD_B pin connects to C_HDMI_HPD net which goes to the HDMI connector hot plug detect pin. This is the hot plug detect input from the HDMI cable. | | 11 | VCC5V | +5VSB | ✅ | VCC5V pin connects to +5VSB supply with 0.1µF decoupling capacitor. This is the 5V power input for the load switch. | | 12 | CT_HPD | HPD_ENB | ✅ | CT_HPD pin connects to HPD_ENB net with 2.2kΩ pullup to +V1P8S. This enables the load switch and HPD by default. | | 13 | 5V_OUT | +HDMI_CRT_VCC | ✅ | 5V_OUT pin connects to +HDMI_CRT_VCC net with 4.7µF capacitor and ferrite bead to HDMI connector 5V pin. This is the current-limited 5V output to the HDMI cable. | | 24 | VCCA | +V1P8S | ✅ | VCCA pin connects to +V1P8S supply with 0.1µF decoupling capacitor. This is the low voltage power supply for the device. | </details> <details> <summary>P1 - microHDMI_TH ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/158-0004513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | HPLG | C_HDMI_HPD | ✅ | Hot Plug Detect signal correctly connected through level translator U2 to system HPD signal. | | 2 | NC | | ✅ | Pin 2 is not connected, which is correct as this pin is typically reserved or used for HEAC+ in HDMI Type D. | | 3 | DAT2+ | HDMI_OUT_TX2_DP | ✅ | TMDS Data2+ correctly connected through common mode choke L17 and level translator U2 from source signal HDMI_TX2_DP. | | 4 | DAT2_S | GND | ✅ | TMDS Data2 shield correctly connected to ground for proper shielding of the differential pair. | | 5 | DAT2- | HDMI_OUT_TX2_DN | ✅ | TMDS Data2- correctly connected through common mode choke L17 and level translator U2 from source signal HDMI_TX2_DN. | | 6 | DAT1+ | HDMI_OUT_TX1_DP | ✅ | TMDS Data1+ correctly connected through common mode choke L16 and level translator U2 from source signal HDMI_TX1_DP. | | 7 | DAT1_S | GND | ✅ | TMDS Data1 shield correctly connected to ground. | | 8 | DAT1- | HDMI_OUT_TX1_DN | ✅ | TMDS Data1- correctly connected through common mode choke L16 and level translator U2 from source signal HDMI_TX1_DN. | | 9 | DAT0+ | HDMI_OUT_TX0_DP | ✅ | TMDS Data0+ correctly connected through common mode choke L15 and level translator U2 from source signal HDMI_TX0_DP. | | 10 | DAT0_S | GND | ✅ | TMDS Data0 shield correctly connected to ground. | | 11 | DAT0- | HDMI_OUT_TX0_DN | ✅ | TMDS Data0- correctly connected through common mode choke L15 and level translator U2 from source signal HDMI_TX0_DN. | | 12 | CLK+ | HDMI_OUT_CLK_DP | ✅ | TMDS Clock+ correctly connected through common mode choke L14 and level translator U2 from source signal HDMI_CLK_DP. | | 13 | CLK_S | GND | ✅ | TMDS Clock shield correctly connected to ground. | | 14 | CLK- | HDMI_OUT_CLK_DN | ✅ | TMDS Clock- correctly connected through common mode choke L14 and level translator U2 from source signal HDMI_CLK_DN. | | 15 | CEC | C_HDMI_CEC | ✅ | CEC signal correctly connected through level translator U2 with proper pullup resistor on source side. | | 16 | DDC/CEC_GND | GND | ✅ | DDC/CEC ground correctly connected to system ground. | | 17 | SCL | C_HDMI_SCL | ✅ | DDC SCL signal correctly connected through level translator U2 with proper pullup resistor on source side. | | 18 | SDA | C_HDMI_SDA | ✅ | DDC SDA signal correctly connected through level translator U2 with proper pullup resistor on source side. | | 19 | +5V | D5_0V_HDMI | ✅ | 5V power correctly supplied through ferrite bead from charge pump output with proper decoupling. | | 20 | MTG1 | GND_EARTH | ✅ | Mounting pins correctly connected to chassis ground (GND_EARTH) with high-voltage capacitive coupling to system ground for EMI filtering. | | 21 | MTG2 | GND_EARTH | ✅ | Mounting pins correctly connected to chassis ground (GND_EARTH) with high-voltage capacitive coupling to system ground for EMI filtering. | | 22 | MTG3 | GND_EARTH | ✅ | Mounting pins correctly connected to chassis ground (GND_EARTH) with high-voltage capacitive coupling to system ground for EMI filtering. | | 23 | MTG4 | GND_EARTH | ✅ | Mounting pins correctly connected to chassis ground (GND_EARTH) with high-voltage capacitive coupling to system ground for EMI filtering. | </details> <details> <summary>L16 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX1_C_DN | ✅ | IN1 pin receives the negative data signal HDMI_TX1_C_DN after AC coupling through C405 and connects internally to OUT1 (pin 6) to pass the signal to the HDMI translator U2. | | 3 | IN2 | HDMI_TX1_C_DP | ✅ | IN2 pin receives the positive data signal HDMI_TX1_C_DP after AC coupling through C404 and connects internally to OUT2 (pin 4) to pass the signal to the HDMI translator U2. | | 4 | OUT2 | HDMI_OUT_TX1_DP | ✅ | OUT2 pin outputs the filtered positive data signal HDMI_OUT_TX1_DP to U2 pin 21 (D1+) and connector P1 pin 6. | | 6 | OUT1 | HDMI_OUT_TX1_DN | ✅ | OUT1 pin outputs the filtered negative data signal HDMI_OUT_TX1_DN to U2 pin 20 (D1-) and connector P1 pin 8. | </details> <details> <summary>L15 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX0_C_DN | ✅ | IN1 pin receives the negative data signal HDMI_TX0_C_DN after AC coupling through C403 and connects internally to OUT1 (pin 6) to pass the signal to the HDMI translator U2. | | 3 | IN2 | HDMI_TX0_C_DP | ✅ | IN2 pin receives the positive data signal HDMI_TX0_C_DP after AC coupling through C402 and connects internally to OUT2 (pin 4) to pass the signal to the HDMI translator U2. | | 4 | OUT2 | HDMI_OUT_TX0_DP | ✅ | OUT2 pin outputs the filtered positive data signal HDMI_OUT_TX0_DP to U2 pin 18 (D0+) and connector P1 pin 9. | | 6 | OUT1 | HDMI_OUT_TX0_DN | ✅ | OUT1 pin outputs the filtered negative data signal HDMI_OUT_TX0_DN to U2 pin 17 (D0-) and connector P1 pin 11. | </details> <details> <summary>L14 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_CLK_C_DN | ✅ | IN1 pin receives the negative clock signal HDMI_CLK_C_DN after AC coupling through C401 and connects internally to OUT1 (pin 6) to pass the signal to the HDMI translator U2. | | 3 | IN2 | HDMI_CLK_C_DP | ✅ | IN2 pin receives the positive clock signal HDMI_CLK_C_DP after AC coupling through C400 and connects internally to OUT2 (pin 4) to pass the signal to the HDMI translator U2. | | 4 | OUT2 | HDMI_OUT_CLK_DP | ✅ | OUT2 pin outputs the filtered positive clock signal HDMI_OUT_CLK_DP to U2 pin 16 (CLK+) and connector P1 pin 12. | | 6 | OUT1 | HDMI_OUT_CLK_DN | ✅ | OUT1 pin outputs the filtered negative clock signal HDMI_OUT_CLK_DN to U2 pin 15 (CLK-) and connector P1 pin 14. | </details> <details> <summary>L17 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | HDMI_TX2_C_DN | ✅ | IN1 pin receives the negative data signal HDMI_TX2_C_DN after AC coupling through C407 and connects internally to OUT1 (pin 6) to pass the signal to the HDMI translator U2. | | 3 | IN2 | HDMI_TX2_C_DP | ✅ | IN2 pin receives the positive data signal HDMI_TX2_C_DP after AC coupling through C406 and connects internally to OUT2 (pin 4) to pass the signal to the HDMI translator U2. | | 4 | OUT2 | HDMI_OUT_TX2_DP | ✅ | OUT2 pin outputs the filtered positive data signal HDMI_OUT_TX2_DP to U2 pin 23 (D2+) and connector P1 pin 3. | | 6 | OUT1 | HDMI_OUT_TX2_DN | ✅ | OUT1 pin outputs the filtered negative data signal HDMI_OUT_TX2_DN to U2 pin 22 (D2-) and connector P1 pin 5. | </details> <details> <summary>R809 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $15N747 | ✅ | Connected to gate of Q101 (N-Channel MOSFET) through net $15N747. | | 2 | 2 | +VCC3 | ✅ | Connected to +VCC3 power rail, providing gate drive voltage to Q101 to enable HDMI termination network. | </details> <details> <summary>Q101 - 2N7002K ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/132-0004419) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | HDMI_TERM | ✅ | Drain pin correctly connected to HDMI_TERM net, which is the common connection point for eight 619Ω termination resistors (R801-R808) serving the HDMI differential pairs. | | G | GATE | $15N747 | ✅ | Gate pin is connected through R809 (0Ω) to +VCC3, keeping Q101 permanently on and the HDMI termination always enabled. | | S | SOURCE | GND | ✅ | Source pin correctly connected to GND, providing the return path for the low-side switch configuration. | </details> <details> <summary>R29 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_CEC | ✅ | 10K pull-up resistor on HDMI CEC line (HDMI_CEC) to +V1P8S. This provides the required pull-up for the open-drain CEC signal on the application side of the TPD12S016PW. | | 2 | 2 | +V1P8S | ✅ | 10K pull-up resistor on HDMI CEC line (HDMI_CEC) to +V1P8S. This provides the required pull-up for the open-drain CEC signal on the application side of the TPD12S016PW. | </details> <details> <summary>R28 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_DDCCLK | ✅ | 10K pull-up resistor on HDMI DDC I2C clock line (HDMI_DDCCLK) to +V1P8S. This provides the required pull-up for the open-drain I2C clock signal on the application side of the TPD12S016PW level shifter. | | 2 | 2 | +V1P8S | ✅ | 10K pull-up resistor on HDMI DDC I2C clock line (HDMI_DDCCLK) to +V1P8S. This provides the required pull-up for the open-drain I2C clock signal on the application side of the TPD12S016PW level shifter. | </details> <details> <summary>R30 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HDMI_DDCDAT | ✅ | 10K pull-up resistor on HDMI DDC I2C data line (HDMI_DDCDAT) to +V1P8S. This provides the required pull-up for the open-drain I2C data signal on the application side of the TPD12S016PW level shifter. | | 2 | 2 | +V1P8S | ✅ | 10K pull-up resistor on HDMI DDC I2C data line (HDMI_DDCDAT) to +V1P8S. This provides the required pull-up for the open-drain I2C data signal on the application side of the TPD12S016PW level shifter. | </details> <details> <summary>R172 - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | 2.2K pull-up resistor on LS_OE control signal to +V1P8S. This pulls up the Level Shifter Output Enable pin of the TPD12S016PW, enabling the level shifters by default. | | 2 | 2 | LS_OE | ✅ | 2.2K pull-up resistor on LS_OE control signal to +V1P8S. This pulls up the Level Shifter Output Enable pin of the TPD12S016PW, enabling the level shifters by default. | </details> <details> <summary>R171 - 110-0001984 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001984) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | 2.2K pull-up resistor on HPD_ENB control signal to +V1P8S. This pulls up the CT_HPD control pin of the TPD12S016PW to set its default state. | | 2 | 2 | HPD_ENB | ✅ | 2.2K pull-up resistor on HPD_ENB control signal to +V1P8S. This pulls up the CT_HPD control pin of the TPD12S016PW to set its default state. | </details> <details> <summary>C157 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +HDMI_CRT_VCC | ✅ | Connected to +HDMI_CRT_VCC, the charge pump output from U2 pin 13. | | 2 | 2 | GND | ✅ | Connected to GND for decoupling the charge pump output. | </details> <details> <summary>C155 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND for decoupling the +5VSB supply. | | 2 | 2 | +5VSB | ✅ | Connected to +5VSB supply rail which powers U2 VCC5V pin. | </details> <details> <summary>L7 - FB_220R_2.2A ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://pim.murata.com/asset/pim4/ferriteBeadInductortypefilter/ENFA0003_PDF_FERRITEBEADINDUCTORTYPEFILTER?lastModifiedDatetime=20250707190934) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0001418) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P1 | +HDMI_CRT_VCC | ✅ | Input side of ferrite bead connected to +HDMI_CRT_VCC from U2 charge pump output. This filters noise from the 5V charge pump before supplying the HDMI connector. | | 2 | P2 | D5_0V_HDMI | ✅ | Output side of ferrite bead connected to D5_0V_HDMI which supplies the HDMI connector 5V pin. This provides filtered 5V power to the HDMI connector. | </details> <details> <summary>C17 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND for decoupling the +V1P8S supply. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S supply rail which powers U2 VCCA pin and pull-up resistors. | </details> <details> <summary>U32 - AP2172MPG ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/AP2162_72.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/AP2172MPG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 5 | OC2# | SOC_USB_HOST_OC1 | ❌ | <details><summary>Open-drain overcurrent flag outputs (FLG2/OC2# on pin 5, FLG1/OC1# on pin 8) connected directly to SoC without external pull-up resistors, deviating from datasheet recommendations.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="35.34,50.66,42.84,58.16" aspect-ratio="1.29" } <ul><li>Pin 5 (OC2#) is connected to SOC_USB_HOST_OC1 net and pin 8 (OC1#) is connected to SOC_USB_HOST_OC0 net (from schematic)</li><li>No external pull-up resistors are present on SOC_USB_HOST_OC0 or SOC_USB_HOST_OC1 nets on this schematic page (from schematic)</li><li>R115 (2.2K) connected to SOC_USB_HOST_EN0 is marked DNI and would be a pull-down, not a pull-up (from schematic)</li><li>The signals connect directly to the SoC which operates at 1.8V logic levels per the level translator U4 configuration (from schematic)</li><li>Pin 5 is FLG2 (Switch 2 over-current and over-temperature fault report) and pin 8 is FLG1 (Switch 1 over-current and over-temperature fault report) per the datasheet (from datasheet <a href="https://www.diodes.com/assets/Datasheets/AP2162_72.pdf#page=2">AP2172MPG</a>, page 2)</li><li>FLG outputs are open-drain and active low when triggered (from datasheet <a href="https://www.diodes.com/assets/Datasheets/AP2162_72.pdf#page=2">AP2172MPG</a>, page 2)</li><li>The datasheet typical application circuit shows 10k pull-up resistors from FLG outputs to IN (from datasheet <a href="https://www.diodes.com/assets/Datasheets/AP2162_72.pdf#page=1">AP2172MPG</a>, page 1)</li><li>Open-drain outputs require pull-up resistors to provide a valid logic high level when not actively pulling low (reasoning)</li><li>Without external pull-ups, the signals would float when there is no fault condition, which is not a valid logic level (reasoning)</li><li>The design may rely on internal pull-ups in the SoC, which is common for GPIO pins and would allow the open-drain outputs to function correctly across the voltage domain (5V USB to 1.8V SoC) (reasoning)</li><li>However, relying on internal pull-ups creates a dependency on SoC configuration and is not guaranteed to work if the internal pull-ups are not enabled or are insufficient (reasoning)</li><li>Best practice per the datasheet is to include external pull-up resistors (typically 10k to an appropriate voltage rail) to ensure proper operation regardless of SoC configuration (reasoning)</li><li>External 10k pull-up resistors should be added to SOC_USB_HOST_OC0 and SOC_USB_HOST_OC1 nets to match datasheet recommendations and ensure reliable operation (reasoning)</li></ul></details> | | 8 | OC1# | SOC_USB_HOST_OC0 | ❌ | <details><summary>Open-drain overcurrent flag outputs (FLG2/OC2# on pin 5, FLG1/OC1# on pin 8) connected directly to SoC without external pull-up resistors, deviating from datasheet recommendations.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="35.34,47.72,42.84,55.22" aspect-ratio="1.29" } <ul><li>Pin 5 (OC2#) is connected to SOC_USB_HOST_OC1 net and pin 8 (OC1#) is connected to SOC_USB_HOST_OC0 net (from schematic)</li><li>No external pull-up resistors are present on SOC_USB_HOST_OC0 or SOC_USB_HOST_OC1 nets on this schematic page (from schematic)</li><li>R115 (2.2K) connected to SOC_USB_HOST_EN0 is marked DNI and would be a pull-down, not a pull-up (from schematic)</li><li>The signals connect directly to the SoC which operates at 1.8V logic levels per the level translator U4 configuration (from schematic)</li><li>Pin 5 is FLG2 (Switch 2 over-current and over-temperature fault report) and pin 8 is FLG1 (Switch 1 over-current and over-temperature fault report) per the datasheet (from datasheet <a href="https://www.diodes.com/assets/Datasheets/AP2162_72.pdf#page=2">AP2172MPG</a>, page 2)</li><li>FLG outputs are open-drain and active low when triggered (from datasheet <a href="https://www.diodes.com/assets/Datasheets/AP2162_72.pdf#page=2">AP2172MPG</a>, page 2)</li><li>The datasheet typical application circuit shows 10k pull-up resistors from FLG outputs to IN (from datasheet <a href="https://www.diodes.com/assets/Datasheets/AP2162_72.pdf#page=1">AP2172MPG</a>, page 1)</li><li>Open-drain outputs require pull-up resistors to provide a valid logic high level when not actively pulling low (reasoning)</li><li>Without external pull-ups, the signals would float when there is no fault condition, which is not a valid logic level (reasoning)</li><li>The design may rely on internal pull-ups in the SoC, which is common for GPIO pins and would allow the open-drain outputs to function correctly across the voltage domain (5V USB to 1.8V SoC) (reasoning)</li><li>However, relying on internal pull-ups creates a dependency on SoC configuration and is not guaranteed to work if the internal pull-ups are not enabled or are insufficient (reasoning)</li><li>Best practice per the datasheet is to include external pull-up resistors (typically 10k to an appropriate voltage rail) to ensure proper operation regardless of SoC configuration (reasoning)</li><li>External 10k pull-up resistors should be added to SOC_USB_HOST_OC0 and SOC_USB_HOST_OC1 nets to match datasheet recommendations and ensure reliable operation (reasoning)</li></ul></details> | | 1 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 2 | IN | +USBVCC | ✅ | Input power pin connected to +USBVCC with appropriate bypass capacitors. | | 3 | EN1 | USB_HOST_EN0 | ✅ | Enable input for channel 1 connected through level translator U4 to SOC control signal. | | 4 | EN2 | USB_HOST_EN1 | ✅ | Enable input for channel 2 connected through level translator U4 to SOC control signal with pull-down on SOC side. | | 6 | OUTB | USBP2 | ✅ | Output channel 2 connected through ferrite bead L2 to VBUS2 with appropriate output capacitors. | | 7 | OUTA | USBP1 | ✅ | Output channel 1 connected through ferrite bead L1 to VBUS1 with appropriate output capacitors. | | 9 | GND_PAD | GND | ✅ | Exposed pad correctly connected to GND for thermal management. | </details> <details> <summary>FB13 - 3044-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3044-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Input side connected to +5VSB supply rail for filtering. | | 2 | 2 | +USBVCC | ✅ | Output side connected to +USBVCC, providing filtered power to USB power switch U32 and level translator U4. | </details> <details> <summary>L1 - BKP2125HS221-T ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BKP2125HS221-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USBP1 | ✅ | Input side connected to USBP1 from power switch U32 output channel 1. | | 2 | 2 | VBUS1 | ✅ | Output side connected to VBUS1, providing filtered power to USB port 1 with appropriate output capacitors. | </details> <details> <summary>L2 - BKP2125HS221-T ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BKP2125HS221-T) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USBP2 | ✅ | Input side connected to USBP2 from power switch U32 output channel 2. | | 2 | 2 | VBUS2 | ✅ | Output side connected to VBUS2, providing filtered power to USB port 2 with appropriate output capacitors. | </details> <details> <summary>C91 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 22uF bulk capacitor on VBUS1 output, smaller than datasheet recommended 68uF for heavy loads but acceptable for typical USB applications. | | 2 | 2 | VBUS1 | ✅ | 22uF bulk capacitor on VBUS1 output, smaller than datasheet recommended 68uF for heavy loads but acceptable for typical USB applications. | </details> <details> <summary>C103 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | 22uF bulk capacitor on VBUS2 output, smaller than datasheet recommended 68uF for heavy loads but acceptable for typical USB applications. | | 2 | 2 | VBUS2 | ✅ | 22uF bulk capacitor on VBUS2 output, smaller than datasheet recommended 68uF for heavy loads but acceptable for typical USB applications. | </details> <details> <summary>R116 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB_HOST_BUFF_ENB | ✅ | 10K pull-up resistor connecting USB_HOST_BUFF_ENB to +V1P8A, providing a default high state for the level translator OE pin. | | 2 | 2 | +V1P8A | ✅ | 10K pull-up resistor connecting USB_HOST_BUFF_ENB to +V1P8A, providing a default high state for the level translator OE pin. | </details> <details> <summary>U4 - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | USB_HOST_EN0 | ✅ | B2 pin connected to USB_HOST_EN0 net, which drives the EN1 pin of USB power switch U32. This is the high-voltage side output of the level translator. | | 2 | GND | GND | ✅ | GND pin correctly connected to the ground net. | | 3 | VCCA | +V1P8A | ✅ | VCCA pin connected to +V1P8A supply, providing the low-voltage side power for the level translator. | | 4 | A2 | SOC_USB_HOST_EN0 | ✅ | A2 pin connected to SOC_USB_HOST_EN0, serving as a low-voltage input from the SOC. | | 5 | A1 | SOC_USB_HOST_EN1 | ✅ | A1 pin connected to SOC_USB_HOST_EN1, serving as a low-voltage input from the SOC with a pull-down resistor. | | 6 | OE | USB_HOST_BUFF_ENB | ✅ | OE pin connected to USB_HOST_BUFF_ENB through pull-up resistor R116, controlling the enable state of the level translator. | | 7 | VCCB | +USBVCC | ✅ | VCCB pin connected to +USBVCC supply, providing the high-voltage side power for the level translator. | | 8 | B1 | USB_HOST_EN1 | ✅ | B1 pin connected to USB_HOST_EN1 net, which drives the EN2 pin of USB power switch U32. This is the high-voltage side output of the level translator. | </details> <details> <summary>U8 - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H1 | ✅ | D+ pin provides ESD protection for USB port B data line. Connected to USB_H1 net which routes through common mode choke CHOKE3 to USB connector pin DB+. | | 2 | D- | USB_L1 | ✅ | D- pin provides ESD protection for USB port B data line. Connected to USB_L1 net which routes through common mode choke CHOKE3 to USB connector pin DB-. | | 3 | ID | | ✅ | ID pin is left floating (no connection). This is acceptable per datasheet as ID pin can be left floating if not used. | | 4 | GND | GND | ✅ | GND pin is correctly connected to the GND net providing ground reference for the ESD protection device. | | 5 | NC | | ✅ | NC pin has no connection, which is correct as this pin is not internally connected per the datasheet. | | 6 | VBUS | VBUS2 | ✅ | VBUS pin provides ESD protection for USB port B power line. Connected to VBUS2 net with proper decoupling capacitors and routes through ferrite bead L2 to USB connector. | </details> <details> <summary>U9 - TPD4S012 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Ftpd4s012) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/TPD4S012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D+ | USB_H0 | ✅ | D+ pin provides ESD protection for USB port A data line. Connected to USB_H0 net which routes through common mode choke CHOKE4 to USB connector pin DA+. | | 2 | D- | USB_L0 | ✅ | D- pin provides ESD protection for USB port A data line. Connected to USB_L0 net which routes through common mode choke CHOKE4 to USB connector pin DA-. | | 3 | ID | | ✅ | ID pin is left floating (no connection). This is acceptable per datasheet as ID pin can be left floating if not used. | | 4 | GND | GND | ✅ | GND pin is correctly connected to the GND net providing ground reference for the ESD protection device. | | 5 | NC | | ✅ | NC pin has no connection, which is correct as this pin is not internally connected per the datasheet. | | 6 | VBUS | VBUS1 | ✅ | VBUS pin provides ESD protection for USB port A power line. Connected to VBUS1 net with proper decoupling capacitors and routes through ferrite bead L1 to USB connector. | </details> <details> <summary>U29 - TPD4USB30 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/TPD4USB30) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | D1+ | USB3_TX0P_C | ✅ | D1+ pin is connected to USB3_TX0P_C, protecting the USB3 SuperSpeed TX positive differential signal going to the connector. | | 2 | D1- | USB3_TX0N_C | ✅ | D1- pin is connected to USB3_TX0N_C, protecting the USB3 SuperSpeed TX negative differential signal going to the connector. | | 3 | GND1 | GND | ✅ | GND1 pin is correctly connected to the GND net for ESD protection reference. | | 4 | D2+ | USB3_RX0P_C | ✅ | D2+ pin is connected to USB3_RX0P_C, protecting the USB3 SuperSpeed RX positive differential signal from the connector. | | 5 | D2- | USB3_RX0N_C | ✅ | D2- pin is connected to USB3_RX0N_C, protecting the USB3 SuperSpeed RX negative differential signal from the connector. | | 6 | NC4 | USB3_RX0N_C | ✅ | NC4 pin is labeled as No Connect but is connected to USB3_RX0N_C. Without the datasheet, it cannot be confirmed whether this connection is correct, though it may be intentional for improved ESD protection. | | 7 | NC3 | USB3_RX0P_C | ✅ | NC3 pin is labeled as No Connect but is connected to USB3_RX0P_C. Without the datasheet, it cannot be confirmed whether this connection is correct, though it may be intentional for improved ESD protection. | | 8 | GND2 | GND | ✅ | GND2 pin is correctly connected to the GND net for ESD protection reference. | | 9 | NC2 | USB3_TX0N_C | ✅ | NC2 pin is labeled as No Connect but is connected to USB3_TX0N_C. Without the datasheet, it cannot be confirmed whether this connection is correct, though it may be intentional for improved ESD protection. | | 10 | NC1 | USB3_TX0P_C | ✅ | NC1 pin is labeled as No Connect but is connected to USB3_TX0P_C. Without the datasheet, it cannot be confirmed whether this connection is correct, though it may be intentional for improved ESD protection. | </details> <details> <summary>C191 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_TXN0 | ✅ | Connected to USB3_TXN0 from the SOC, providing AC coupling for the USB3 TX negative signal. | | 2 | 2 | USB3_TX0N-R | ✅ | Connected to USB3_TX0N-R going to CHOKE2, completing the AC coupling path for the USB3 TX negative signal. | </details> <details> <summary>C192 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001056) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | USB3_TXP0 | ✅ | Connected to USB3_TXP0 from the SOC, providing AC coupling for the USB3 TX positive signal. | | 2 | 2 | USB3_TX0P-R | ✅ | Connected to USB3_TX0P-R going to CHOKE2, completing the AC coupling path for the USB3 TX positive signal. | </details> <details> <summary>CHOKE1 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_RX0N_C | ✅ | IN1 pin receives the USB3 RX negative signal (USB3_RX0N_C) from the USB connector and ESD protection, forming one side of the common mode choke for filtering. | | 3 | IN2 | USB3_RX0P_C | ✅ | IN2 pin receives the USB3 RX positive signal (USB3_RX0P_C) from the USB connector and ESD protection, forming the other side of the common mode choke for filtering. | | 4 | OUT2 | USB3_RXP0 | ✅ | OUT2 pin outputs the filtered USB3 RX positive signal (USB3_RXP0) to the SOC. | | 6 | OUT1 | USB3_RXN0 | ✅ | OUT1 pin outputs the filtered USB3 RX negative signal (USB3_RXN0) to the SOC. | </details> <details> <summary>CHOKE2 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB3_TX0P-R | ✅ | IN1 pin receives the AC-coupled USB3 TX positive signal (USB3_TX0P-R) from the SOC through capacitor C192, forming one side of the common mode choke for filtering. | | 3 | IN2 | USB3_TX0N-R | ✅ | IN2 pin receives the AC-coupled USB3 TX negative signal (USB3_TX0N-R) from the SOC through capacitor C191, forming the other side of the common mode choke for filtering. | | 4 | OUT2 | USB3_TX0N_C | ✅ | OUT2 pin outputs the filtered USB3 TX negative signal (USB3_TX0N_C) to the ESD protection and USB connector SSTX- pin. | | 6 | OUT1 | USB3_TX0P_C | ✅ | OUT1 pin outputs the filtered USB3 TX positive signal (USB3_TX0P_C) to the ESD protection and USB connector SSTX+ pin. | </details> <details> <summary>CHOKE4 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN0 | ✅ | IN1 pin connected to USB_DN0, which is the D- signal from the USB controller for port 0. This pin is the input side of the common mode choke for the negative differential signal. | | 3 | IN2 | USB_DP0 | ✅ | IN2 pin connected to USB_DP0, which is the D+ signal from the USB controller for port 0. This pin is the input side of the common mode choke for the positive differential signal. | | 4 | OUT2 | USB_H0 | ✅ | OUT2 pin connected to USB_H0, which routes to the D+ line of USB port A through ESD protection. This pin is the output side of the common mode choke for the positive differential signal. | | 6 | OUT1 | USB_L0 | ✅ | OUT1 pin connected to USB_L0, which routes to the D- line of USB port A through ESD protection. This pin is the output side of the common mode choke for the negative differential signal. | </details> <details> <summary>CHOKE3 - 3142-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3142-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | IN1 | USB_DN1 | ✅ | IN1 pin connected to USB_DN1, which is the D- signal from the USB controller for port 1. This pin is the input side of the common mode choke for the negative differential signal. | | 3 | IN2 | USB_DP1 | ✅ | IN2 pin connected to USB_DP1, which is the D+ signal from the USB controller for port 1. This pin is the input side of the common mode choke for the positive differential signal. | | 4 | OUT2 | USB_H1 | ✅ | OUT2 pin connected to USB_H1, which routes to the D+ line of USB port B through ESD protection. This pin is the output side of the common mode choke for the positive differential signal. | | 6 | OUT1 | USB_L1 | ✅ | OUT1 pin connected to USB_L1, which routes to the D- line of USB port B through ESD protection. This pin is the output side of the common mode choke for the negative differential signal. | </details> <details> <summary>USB1 - 258-0004503 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0004503) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VBUSA | VBUS1 | ✅ | VBUSA provides power to USB port A. Connected to VBUS1 net with proper decoupling and power switching through U32. | | 2 | DA- | USB_L0 | ✅ | DA- is the USB 2.0 differential pair negative signal for port A. Connected through common mode choke CHOKE4 with ESD protection from U9. | | 3 | DA+ | USB_H0 | ✅ | DA+ is the USB 2.0 differential pair positive signal for port A. Connected through common mode choke CHOKE4 with ESD protection from U9. | | 4 | GNDA | GND | ✅ | GNDA is the ground connection for USB port A, correctly connected to the GND net. | | 5 | SSRX- | USB3_RX0N_C | ✅ | SSRX- is the USB 3.0 SuperSpeed receive negative signal. Connected through common mode choke CHOKE1 with ESD protection from U29. | | 6 | SSRX+ | USB3_RX0P_C | ✅ | SSRX+ is the USB 3.0 SuperSpeed receive positive signal. Connected through common mode choke CHOKE1 with ESD protection from U29. | | 7 | GND_DRAIN | GND | ✅ | GND_DRAIN is a drain/shield ground connection, correctly connected to the GND net. | | 8 | SSTX- | USB3_TX0N_C | ✅ | SSTX- is the USB 3.0 SuperSpeed transmit negative signal. Connected through common mode choke CHOKE2 with ESD protection from U29 and AC coupling capacitor C191. | | 9 | SSTX+ | USB3_TX0P_C | ✅ | SSTX+ is the USB 3.0 SuperSpeed transmit positive signal. Connected through common mode choke CHOKE2 with ESD protection from U29 and AC coupling capacitor C192. | | 10 | VBUSB | VBUS2 | ✅ | VBUSB provides power to USB port B. Connected to VBUS2 net with proper decoupling and power switching through U32. | | 11 | DB- | USB_L1 | ✅ | DB- is the USB 2.0 differential pair negative signal for port B. Connected through common mode choke CHOKE3 with ESD protection from U8. | | 12 | DB+ | USB_H1 | ✅ | DB+ is the USB 2.0 differential pair positive signal for port B. Connected through common mode choke CHOKE3 with ESD protection from U8. | | 13 | GNDB | GND | ✅ | GNDB is the ground connection for USB port B, correctly connected to the GND net. | | MH1 | SHIELD1 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity. | | MH2 | SHIELD2 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity. | | MH3 | SHIELD3 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity. | | MH4 | SHIELD4 | GND_EARTH | ✅ | Shield pins are connected to GND_EARTH for EMI and ESD protection. An optional 8200pF capacitor (C211, DNI) can be populated to couple GND_EARTH to GND for conducted immunity. | </details> <details> <summary>J10 - 158-0004534 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/158-0004534) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 2 | 2 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 13 | 13 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 14 | 14 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 25 | 25 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 26 | 26 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 37 | 37 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 38 | 38 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 49 | 49 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 50 | 50 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 59 | 59 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 60 | 60 | GND | ✅ | Ground pins providing return paths for power and signals throughout the connector. | | 3 | 3 | mSATA_TX_P | ✅ | mSATA transmit differential pair (TX_P and TX_N) for SATA interface. | | 5 | 5 | mSATA_TX_N | ✅ | mSATA transmit differential pair (TX_P and TX_N) for SATA interface. | | 4 | 4 | mSATA_RX_P | ✅ | mSATA receive differential pair (RX_P and RX_N) for SATA interface. | | 6 | 6 | mSATA_RX_N | ✅ | mSATA receive differential pair (RX_P and RX_N) for SATA interface. | | 7 | 7 | +5VSB | ✅ | 5V standby power supply pins distributed throughout the connector. | | 8 | 8 | +5VSB | ✅ | 5V standby power supply pins distributed throughout the connector. | | 19 | 19 | +5VSB | ✅ | 5V standby power supply pins distributed throughout the connector. | | 20 | 20 | +5VSB | ✅ | 5V standby power supply pins distributed throughout the connector. | | 31 | 31 | +5VSB | ✅ | 5V standby power supply pins distributed throughout the connector. | | 32 | 32 | +5VSB | ✅ | 5V standby power supply pins distributed throughout the connector. | | 43 | 43 | +5VSB | ✅ | 5V standby power supply pins distributed throughout the connector. | | 44 | 44 | +5VSB | ✅ | 5V standby power supply pins distributed throughout the connector. | | 9 | 9 | mPCIE_REFCLK_P | ✅ | mPCIE reference clock differential pair (REFCLK_P and REFCLK_N). | | 11 | 11 | mPCIE_REFCLK_N | ✅ | mPCIE reference clock differential pair (REFCLK_P and REFCLK_N). | | 10 | 10 | USB_HOST_DP | ✅ | USB host differential pair (D+ and D-) for USB 2.0 interface. | | 12 | 12 | USB_HOST_DN | ✅ | USB host differential pair (D+ and D-) for USB 2.0 interface. | | 15 | 15 | mPCIE_TX_P | ✅ | mPCIE transmit differential pair (TX_P and TX_N) for PCIe interface. | | 17 | 17 | mPCIE_TX_N | ✅ | mPCIE transmit differential pair (TX_P and TX_N) for PCIe interface. | | 16 | 16 | mPCIE_RX_N | ✅ | mPCIE receive differential pair (RX_N and RX_P) for PCIe interface. Note indicates intentional polarity inversion for routing ease. | | 18 | 18 | mPCIE_RX_P | ✅ | mPCIE receive differential pair (RX_N and RX_P) for PCIe interface. Note indicates intentional polarity inversion for routing ease. | | 21 | 21 | I2C6_SCL | ✅ | I2C clock line with 10K pullup resistor to +V1P8S. | | 22 | 22 | mPCIE_WAKEB | ✅ | Mini-PCIe wake signal (active low). | | 23 | 23 | I2C6_SDA | ✅ | I2C data line with 10K pullup resistor to +V1P8S. | | 24 | 24 | mPCIe_CLKREQ3_B | ✅ | Mini-PCIe clock request signal (active low). | | 27 | 27 | EXP_GPIO1 | ✅ | General purpose I/O expansion pins. | | 28 | 28 | EXP_GPIO3 | ✅ | General purpose I/O expansion pins. | | 29 | 29 | EXP_GPIO2 | ✅ | General purpose I/O expansion pins. | | 30 | 30 | EXP_GPIO4 | ✅ | General purpose I/O expansion pins. | | 33 | 33 | XDP_H_OBSDATA_A1 | ✅ | XDP observation data bus signals for debug interface. | | 34 | 34 | XDP_H_OBSDATA_A0 | ✅ | XDP observation data bus signals for debug interface. | | 35 | 35 | XDP_H_OBSDATA_A2 | ✅ | XDP observation data bus signals for debug interface. | | 36 | 36 | XDP_H_OBSDATA_A3 | ✅ | XDP observation data bus signals for debug interface. | | 39 | 39 | XDP_H_PRDYB | ✅ | XDP probe ready signal (active low). | | 40 | 40 | XDP_H_PREQB_PB | ✅ | XDP probe request signal (active low) with buffer and pullup. | | 41 | 41 | HOOK0 | ✅ | Hook signal connected through 1K resistor to PMC_RSMRST. | | 42 | 42 | HOOK1 | ✅ | Hook signal connected through 0 ohm resistor to front panel power button. | | 45 | 45 | HOOK2 | ✅ | Hook signal connected through 1K resistor to PMC_CORE_PWROK. | | 46 | 46 | PMC_RSTBTN | ✅ | PMC reset button signal with RC filtering (1K pullup and 0.1uF capacitor). | | 47 | 47 | HOOK6 | ✅ | Hook signal connected through 1K resistor to PMC_PLTRST_R_V1P8. | | 48 | 48 | ILB_RTC_TESTB | ✅ | RTC test signal (active low) with RC filtering (1K pullup and 1uF capacitor). | | 51 | 51 | HOOK4 | ✅ | Hook signal connected through 0 ohm resistor to +3VSB. | | 52 | 52 | XDP_H_TRSTB | ✅ | JTAG test reset signal (active low) for XDP debug interface. | | 53 | 53 | HOOK5 | ✅ | Hook signal connected through 0 ohm resistor to +V1P8S. | | 54 | 54 | XDP_H_TCK | ✅ | JTAG test clock signal for XDP debug interface. | | 55 | 55 | +V1P8A | ✅ | 1.8V analog power supply with 0.1uF decoupling capacitor. | | 56 | 56 | XDP_H_TMS | ✅ | JTAG test mode select signal for XDP debug interface. | | 57 | 57 | XDP_H_TDO | ✅ | JTAG test data out signal with 51 ohm pullup resistor. | | 58 | 58 | XDP_H_TDI | ✅ | JTAG test data in signal for XDP debug interface. | </details> <details> <summary>R3 - 200 ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | XDP_H_PREQB_PB | ✅ | Connected to XDP_H_PREQB_PB input signal from expansion connector J10 pin 40. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A supply, providing pull-up function for the input signal. | </details> <details> <summary>C5 - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND for decoupling capacitor function. | | 2 | 2 | +V1P8A | ✅ | Connected to +V1P8A supply, providing decoupling for U1 VCC pin. | </details> <details> <summary>U1 - SN74AUP1G34 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](http://www.ti.com/lit/gpn/SN74AUP1G34) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/SN74AUP1G34) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | NC | | ✅ | NC pin is correctly left unconnected as specified in the datasheet. | | 2 | A | XDP_H_PREQB_PB | ✅ | Input A is connected to XDP_H_PREQB_PB signal with a 200 ohm pull-up resistor to +V1P8A, providing a strong pull-up for the debug interface. | | 3 | GND | GND | ✅ | Ground pin is correctly connected to the GND net. | | 4 | Y | XDP_H_PREQB | ✅ | Output Y is connected to XDP_H_PREQB net, providing the buffered output signal. | | 5 | VCC | +V1P8A | ✅ | VCC pin is correctly connected to +V1P8A supply with proper 0.1uF bypass capacitor. | </details> <details> <summary>R13 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SCL | ✅ | Pin 1 connects to I2C6_SCL signal line, which goes to connector J10 pin 21. This is the pull-up connection point for the I2C clock line. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S power rail, providing the pull-up voltage for the I2C clock line. This is the correct configuration for an I2C pull-up resistor. | </details> <details> <summary>R14 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2C6_SDA | ✅ | Pin 1 connects to I2C6_SDA signal line, which goes to connector J10 pin 23. This is the pull-up connection point for the I2C data line. | | 2 | 2 | +V1P8S | ✅ | Pin 2 connects to +V1P8S power rail, providing the pull-up voltage for the I2C data line. This is the correct configuration for an I2C pull-up resistor. | </details> <details> <summary>R6 - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSTBTN | ✅ | Connected to PMC_RSTBTN signal, which goes to expansion connector J10 pin 46. Forms pull-up resistor with pin 2 to +V1P8S. | | 2 | 2 | +V1P8S | ✅ | Connected to +V1P8S power rail, providing pull-up voltage for PMC_RSTBTN signal. | </details> <details> <summary>C1 - 123-0001056 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PMC_RSTBTN | ✅ | Connected to PMC_RSTBTN signal, providing filtering and debouncing for the reset button signal. | | 2 | 2 | GND | ✅ | Connected to GND, completing the filter capacitor circuit. | </details> <details> <summary>C2 - 123-0001066 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connected to GND, completing the filter capacitor circuit. | | 2 | 2 | ILB_RTC_TESTB | ✅ | Connected to ILB_RTC_TESTB signal, providing filtering for the RTC test signal. | </details> <details> <summary>R7 - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | ILB_RTC_TESTB | ✅ | Connected to ILB_RTC_TESTB signal, which goes to expansion connector J10 pin 48. Forms pull-up resistor with pin 2 to +RTCVCC. | | 2 | 2 | +RTCVCC | ✅ | Connected to +RTCVCC power rail, providing pull-up voltage for ILB_RTC_TESTB signal. | </details> <details> <summary>R4 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 connects to GND. This resistor is marked DNI (Do Not Install) so it is not populated on the board. | | 2 | 2 | HOOK1 | ✅ | Pin 2 connects to HOOK1 net. This resistor is marked DNI (Do Not Install) so it is not populated on the board. | </details> <details> <summary>R5 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | HOOK1 | ✅ | Pin 1 connects to HOOK1 net from expansion connector J10 pin 42. This is the input side of the 0-ohm resistor. | | 2 | 2 | FP_PWRBTN | ✅ | Pin 2 connects to FP_PWRBTN net, which is the front panel power button signal. This is the output side of the 0-ohm resistor. | </details> <details> <summary>R21 - 110-0002078 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | 51 ohm resistor connecting XDP_H_TDO to +V1P8A power rail, functioning as a pull-up resistor. The value is unusually low for a typical pull-up resistor. | | 2 | 2 | XDP_H_TDO | ✅ | 51 ohm resistor connecting XDP_H_TDO to +V1P8A power rail, functioning as a pull-up resistor. The value is unusually low for a typical pull-up resistor. | </details> <details> <summary>U42 - WGI210AT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4300-0071) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | LAN_PWR_GOOD | $18N3538 | ✅ | LAN_PWR_GOOD is pulled up to +3VSB_LAN through a 10K resistor, indicating this is a power good output signal. | | 2 | NC_SI_CLK_IN | $18N3372 | ✅ | NC_SI_CLK_IN is terminated to ground through a 1K resistor, which is appropriate for an unused input signal. | | 3 | NC_SI_CRS_DV | $18N3374 | ✅ | NC_SI_CRS_DV is terminated to ground through a 1K resistor, which is appropriate for an unused input signal. | | 4 | JTAG_TDO | | ✅ | JTAG_TDO is left unconnected, which is acceptable for a JTAG output pin when JTAG is not being used. | | 5 | NC_SI_RXD1 | $18N3305 | ✅ | NC_SI_RXD1 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal. | | 6 | NC_SI_RXD0 | $18N3303 | ✅ | NC_SI_RXD0 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal. | | 7 | NC_SI_TX_EN | $18N3376 | ✅ | NC_SI_TX_EN is terminated to ground through a 1K resistor, which is appropriate for an unused input signal. | | 8 | NC_SI_TXD1 | $18N3301 | ✅ | NC_SI_TXD1 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal. | | 9 | NC_SI_TXD0 | $18N3299 | ✅ | NC_SI_TXD0 is pulled up to +3VSB_LAN through a 10K resistor, which is appropriate for an unused input signal. | | 10 | VDD3P3_10 | +3VSB_LAN | ✅ | VDD3P3_10 is correctly connected to the +3VSB_LAN power rail. | | 11 | VDD0P9_11 | +0V9_LAN | ✅ | VDD0P9_11 is correctly connected to the +0V9_LAN power rail. | | 12 | NVM_SI | $18N2399 | ✅ | NVM_SI is correctly connected to the SPI flash MOSI line through a 33.2 ohm series resistor for signal integrity. | | 13 | NVM_SK | $18N2397 | ✅ | NVM_SK is correctly connected to the SPI flash clock line through a 33.2 ohm series resistor for signal integrity. | | 14 | NVM_SO | $18N3554 | ✅ | NVM_SO is correctly connected to the SPI flash MISO line through a 33.2 ohm series resistor for signal integrity. | | 15 | NVM_CS_N | $18N2395 | ✅ | NVM_CS_N is correctly connected to the SPI flash chip select line through a 33.2 ohm series resistor for signal integrity. | | 16 | PE_WAKE_N | PMC_PCIE_WAKE | ✅ | PE_WAKE_N is connected to the PCIe wake signal going to the system controller. | | 17 | PE_RST_N | PMC_PLTRST_L | ✅ | PE_RST_N is connected to the platform reset signal from the system controller. | | 18 | JTAG_TMS | $18N3293 | ✅ | JTAG_TMS is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces. | | 19 | JTAG_CLK | $18N3295 | ✅ | JTAG_CLK is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces. | | 20 | PE_TXN | PCIE_C_RXP2 | ✅ | PE_TXN and PE_TXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification. | | 21 | PE_TXP | PCIE_C_RXN2 | ✅ | PE_TXN and PE_TXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification. | | 22 | NC/INTVCC | | ✅ | NC/INTVCC is left unconnected, which is acceptable as this pin can be either not connected or used for internal VCC depending on configuration. | | 23 | PE_RXN | PCIE_C_TXP2 | ✅ | PE_RXN and PE_RXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification. | | 24 | PE_RXP | PCIE_C_TXN2 | ✅ | PE_RXN and PE_RXP have intentional polarity inversion as documented in the schematic notes. This is acceptable per PCIe specification. | | 25 | PECLK_N | PCIE_CLK-N2 | ✅ | PECLK_N is correctly connected to the PCIe reference clock negative signal. | | 26 | PECLK_P | PCIE_CLK-P2 | ✅ | PECLK_P is correctly connected to the PCIe reference clock positive signal. | | 27 | VDD3P3_27 | +3VSB_LAN | ✅ | VDD3P3_27 is correctly connected to the +3VSB_LAN power rail. | | 28 | DEV_OFF_N | $18N3540 | ✅ | DEV_OFF_N is pulled up to +3VSB_LAN through a 10K resistor, keeping the device enabled by default. | | 29 | JTAG_TDI | $18N3297 | ✅ | JTAG_TDI is pulled up to +3VSB_LAN through a 10K resistor, which is standard for JTAG interfaces. | | 30 | LED1 | LAN-LED1 | ✅ | LED1 is connected to an off-page signal for LED control. | | 31 | LED0 | LAN-LED0 | ✅ | LED0 is correctly connected to the RJ45 connector LED with appropriate filtering. | | 32 | VDD0P9_32 | +0V9_LAN | ✅ | VDD0P9_32 is correctly connected to the +0V9_LAN power rail. | | 33 | LED2 | LAN-LED2 | ✅ | LED2 is correctly connected to the RJ45 connector LED through a current limiting resistor. | | 34 | SMB_CLK | LAN-SMB-CLK | ✅ | SMB_CLK is connected to an off-page SMBus clock signal. | | 35 | SMB_ALRT_N | LAN-SMB-ALERT# | ✅ | SMB_ALRT_N is connected to an off-page SMBus alert signal. | | 36 | SMB_DATA | LAN-SMB-DATA | ✅ | SMB_DATA is connected to an off-page SMBus data signal. | | 37 | CBOT | $18N2590 | ✅ | CBOT and CTOP are correctly connected through a 0.039uF compensation capacitor for the internal regulators. | | 40 | CTOP | $18N2588 | ✅ | CBOT and CTOP are correctly connected through a 0.039uF compensation capacitor for the internal regulators. | | 38 | VDD0P9_OUT | +0V9_LAN | ✅ | VDD0P9_OUT is connected to the +0V9_LAN rail, indicating the internal 0.9V regulator output is being used. | | 39 | VDD1P5_OUT | +1V5_LAN | ✅ | VDD1P5_OUT is connected to the +1V5_LAN rail, indicating the internal 1.5V regulator output is being used. | | 41 | VDD3P3_41 | +3VSB_LAN | ✅ | VDD3P3_41 is correctly connected to the +3VSB_LAN power rail. | | 42 | VDD0P9_42 | +0V9_LAN | ✅ | VDD0P9_42 is correctly connected to the +0V9_LAN power rail. | | 43 | NC_SI_ARB_IN | | ✅ | NC_SI_ARB_IN is left unconnected, which is acceptable for an unused signal. | | 44 | NC_SI_ARB_OUT | | ✅ | NC_SI_ARB_OUT is left unconnected, which is acceptable for an unused output signal. | | 45 | XTAL2 | LAN_XTAL2 | ✅ | XTAL2 and XTAL1 are correctly connected to a 25MHz crystal with appropriate load capacitors. | | 46 | XTAL1 | LAN_XTAL1 | ✅ | XTAL2 and XTAL1 are correctly connected to a 25MHz crystal with appropriate load capacitors. | | 47 | VDD1P5_47 | +1V5_LAN | ✅ | VDD1P5_47 is correctly connected to the +1V5_LAN power rail. | | 48 | RSET | LAN_RSET | ✅ | RSET is correctly connected to ground through a 4.99K resistor to set the PHY reference current. | | 49 | MDI_MINUS3/SER_N | MDI_N3 | ✅ | MDI_MINUS3 and MDI_PLUS3 are correctly connected to the RJ45 connector for Ethernet pair 3. | | 50 | MDI_PLUS3/SER_P | MDI_P3 | ✅ | MDI_MINUS3 and MDI_PLUS3 are correctly connected to the RJ45 connector for Ethernet pair 3. | | 51 | VDD3P3_51 | +3VSB_LAN | ✅ | VDD3P3_51 is correctly connected to the +3VSB_LAN power rail. | | 52 | MDI_MINUS2/SET_N | MDI_N2 | ✅ | MDI_MINUS2 and MDI_PLUS2 are correctly connected to the RJ45 connector for Ethernet pair 2. | | 53 | MDI_PLUS2 | MDI_P2 | ✅ | MDI_MINUS2 and MDI_PLUS2 are correctly connected to the RJ45 connector for Ethernet pair 2. | | 54 | MDI_MINUS1/SRDS_SIG_DET | MDI_N1 | ✅ | MDI_MINUS1 and MDI_PLUS1 are correctly connected to the RJ45 connector for Ethernet pair 1. | | 55 | MDI_PLUS1/SFP_I2C_CLK | MDI_P1 | ✅ | MDI_MINUS1 and MDI_PLUS1 are correctly connected to the RJ45 connector for Ethernet pair 1. | | 56 | VDD1P5_56 | +1V5_LAN | ✅ | VDD1P5_56 is correctly connected to the +1V5_LAN power rail. | | 57 | MDI_MINUS0/SFP_I2C_DATA | MDI_N0 | ✅ | MDI_MINUS0 and MDI_PLUS0 are correctly connected to the RJ45 connector for Ethernet pair 0. | | 58 | MDI_PLUS0/NC | MDI_P0 | ✅ | MDI_MINUS0 and MDI_PLUS0 are correctly connected to the RJ45 connector for Ethernet pair 0. | | 59 | VDD0P9_59 | +0V9_LAN | ✅ | VDD0P9_59 is correctly connected to the +0V9_LAN power rail. | | 60 | SDP3 | | ✅ | SDP3 is left unconnected, which is acceptable for an unused software-defined pin. | | 61 | SDP1/PCIE_DIS | | ✅ | SDP1/PCIE_DIS is left unconnected, which is acceptable for an unused software-defined pin. | | 62 | SDP2 | | ✅ | SDP2 is left unconnected, which is acceptable for an unused software-defined pin. | | 63 | SDP0 | | ✅ | SDP0 is left unconnected, which is acceptable for an unused software-defined pin. | | 64 | VDD3P3_64 | +3VSB_LAN | ✅ | VDD3P3_64 is correctly connected to the +3VSB_LAN power rail. | | 65 | GND_PAD | GND | ✅ | GND_PAD is correctly connected to the ground plane. | </details> <details> <summary>R832 - 33.2Ω ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2435 | ✅ | Connected to SI line (net $18N2435) of U43, providing series resistance for signal integrity. | | 2 | 2 | $18N2399 | ✅ | Series resistor on the SI (Serial Input) line between U42 and U43, providing signal integrity and impedance matching. Pin 2 connects to U42 NVM_SI. | </details> <details> <summary>R833 - 33.2Ω ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3554 | ✅ | Connected to NVM_SO line (net $18N3554) from U42, providing series resistance for signal integrity. | | 2 | 2 | $18N3552 | ✅ | Series resistor on the SO (Serial Output) line between U43 and U42, providing signal integrity and impedance matching. Pin 2 connects to U43 SO. | </details> <details> <summary>R834 - 33.2Ω ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2437 | ✅ | Connected to SCK line (net $18N2437) of U43, providing series resistance for signal integrity. | | 2 | 2 | $18N2397 | ✅ | Series resistor on the SCK (Serial Clock) line between U42 and U43, providing signal integrity and impedance matching. Pin 2 connects to U42 NVM_SK. | </details> <details> <summary>R835 - 33.2Ω ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0003) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N2439 | ✅ | Connected to CS# line (net $18N2439) of U43, providing series resistance for signal integrity. | | 2 | 2 | $18N2395 | ✅ | Series resistor on the CS# (Chip Select) line between U42 and U43, providing signal integrity and impedance matching. Pin 2 connects to U42 NVM_CS_N. | </details> <details> <summary>R830 - 10.0KΩ ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Connected to +3VSB_LAN power supply, providing pull-up voltage source. | | 2 | 2 | $18N3609 | ✅ | Pull-up resistor for WP# (Write Protect) pin on U43. Pin 2 connects to U43 WP#, pulling it high to disable hardware write protection. | </details> <details> <summary>R831 - 10.0KΩ ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +3VSB_LAN | ✅ | Connected to +3VSB_LAN power supply, providing pull-up voltage source. | | 2 | 2 | $18N3659 | ✅ | Pull-up resistor for HOLD# pin on U43. Pin 2 connects to U43 HOLD#, pulling it high to disable the hold function. | </details> <details> <summary>R829 - 10.0KΩ ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3609 | ✅ | Connected to WP# line (net $18N3609) of U43. This resistor is DNI (Do Not Install), so it is not electrically present in the circuit. | | 2 | 2 | GND | ✅ | DNI (Do Not Install) pull-down resistor for WP# pin. When not installed, WP# is pulled high only through R830, disabling hardware write protection. Pin 2 connects to GND. | </details> <details> <summary>U43 - AT25DF081A-SSH ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.renesas.com/us/en/document/dst/at25df081a-datasheet?language=en) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4356-0082) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | $18N2439 | ✅ | CS# (Chip Select) is correctly connected to the LAN controller U42 through series resistor R835 (33.2Ω) for signal integrity and protection. | | 2 | SO | $18N3552 | ✅ | SO (Serial Output) is correctly connected to the LAN controller U42 through series resistor R833 (33.2Ω) for signal integrity and protection. | | 3 | WP# | $18N3609 | ✅ | WP# (Write Protect) is correctly pulled up to +3VSB_LAN through R830 (10KΩ), keeping the pin inactive (high) as recommended by the datasheet. | | 4 | GND | GND | ✅ | GND is correctly connected to the ground plane. | | 5 | SI | $18N2435 | ✅ | SI (Serial Input) is connected to the LAN controller U42 through series resistor R832 (33.2Ω), with an additional weak pull-up R848 (33.2KΩ) to +3VSB_LAN. The pull-up is unusual but acceptable as it's weak enough not to interfere with the SPI master driving the line. | | 6 | SCK | $18N2437 | ✅ | SCK (Serial Clock) is correctly connected to the LAN controller U42 through series resistor R834 (33.2Ω) for signal integrity and protection. | | 7 | HOLD# | $18N3659 | ✅ | HOLD# is correctly pulled up to +3VSB_LAN through R831 (10KΩ), keeping the pin inactive (high) as recommended by the datasheet. | | 8 | VCC | +3VSB_LAN | ✅ | VCC is correctly connected to +3VSB_LAN (3.3V standby power), which is within the specified operating range of 2.7V to 3.6V. | </details> <details> <summary>C252 - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001107) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL1 | ✅ | Load capacitor for crystal oscillator, connected to LAN_XTAL1 net (X1 pin 3 and U42 pin 46). | | 2 | 2 | GND | ✅ | Ground connection for load capacitor. | </details> <details> <summary>X1 - 145-0004792 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/145-0004792) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | Crystal active pin connected to U42 XTAL2 (pin 45) with 27pF load capacitor C253 to ground. This is a standard crystal oscillator configuration. | | 2 | 2 | GND | ✅ | Crystal ground pin correctly connected to GND for shielding and stability. | | 3 | 3 | LAN_XTAL1 | ✅ | Crystal active pin connected to U42 XTAL1 (pin 46) with 27pF load capacitor C252 to ground. This is a standard crystal oscillator configuration. | | 4 | 4 | GND | ✅ | Crystal ground pin correctly connected to GND for shielding and stability. | </details> <details> <summary>C253 - 123-0001107 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001107) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN_XTAL2 | ✅ | Load capacitor for crystal oscillator, connected to LAN_XTAL2 net (X1 pin 1 and U42 pin 45). | | 2 | 2 | GND | ✅ | Ground connection for load capacitor. | </details> <details> <summary>R843 - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0203) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED1 | ✅ | Pin 1 connects to LAN-LED1 net, which routes to U42 pin 30 (LED1 output). | | 2 | 2 | LINK-LED-N | ✅ | Pin 2 connects to LINK-LED-N net, which routes to J11 pin 13 (LED1_C cathode). | </details> <details> <summary>R844 - 1120-0203 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0203) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED2 | ✅ | Pin 1 connects to LAN-LED2 net, which routes to U42 pin 33 (LED2 output). | | 2 | 2 | 1G-LED-N | ✅ | Pin 2 connects to 1G-LED-N net, which routes to J11 pin 12 (LED2_AD1 cathode). | </details> <details> <summary>C429 - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LINK-LED-N | ✅ | Pin 1 connects to LINK-LED-N net for high-frequency noise filtering. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND for filtering. | </details> <details> <summary>C430 - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1G-LED-N | ✅ | Pin 1 connects to 1G-LED-N net for high-frequency noise filtering. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND for filtering. | </details> <details> <summary>C431 - 2220-0039 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2220-0039) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | LAN-LED0 | ✅ | Pin 1 connects to LAN-LED0 net for high-frequency noise filtering. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND for filtering. | </details> <details> <summary>C426 - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Pin 1 connects to the center tap net $18N3856 for common mode filtering. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND for common mode filtering. | </details> <details> <summary>C427 - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2222-0016) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Pin 1 connects to the center tap net $18N3856 for common mode filtering, in parallel with C426 and C428. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND for common mode filtering. | </details> <details> <summary>C428 - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2222-0014) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $18N3856 | ✅ | Pin 1 connects to the center tap net $18N3856 for common mode filtering, in parallel with C426 and C427. | | 2 | 2 | GND | ✅ | Pin 2 connects to GND for common mode filtering. | </details> <details> <summary>J11 - RJ45 W XFMR GRN-ORN GRN LEDS ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3362-0042) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | MD1+ | MDI_P0 | ✅ | MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation. | | 2 | MD1- | MDI_N0 | ✅ | MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation. | | 3 | MD2+ | MDI_P1 | ✅ | MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation. | | 4 | MD2- | MDI_N1 | ✅ | MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation. | | 7 | MD3+ | MDI_P2 | ✅ | MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation. | | 8 | MD3- | MDI_N2 | ✅ | MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation. | | 9 | MD4+ | MDI_P3 | ✅ | MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation. | | 10 | MD4- | MDI_N3 | ✅ | MDI differential pairs correctly connected to U42 Ethernet controller for 1000BASE-T operation. | | 5 | CT1 | $18N3856 | ✅ | Center tap pins correctly connected to common net with AC coupling capacitors to ground for common-mode filtering. | | 6 | CT2 | $18N3856 | ✅ | Center tap pins correctly connected to common net with AC coupling capacitors to ground for common-mode filtering. | | 11 | LED2_AC1 | LAN-LED0 | ✅ | LED2 pins configured as bi-color LED with pin 11 driven directly by U42 LED0 and pin 12 driven through R844 by U42 LED2. Pin 11 lacks a series current-limiting resistor, which is inconsistent with other LED connections but may be intentional depending on controller configuration or connector design. | | 12 | LED2_AD1 | 1G-LED-N | ✅ | LED2 pins configured as bi-color LED with pin 11 driven directly by U42 LED0 and pin 12 driven through R844 by U42 LED2. Pin 11 lacks a series current-limiting resistor, which is inconsistent with other LED connections but may be intentional depending on controller configuration or connector design. | | 13 | LED1_C | LINK-LED-N | ✅ | LED1 pins correctly configured with pin 14 as anode connected to +3VSB_LAN and pin 13 as cathode driven through R843 by U42 LED1 output. | | 14 | LED1_A | +3VSB_LAN | ✅ | LED1 pins correctly configured with pin 14 as anode connected to +3VSB_LAN and pin 13 as cathode driven through R843 by U42 LED1 output. | | 15 | SHLD1 | GND_EARTH | ✅ | Shield pins correctly connected to GND_EARTH for EMI shielding. | | 16 | SHLD2 | GND_EARTH | ✅ | Shield pins correctly connected to GND_EARTH for EMI shielding. | </details> <details> <summary>U10 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA pin correctly connected to +V1P8A (1.8V supply) with proper decoupling. | | 2 | A1 | SOC_GPIO_S5_2 | ✅ | A1 pin correctly connected to SOC_GPIO_S5_2 on the 1.8V side. | | 3 | A2 | SOC_GPIO_S5_1 | ✅ | A2 pin correctly connected to SOC_GPIO_S5_1 on the 1.8V side. | | 4 | A3 | SOC_GPIO_S5_0 | ✅ | A3 pin correctly connected to SOC_GPIO_S5_0 on the 1.8V side. | | 5 | A4 | | ✅ | A4 (pin 5) is not connected while B4 (pin 7) is tied to GND. This is a non-standard configuration for an unused channel that causes minor power consumption but should not affect functionality. | | 7 | B4 | GND | ✅ | A4 (pin 5) is not connected while B4 (pin 7) is tied to GND. This is a non-standard configuration for an unused channel that causes minor power consumption but should not affect functionality. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground. | | 8 | B3 | GPIO_S5_0 | ✅ | B3 pin correctly connected to GPIO_S5_0 on the 3.3V side. | | 9 | B2 | GPIO_S5_1 | ✅ | B2 pin correctly connected to GPIO_S5_1 on the 3.3V side. | | 10 | B1 | GPIO_S5_2 | ✅ | B1 pin correctly connected to GPIO_S5_2 on the 3.3V side. | | 11 | VCCB | +PS_3VSB | ✅ | VCCB pin correctly connected to +PS_3VSB (3.3V supply) with proper decoupling. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal. | </details> <details> <summary>U17 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V supply) with proper decoupling. | | 2 | A1 | I2S_MCLK | ✅ | A1 pin correctly connected to I2S_MCLK on the 1.8V side. | | 3 | A2 | SOC_PWM1 | ✅ | A2 pin correctly connected to SOC_PWM1 on the 1.8V side. | | 4 | A3 | SOC_PWM0 | ✅ | A3 pin correctly connected to SOC_PWM0 on the 1.8V side. | | 5 | A4 | | ✅ | A4 (pin 5) is not connected while B4 (pin 7) is tied to GND. This is a non-standard configuration for an unused channel that causes minor power consumption but should not affect functionality. | | 7 | B4 | GND | ✅ | A4 (pin 5) is not connected while B4 (pin 7) is tied to GND. This is a non-standard configuration for an unused channel that causes minor power consumption but should not affect functionality. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground. | | 8 | B3 | PWM0 | ✅ | B3 pin correctly connected to PWM0 on the 3.3V side. | | 9 | B2 | PWM1 | ✅ | B2 pin correctly connected to PWM1 on the 3.3V side. | | 10 | B1 | I2SMCLK_GPIO | ✅ | B1 pin correctly connected to I2SMCLK_GPIO on the 3.3V side. | | 11 | VCCB | +3VSB | ✅ | VCCB pin correctly connected to +3VSB (3.3V supply) with proper decoupling. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal. | </details> <details> <summary>U16 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V supply) with proper decoupling. | | 2 | A1 | I2S_DATIN_R | ✅ | A1 pin correctly connected to I2S_DATIN_R on the 1.8V side, with series resistor R128 to LPE_I2S_DATIN. | | 3 | A2 | I2S_DATOUT_R | ✅ | A2 pin correctly connected to I2S_DATOUT_R on the 1.8V side, with series resistor R130 to LPE_I2S_DATOUT. | | 4 | A3 | I2S_FRM_R | ✅ | A3 pin correctly connected to I2S_FRM_R on the 1.8V side, with series resistor R129 to LPE_I2S_FRM. | | 5 | A4 | I2S_CLK_R | ✅ | A4 pin correctly connected to I2S_CLK_R on the 1.8V side, with series resistor R127 to LPE_I2S_CLK. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground. | | 7 | B4 | I2SCLK_GPIO | ✅ | B4 pin correctly connected to I2SCLK_GPIO on the 3.3V side. | | 8 | B3 | I2SFRM_GPIO | ✅ | B3 pin correctly connected to I2SFRM_GPIO on the 3.3V side. | | 9 | B2 | I2SDO_GPIO | ✅ | B2 pin correctly connected to I2SDO_GPIO on the 3.3V side. | | 10 | B1 | I2SDI_GPIO | ✅ | B1 pin correctly connected to I2SDI_GPIO on the 3.3V side. | | 11 | VCCB | +3VSB | ✅ | VCCB pin correctly connected to +3VSB (3.3V supply) with proper decoupling. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal. | </details> <details> <summary>U7 - NTS0102GT ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTS0102GT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | B2 | UART2_RXD | ✅ | B2 pin correctly connected to UART2_RXD on the 3.3V side of the level translator. | | 2 | GND | GND | ✅ | GND pin correctly connected to ground. | | 3 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V supply) with proper decoupling. | | 4 | A2 | SIO_UART2_RXD | ✅ | A2 pin correctly connected to SIO_UART2_RXD on the 1.8V side of the level translator. | | 5 | A1 | SIO_UART2_TXD | ✅ | A1 pin correctly connected to SIO_UART2_TXD on the 1.8V side of the level translator. | | 6 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal to enable translation when platform is active. | | 7 | VCCB | +3VSB | ✅ | VCCB pin correctly connected to +3VSB (3.3V supply) with proper decoupling. | | 8 | B1 | UART2_TXD | ✅ | B1 pin correctly connected to UART2_TXD on the 3.3V side of the level translator. | </details> <details> <summary>U15 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V supply) with proper decoupling. | | 2 | A1 | SIO_UART1_RTSB | ✅ | A1 pin correctly connected to SIO_UART1_RTSB on the 1.8V side. | | 3 | A2 | SIO_UART1_CTSB | ✅ | A2 pin correctly connected to SIO_UART1_CTSB on the 1.8V side. | | 4 | A3 | SIO_UART1_RXD | ✅ | A3 pin correctly connected to SIO_UART1_RXD on the 1.8V side. | | 5 | A4 | SIO_UART1_TXD | ✅ | A4 pin correctly connected to SIO_UART1_TXD on the 1.8V side. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground. | | 7 | B4 | UART1_TXD | ✅ | B4 pin correctly connected to UART1_TXD on the 3.3V side. | | 8 | B3 | UART1_RXD | ✅ | B3 pin correctly connected to UART1_RXD on the 3.3V side. | | 9 | B2 | UART1_CTSB | ✅ | B2 pin correctly connected to UART1_CTSB on the 3.3V side. | | 10 | B1 | UART1_RTSB | ✅ | B1 pin correctly connected to UART1_RTSB on the 3.3V side. | | 11 | VCCB | +3VSB | ✅ | VCCB pin correctly connected to +3VSB (3.3V supply) with proper decoupling. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal. | </details> <details> <summary>U18 - NTB0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTB0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8A | ✅ | VCCA pin correctly connected to +V1P8A (1.8V supply) with proper decoupling. | | 2 | A1 | SOC_SPI_MOSI-R | ✅ | A1 pin correctly connected to SOC_SPI_MOSI-R on the 1.8V side. | | 3 | A2 | SOC_SPI_CLK-R | ✅ | A2 pin correctly connected to SOC_SPI_CLK-R on the 1.8V side. | | 4 | A3 | SOC_SPI_MISO-R | ✅ | A3 pin correctly connected to SOC_SPI_MISO-R on the 1.8V side. | | 5 | A4 | SOC_SPI_CS0B-R | ✅ | A4 pin correctly connected to SOC_SPI_CS0B-R on the 1.8V side. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground. | | 7 | B4 | SPI_CS0 | ✅ | B4 pin correctly connected to SPI_CS0 which connects to the SPI flash chip select. | | 8 | B3 | SPI_MISO | ✅ | B3 pin correctly connected to SPI_MISO which connects to the SPI flash data output. | | 9 | B2 | SPI_CLK | ✅ | B2 pin correctly connected to SPI_CLK which connects to the SPI flash clock input. | | 10 | B1 | SPI_MOSI | ✅ | B1 pin correctly connected to SPI_MOSI which connects to the SPI flash data input. | | 11 | VCCB | +V_SPI | ✅ | VCCB pin correctly connected to +V_SPI, which is a selectable voltage supply (1.8V or 3.3V) for the SPI flash, with proper decoupling. | | 12 | OE | DDP_IO3L | ✅ | OE pin correctly connected to DDP_IO3L with 100K pull-up to +V1P8A, allowing DediProg programmer to control translator enable. | </details> <details> <summary>U14 - NTS0104GU12 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTS0104GU12) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VCCA | +V1P8S | ✅ | VCCA pin correctly connected to +V1P8S (1.8V supply) with proper decoupling. | | 2 | A1 | SOC_SIO_SPI_CLK | ✅ | A1 pin correctly connected to SOC_SIO_SPI_CLK on the 1.8V side. | | 3 | A2 | SOC_SIO_SPI_MOSI | ✅ | A2 pin correctly connected to SOC_SIO_SPI_MOSI on the 1.8V side. | | 4 | A3 | SOC_SIO_SPI_MISO | ✅ | A3 pin correctly connected to SOC_SIO_SPI_MISO on the 1.8V side. | | 5 | A4 | SOC_SIO_SPI_CS1 | ✅ | A4 pin correctly connected to SOC_SIO_SPI_CS1 on the 1.8V side. | | 6 | GND | GND | ✅ | GND pin correctly connected to ground. | | 7 | B4 | SIO_SPI_CS1 | ✅ | B4 pin correctly connected to SIO_SPI_CS1 on the 3.3V side. | | 8 | B3 | SIO_SPI_MISO | ✅ | B3 pin correctly connected to SIO_SPI_MISO on the 3.3V side. | | 9 | B2 | SIO_SPI_MOSI | ✅ | B2 pin correctly connected to SIO_SPI_MOSI on the 3.3V side. | | 10 | B1 | SIO_SPI_CLK | ✅ | B1 pin correctly connected to SIO_SPI_CLK on the 3.3V side. | | 11 | VCCB | +3VSB | ✅ | VCCB pin correctly connected to +3VSB (3.3V supply) with proper decoupling. | | 12 | OE | PMC_PLTRST_R_V1P8 | ✅ | OE pin correctly connected to PMC_PLTRST_R_V1P8 platform reset signal. | </details> <details> <summary>U40 - PCA9306DCUT ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%253A%252F%252Fwww.ti.com%252Flit%252Fgpn%252Fpca9306) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/PCA9306DCUT) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | GND pin correctly connected to ground plane. | | 2 | VREF1 | +V1P8S | ✅ | VREF1 pin correctly connected to +V1P8S (1.8V supply) with proper decoupling capacitor C376. | | 3 | SCL1 | I2C5_SCL | ✅ | SCL1 pin correctly connected to I2C5_SCL with 10K pullup resistor R267 to VREF1. | | 4 | SDA1 | I2C5_SDA | ✅ | SDA1 pin correctly connected to I2C5_SDA with 10K pullup resistor R266 to VREF1. | | 5 | SDA2 | GPIO_I2C_SDA | ✅ | SDA2 pin connected to GPIO_I2C_SDA going to external connector JP1. Pullup resistors are likely on the external board. | | 6 | SCL2 | GPIO_I2C_SCL | ✅ | SCL2 pin connected to GPIO_I2C_SCL going to external connector JP1. Pullup resistors are likely on the external board. | | 7 | VREF2 | $20N1576 | ✅ | VREF2 pin is correctly connected to EN pin and pulled up to +3VSB through R812 (200K ohm). However, the datasheet-recommended 100pF filter capacitor on VREF2 is missing. | | 8 | EN | $20N1576 | ✅ | EN pin correctly shorted to VREF2 and pulled up to +3VSB through R812 (200K) for always-enabled operation. | </details> <details> <summary>R812 - 110-0001951 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001951) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N1576 | ✅ | Connected to VREF2/EN net ($20N1576) of U40. | | 2 | 2 | +3VSB | ✅ | Connected to +3VSB supply rail, providing pullup for VREF2/EN through 200K resistance. | </details> <details> <summary>U3 - W25Q64BVSSIG ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/653/W25Q64BV.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/W25Q64BVSSIG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | CS# | SPI_CS0 | ✅ | CS# (Chip Select) is correctly connected to SPI_CS0 with a 10K pull-up resistor R163 to +V_SPI, and routed through level translator U18 to the SOC. | | 2 | SO/IO1 | SPI_MISO | ✅ | SO/IO1 (Data Output) is correctly connected to SPI_MISO and routed through level translator U18 to the SOC for SPI read operations. | | 3 | WP#/IO2 | SPI_WP | ✅ | WP#/IO2 (Write Protect) is correctly pulled high with 10K resistor R164 to +V_SPI, disabling hardware write protection. It is not connected through the level translator, which is acceptable for standard SPI mode where software-only write protection is used. | | 4 | GND | GND | ✅ | GND is correctly connected to the ground net. | | 5 | SI/IO0 | SPI_MOSI | ✅ | SI/IO0 (Data Input) is correctly connected to SPI_MOSI and routed through level translator U18 to the SOC for SPI write operations. | | 6 | SCK | SPI_CLK | ✅ | SCK (Serial Clock) is correctly connected to SPI_CLK and routed through level translator U18 to the SOC. | | 7 | HOLD#/IO3 | SPI_HOLD | ✅ | HOLD#/IO3 is correctly pulled high with 10K resistor R165 to +V_SPI, disabling the hold function. It is not connected through the level translator, which is acceptable for standard SPI mode where the hold function is not used. | | 8 | VCC | +V_SPI | ✅ | VCC is correctly connected to +V_SPI, which is derived from +3VSB through 0-ohm resistor R152 and Schottky diode D8. The resulting voltage (approximately 2.9-3.0V after diode drop) is within the datasheet specification of 2.7-3.6V. | </details> <details> <summary>R164 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V_SPI | ✅ | 10K pull-up resistor correctly pulls WP# (SPI_WP) high to +V_SPI, disabling hardware write protection for standard SPI operation. | | 2 | 2 | SPI_WP | ✅ | 10K pull-up resistor correctly pulls WP# (SPI_WP) high to +V_SPI, disabling hardware write protection for standard SPI operation. | </details> <details> <summary>R163 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V_SPI | ✅ | 10K pull-up resistor correctly pulls CS# (SPI_CS0) high to +V_SPI, meeting the datasheet requirement for CS# to track VCC at power-up. | | 2 | 2 | SPI_CS0 | ✅ | 10K pull-up resistor correctly pulls CS# (SPI_CS0) high to +V_SPI, meeting the datasheet requirement for CS# to track VCC at power-up. | </details> <details> <summary>R165 - 10K0 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V_SPI | ✅ | 10K pull-up resistor correctly pulls HOLD# (SPI_HOLD) high to +V_SPI, disabling the hold function for standard SPI operation. | | 2 | 2 | SPI_HOLD | ✅ | 10K pull-up resistor correctly pulls HOLD# (SPI_HOLD) high to +V_SPI, disabling the hold function for standard SPI operation. | </details> <details> <summary>R152 - 110-0002124 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002124) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $20N2079 | ✅ | Connected to intermediate net $20N2079, which connects to D8 pin A2 (anode 2 of OR-ing diode). Part of the voltage selection scheme for SPI flash operating voltage. | | 2 | 2 | +3VSB | ✅ | Connected to +3VSB (3.3V standby power supply). Provides the 3.3V source for SPI flash operation when R152 is populated. | </details> <details> <summary>R147 - 110-0001859 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001859) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A | ✅ | Connected to +V1P8A (1.8V power rail). Provides the pull-up voltage source for U18 OE pin. | | 2 | 2 | DDP_IO3L | ✅ | Connected to net DDP_IO3L, which connects to U18 pin 12 (OE) and J1 pin 8. Pulls up the output enable pin of voltage translator U18 to enable it during normal operation. | </details> <details> <summary>D8 - BAT754C ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAT754C) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A1 | A1 | DDP_VCC | ✅ | Connected to DDP_VCC from the external programmer connector. Forms one input of an OR-ing diode configuration to power +V_SPI. | | A2 | A2 | $20N2079 | ✅ | Connected to board supply (+3VSB) through jumper R152 for 3.3V operation. Forms the second input of an OR-ing diode configuration to power +V_SPI when the programmer is not connected. | | C | C | +V_SPI | ✅ | Connected to +V_SPI output, which powers the SPI flash and voltage translator. Outputs the higher of the two input voltages minus the diode forward voltage drop. | </details> <details> <summary>J1 - HEADER 4x2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0004612) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDP_VCC | ✅ | DDP_VCC provides power input from DediProg programmer to the SPI flash through diode OR circuit with internal supply. This allows the flash to be powered from either the external programmer or the internal +3VSB supply. | | 2 | 2 | GND | ✅ | Ground connection for the DediProg programmer interface. | | 3 | 3 | SPI_CS0 | ✅ | SPI_CS0 provides chip select signal to the SPI flash. Connected to U3 CS# pin and level translator U18 B4 output, with 10K pull-up to +V_SPI. | | 4 | 4 | SPI_CLK | ✅ | SPI_CLK provides clock signal to the SPI flash. Connected to U3 SCK pin and level translator U18 B2 output. | | 5 | 5 | SPI_MISO | ✅ | SPI_MISO provides data output from the SPI flash. Connected to U3 SO/IO1 pin and level translator U18 B3 output. | | 6 | 6 | SPI_MOSI | ✅ | SPI_MOSI provides data input to the SPI flash. Connected to U3 SI/IO0 pin and level translator U18 B1 output. | | 7 | 7 | | ✅ | No connection on pin 7. This is acceptable as the SPI flash WP# and HOLD# pins are pulled high through resistors and do not require programmer control. | | 8 | 8 | DDP_IO3L | ✅ | DDP_IO3L controls the level translator output enable. Connected to U18 OE pin with 100K pull-up to +V1P8A, allowing the DediProg programmer to disable the SOC interface when programming. | </details> <details> <summary>JP1 - HEADER 4x2 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0005019) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Ground pins for the header, providing a solid ground reference for connected devices. | | 2 | 2 | GND | ✅ | Ground pins for the header, providing a solid ground reference for connected devices. | | 3 | 3 | +PS_5VSB | ✅ | Provides +PS_5VSB (5V standby power) to the header for powering external devices. | | 4 | 4 | +3VSB | ✅ | Provides +3VSB (3.3V standby power) to the header for powering external devices. | | 5 | 5 | SIO_SPI_CS1 | ✅ | SPI chip select signal (CS1) at 3.3V level, translated from SOC_SIO_SPI_CS1 via U14. | | 6 | 6 | UART1_TXD | ✅ | UART1 transmit signal at 3.3V level, translated from SIO_UART1_TXD via U15. | | 7 | 7 | SIO_SPI_MISO | ✅ | SPI MISO signal at 3.3V level, translated from SOC_SIO_SPI_MISO via U14. | | 8 | 8 | UART1_RXD | ✅ | UART1 receive signal at 3.3V level, translated from SIO_UART1_RXD via U15. | | 9 | 9 | SIO_SPI_MOSI | ✅ | SPI MOSI signal at 3.3V level, translated from SOC_SIO_SPI_MOSI via U14. | | 10 | 10 | UART1_CTSB | ✅ | UART1 clear-to-send signal (active low) at 3.3V level, translated from SIO_UART1_CTSB via U15. | | 11 | 11 | SIO_SPI_CLK | ✅ | SPI clock signal at 3.3V level, translated from SOC_SIO_SPI_CLK via U14. | | 12 | 12 | UART1_RTSB | ✅ | UART1 request-to-send signal (active low) at 3.3V level, translated from SIO_UART1_RTSB via U15. | | 13 | 13 | GPIO_I2C_SCL | ✅ | I2C clock signal at 3.3V level, translated from I2C5_SCL via U40 (PCA9306DCUT I2C level translator). | | 14 | 14 | I2SCLK_GPIO | ✅ | I2S clock signal at 3.3V level, translated from I2S_CLK_R via U16. | | 15 | 15 | GPIO_I2C_SDA | ✅ | I2C data signal at 3.3V level, translated from I2C5_SDA via U40 (PCA9306DCUT I2C level translator). | | 16 | 16 | I2SFRM_GPIO | ✅ | I2S frame signal at 3.3V level, translated from I2S_FRM_R via U16. | | 17 | 17 | UART2_TXD | ✅ | UART2 transmit signal at 3.3V level, translated from SIO_UART2_TXD via U7. | | 18 | 18 | I2SDO_GPIO | ✅ | I2S data output signal at 3.3V level, translated from I2S_DATOUT_R via U16. | | 19 | 19 | UART2_RXD | ✅ | UART2 receive signal at 3.3V level, translated from SIO_UART2_RXD via U7. | | 20 | 20 | I2SDI_GPIO | ✅ | I2S data input signal at 3.3V level, translated from I2S_DATIN_R via U16. | | 21 | 21 | GPIO_S5_0 | ✅ | GPIO S5_0 signal at 3.3V level, translated from SOC_GPIO_S5_0 via U10. | | 22 | 22 | PWM0 | ✅ | PWM0 signal at 3.3V level, translated from SOC_PWM0 via U17. | | 23 | 23 | GPIO_S5_1 | ✅ | GPIO S5_1 signal at 3.3V level, translated from SOC_GPIO_S5_1 via U10. | | 24 | 24 | PWM1 | ✅ | PWM1 signal at 3.3V level, translated from SOC_PWM1 via U17. | | 25 | 25 | GPIO_S5_2 | ✅ | GPIO S5_2 signal at 3.3V level, translated from SOC_GPIO_S5_2 via U10. | | 26 | 26 | I2SMCLK_GPIO | ✅ | I2S master clock signal at 3.3V level, translated from I2S_MCLK via U17. | </details> <details> <summary>R129 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_FRM_R | ✅ | 0-ohm series resistor connecting I2S frame sync signal from level translator U16 (pin A3) to LPE interface. This provides a series connection point for the I2S_FRM signal at 1.8V. | | 2 | 2 | LPE_I2S_FRM | ✅ | 0-ohm series resistor connecting I2S frame sync signal from level translator U16 (pin A3) to LPE interface. This provides a series connection point for the I2S_FRM signal at 1.8V. | </details> <details> <summary>R128 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_DATIN_R | ✅ | 0-ohm series resistor connecting I2S data input signal from level translator U16 (pin A1) to LPE interface. This provides a series connection point for the I2S_DATIN signal at 1.8V. | | 2 | 2 | LPE_I2S_DATIN | ✅ | 0-ohm series resistor connecting I2S data input signal from level translator U16 (pin A1) to LPE interface. This provides a series connection point for the I2S_DATIN signal at 1.8V. | </details> <details> <summary>R130 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_DATOUT_R | ✅ | 0-ohm series resistor connecting I2S data output signal from level translator U16 (pin A2) to LPE interface. This provides a series connection point for the I2S_DATOUT signal at 1.8V. | | 2 | 2 | LPE_I2S_DATOUT | ✅ | 0-ohm series resistor connecting I2S data output signal from level translator U16 (pin A2) to LPE interface. This provides a series connection point for the I2S_DATOUT signal at 1.8V. | </details> <details> <summary>R127 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | I2S_CLK_R | ✅ | 0-ohm series resistor connecting I2S clock signal from level translator U16 (pin A4) to LPE interface. This provides a series connection point for the I2S_CLK signal at 1.8V. | | 2 | 2 | LPE_I2S_CLK | ✅ | 0-ohm series resistor connecting I2S clock signal from level translator U16 (pin A4) to LPE interface. This provides a series connection point for the I2S_CLK signal at 1.8V. | </details> <details> <summary>Q105 - FDN327N ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/fdn327n-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/FDN327N) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | GPIO_LED_CONTROL | ❌ | <details><summary>Drain is connected to GPIO_LED_CONTROL net along with LED D2 anode and resistor R746, creating a parallel (shunt switch) configuration. The standard series topology should be used instead, with the drain connecting to D2 cathode.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="50.34,36.84,57.84,44.34" aspect-ratio="1.29" } <ul><li>Pin D is connected to net GPIO_LED_CONTROL (from schematic)</li><li>GPIO_LED_CONTROL net connects to R746 pin 2 (470Ω from +VCC), D2 anode, and C149 pin 1 (2.2µF to GND) (from schematic)</li><li>Pin D is the Drain terminal according to the FDN327N datasheet (from datasheet <a href="https://www.onsemi.com/pdf/datasheet/fdn327n-d.pdf#page=1">FDN327N</a>, page 1)</li><li>The current configuration places D2 and Q105 in parallel between GPIO_LED_CONTROL and GND, creating a shunt switch topology where the MOSFET bypasses the LED (reasoning)</li><li>In the shunt switch topology, when Q105 is ON (gate high), current flows from +VCC through R746 and Q105 to GND, pulling GPIO_LED_CONTROL low and turning off D2, but wasting approximately VCC/470Ω (7-11mA depending on VCC voltage) of continuous current (reasoning)</li><li>When Q105 is OFF (gate low), GPIO_LED_CONTROL is pulled high through R746, forward-biasing D2 and turning the LED on, creating inverted control logic (GPIO high = LED off) (reasoning)</li><li>The standard low-side N-channel MOSFET LED driver topology requires the LED in series with the MOSFET: VCC → R746 → D2 anode → D2 cathode → Q105 drain → Q105 source → GND (reasoning)</li><li>The series topology provides non-inverted logic (GPIO high = LED on), eliminates power waste when the LED is off, and is the standard approach used in 99% of GPIO-controlled LED circuits (reasoning)</li><li>While the shunt switch topology is functional, it wastes significant power (7-11mA continuously when LED is off) and has no apparent advantage over the standard series topology for a system status indicator (reasoning)</li><li>The text note 'SYSTEM POWER LED - GPIO CONTROLLED' confirms this is intended as a GPIO-controlled system status indicator, which would typically use the standard series topology (from schematic)</li><li>The drain should connect to D2 cathode (not to GPIO_LED_CONTROL with R746 and D2 anode) to implement the standard, efficient series topology (reasoning)</li></ul></details> | | G | GATE | GPIO_D2_LED_CTRL | ✅ | Gate is connected to GPIO_D2_LED_CTRL control signal with a 10kΩ pulldown resistor (R706) to ensure the MOSFET stays off when not actively driven. | | S | SOURCE | GND | ✅ | Source is correctly connected to GND, providing the return path for the MOSFET in this shunt switch configuration. | </details> <details> <summary>D2 - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GPIO_LED_CONTROL | ✅ | Anode is correctly connected to current limiting resistor R746 via the GPIO_LED_CONTROL net. However, Q105 drain is also on this net, creating an incorrect parallel configuration instead of the intended series topology. | | C | CATHODE | GND | ✅ | Cathode is connected to GND, which is incorrect for a series LED-MOSFET topology. The cathode should connect to Q105 drain instead to form the proper series path. | </details> <details> <summary>J5 - 258-0002513 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0002513) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Header pin 1 connects to FP_PWRBTN, providing an external connection point for a front panel power button. The signal is pulled up to +PS_5VSB and protected by TVS diode D9. | | 2 | 2 | GND | ✅ | Header pin 2 connects to GND, providing the ground reference for an external front panel power button. When a button connected to J5 is pressed, it pulls pin 1 (FP_PWRBTN) to ground. | </details> <details> <summary>D9 - D5V0L1B2LP-7B ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.diodes.com/assets/Datasheets/D5V0L1B2LP.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/D5V0L1B2LP-7B) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | N | N | GND | ✅ | TVS diode D9 provides bidirectional ESD protection for the FP_PWRBTN signal. Pin P connects to FP_PWRBTN and pin N connects to GND, protecting against ESD events on the external front panel connection. | | P | P | FP_PWRBTN | ✅ | TVS diode D9 provides bidirectional ESD protection for the FP_PWRBTN signal. Pin P connects to FP_PWRBTN and pin N connects to GND, protecting against ESD events on the external front panel connection. | </details> <details> <summary>SW1 - 3770-0026 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3770-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | FP_PWRBTN | ✅ | Switch pin 1 connects to FP_PWRBTN signal, which is pulled up to +PS_5VSB through R149 and protected by TVS diode D9. When the switch is pressed, this pin is shorted to pin 2 (GND), creating an active-low power button signal. | | 2 | 2 | GND | ✅ | Switch pin 2 connects to GND. When the switch is pressed, it shorts pin 1 to pin 2, pulling FP_PWRBTN low to signal a power button press. | | 3 | GND1 | GND_EARTH | ✅ | Switch pins 3 and 4 (GND1 and GND2) connect to GND_EARTH, providing chassis ground connection for EMI shielding. GND_EARTH is isolated from GND by DNI resistor R145. | | 4 | GND2 | GND_EARTH | ✅ | Switch pins 3 and 4 (GND1 and GND2) connect to GND_EARTH, providing chassis ground connection for EMI shielding. GND_EARTH is isolated from GND by DNI resistor R145. | </details> <details> <summary>D1 - 4560-0045 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4560-0045) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | +PS_5VSB | ✅ | Anode is correctly connected to +PS_5VSB (5V standby supply). This LED serves as an adaptor power indicator. | | C | CATHODE | PWR_LEDR | ✅ | Cathode is correctly connected through current limiting resistor R148 (470Ω) to ground. The circuit provides approximately 3-4mA LED current. | </details> <details> <summary>U13 - REG_LDO_BUCK_24V ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.monolithicpower.com/en/documentview/productdocument/index/version/2/document_type/Datasheet/lang/en/sku/NB670/document_id/6379) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NB670) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VIN | PS5VSB_VIN | ✅ | VIN pin correctly connected to PS5VSB_VIN with appropriate input decoupling capacitors (88.1µF total) and ferrite bead filtering from +PS_5VSB. | | 2 | PGND | GND | ✅ | PGND pin correctly connected to GND for power ground return. | | 3 | N/C | | ✅ | N/C pin correctly left unconnected per datasheet. | | 4 | PG | +PS_3VSB_PG | ✅ | PG pin correctly connected as open-drain output with 100kΩ pull-up resistor R119 to PS3_VCC, and connected to power sequencing diode D6. | | 5 | CLK | $22N1411 | ✅ | CLK pin correctly connected to charge pump circuit using diode arrays Q2 and Q9 with capacitors C72 and C283 to generate higher voltage for gate drive. | | 6 | LDO | PS3_LDO | ✅ | LDO pin correctly connected with 10µF decoupling capacitor C95, exceeding the minimum 4.7µF requirement. | | 7 | VOUT | +PS_3VSB | ✅ | VOUT pin correctly connected to +PS_3VSB output through inductor L3, with multiple 22µF output capacitors (110µF total) for filtering. | | 8 | SW1 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to switching node PS3VSB_PHASE, which connects to inductor L3 and bootstrap circuit. However, bootstrap circuit includes unusual 4.7Ω series resistor R291 not shown in datasheet typical application. | | 9 | SW2 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to switching node PS3VSB_PHASE, which connects to inductor L3 and bootstrap circuit. However, bootstrap circuit includes unusual 4.7Ω series resistor R291 not shown in datasheet typical application. | | 15 | SW3 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to switching node PS3VSB_PHASE, which connects to inductor L3 and bootstrap circuit. However, bootstrap circuit includes unusual 4.7Ω series resistor R291 not shown in datasheet typical application. | | 16 | SW4 | PS3VSB_PHASE | ✅ | SW pins correctly connected together to switching node PS3VSB_PHASE, which connects to inductor L3 and bootstrap circuit. However, bootstrap circuit includes unusual 4.7Ω series resistor R291 not shown in datasheet typical application. | | 10 | BST | PS3_BST | ✅ | BST pin connected to bootstrap circuit through 4.7Ω resistor R291, with C306 (0.1µF) as bootstrap capacitor. Series resistor is unusual but may be intentional for current limiting or damping. | | 11 | VCC | PS3_VCC | ✅ | VCC pin correctly connected with 1µF decoupling capacitor C97 meeting minimum requirement, and 100kΩ pull-up resistor R119 for power-good signal. | | 12 | ENLDO | | ✅ | ENLDO pin correctly left open to enable LDO per datasheet recommendation. | | 13 | EN | PS3_EN | ✅ | EN pin connected with 499kΩ pull-up resistor R109 to PS5VSB_VIN for enable control. Datasheet-recommended 10nF noise filtering capacitor C85 is marked DNI, which may be acceptable if noise is not an issue. | | 14 | AGND | GND | ✅ | AGND pin correctly connected to GND for analog ground reference. | </details> <details> <summary>C306 - 0.1uF 10% 25V 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3VSB_PHASE | ✅ | C306 is the 0.1µF bootstrap capacitor connected between switching node PS3VSB_PHASE and intermediate node (through R291 to BST). Capacitor value matches datasheet recommendation, but series resistor R291 is unusual. | | 2 | 2 | $22N1498 | ✅ | C306 is the 0.1µF bootstrap capacitor connected between switching node PS3VSB_PHASE and intermediate node (through R291 to BST). Capacitor value matches datasheet recommendation, but series resistor R291 is unusual. | </details> <details> <summary>L3 - IND_2.2uH_20%_10A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/125-0004501) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3VSB_PHASE | ✅ | Inductor pin 1 correctly connected to switching node PS3VSB_PHASE from U13 SW pins. | | 2 | 2 | +PS_3VSB | ✅ | Inductor pin 2 correctly connected to output +PS_3VSB with appropriate output capacitors. | </details> <details> <summary>R291 - 4.7 ohm 1% 1/4W 0603 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | PS3_BST | ✅ | R291 is a 4.7Ω resistor in series with bootstrap circuit between BST pin and bootstrap capacitor C306. This configuration is unusual and not shown in NB670 datasheet typical application, but may be intentional for current limiting or damping. | | 2 | 2 | $22N1498 | ✅ | R291 is a 4.7Ω resistor in series with bootstrap circuit between BST pin and bootstrap capacitor C306. This configuration is unusual and not shown in NB670 datasheet typical application, but may be intentional for current limiting or damping. | </details> <details> <summary>U35 - PWR_CTRL_EMB_PROC ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NCT3012S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | DeepS5_Sel | S5_SEL | ✅ | DeepS5_Sel configuration pin connected to S5_SEL net with 2.2K pull-up to +PS_5VSB. This appears to configure the Deep S5 mode behavior. | | 2 | VSB | +PS_5VSB | ✅ | VSB power supply pin correctly connected to +PS_5VSB rail with adequate decoupling capacitors nearby. | | 3 | PS_IN# | PB_RES | ✅ | PS_IN# power button input connected to PB_RES net through 33 ohm series resistor R308, which connects to front panel power button. | | 4 | SLP_S5# | SLP_S4_L | ✅ | SLP_S5# pin is connected to SLP_S4_L net. There is a naming mismatch between S5 (pin name) and S4 (net name), which represents different ACPI sleep states. However, this may be intentional if the system design treats S4 and S5 identically or uses a simplified power state model common in embedded systems. | | 5 | SDA | DDR_SMB_DATA | ✅ | SDA pin correctly connected to DDR_SMB_DATA for I2C/SMBus communication with DDR memory. | | 6 | SCLK | DDR_SMB_CLK | ✅ | SCLK pin correctly connected to DDR_SMB_CLK for I2C/SMBus clock communication with DDR memory. | | 7 | PS_OUT# | PS_OUT_L | ✅ | PS_OUT# power state output connected to PS_OUT_L net. The pull-up resistor R289 is marked DNI, which may be acceptable if the receiving circuit has its own pull-up or if the pin has an internal pull-up. | | 8 | SYS5VSB_OFF | 5VSB_CTRL | ✅ | SYS5VSB_OFF output controls 5VSB system power through 5VSB_CTRL net. Connected with appropriate pull-up and drives FET gate for EuP control. Text notes indicate Low=EuP Disable, High=EuP Enable. | | 9 | GND | GND | ✅ | GND pin correctly connected to system ground. | </details> <details> <summary>Q104 - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +3VSB | ✅ | Source pins correctly connected to +3VSB output rail. These pins carry the output current when the MOSFET is conducting. | | 2 | S2 | +3VSB | ✅ | Source pins correctly connected to +3VSB output rail. These pins carry the output current when the MOSFET is conducting. | | 3 | S3 | +3VSB | ✅ | Source pins correctly connected to +3VSB output rail. These pins carry the output current when the MOSFET is conducting. | | 4 | G | +3VSB_EN | ✅ | Gate pin correctly connected to +3VSB_EN control signal with appropriate drive voltage of +10V to turn on the MOSFET. | | 5 | D1 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting. | | 6 | D2 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting. | | 7 | D3 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting. | | 8 | D4 | +PS_3VSB | ✅ | Drain pins correctly connected to +PS_3VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting. | </details> <details> <summary>Q103 - SISA18ADN-T1-GE3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.vishay.com/docs/63259/sisa18adn.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/SISA18ADN-T1-GE3) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. These pins carry the output current when the MOSFET is conducting. | | 2 | S2 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. These pins carry the output current when the MOSFET is conducting. | | 3 | S3 | +5VSB | ✅ | Source pins correctly connected to +5VSB output rail. These pins carry the output current when the MOSFET is conducting. | | 4 | G | 5VSB_LSENB | ✅ | Gate pin correctly connected to 5VSB_LSENB control signal with appropriate drive voltage of +10V to turn on the MOSFET. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB input rail. These pins receive input power and are at higher potential than source when MOSFET is conducting. | </details> <details> <summary>D13 - 4.3V Zener ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4620-0026) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | A | ANODE | GND | ✅ | Anode correctly connected to GND. For a Zener diode used in voltage clamping, the anode should be at the lower potential. | | C | CATHODE | $22N2300 | ✅ | Cathode correctly connected to $22N2300, which is the gate control voltage for Q106. The Zener clamps this voltage at 4.3V above GND. | </details> <details> <summary>Q106 - BSS84 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/bss84-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BSS84) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | D | DC_GATE_ENB | ✅ | Drain correctly connected to DC_GATE_ENB to control the gate of U36. When Q106 turns on at overvoltage conditions, it pulls DC_GATE_ENB high to turn off U36. | | G | G | $22N2300 | ✅ | Gate correctly connected to $22N2300, which is clamped at 4.3V by Zener diode D13. The gate voltage relative to source determines when Q106 turns on to activate overvoltage protection. | | S | S | $22N1502 | ✅ | Source correctly connected to $22N1502, which is the same net as U36 source. This provides the reference voltage for Q106's gate-source voltage calculation. | </details> <details> <summary>U36 - MOSFET_30V_15A_8-SOIC ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.umw-ic.com/static/pdf/b379d167af492bcd72ba51c793d83236.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/IRF9321) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | S1 | $22N1502 | ✅ | Source pins correctly connected to $22N1502, which connects through ferrite beads to DC_IN_1 (5V input). This is the correct configuration for a P-channel high-side switch. | | 2 | S2 | $22N1502 | ✅ | Source pins correctly connected to $22N1502, which connects through ferrite beads to DC_IN_1 (5V input). This is the correct configuration for a P-channel high-side switch. | | 3 | S3 | $22N1502 | ✅ | Source pins correctly connected to $22N1502, which connects through ferrite beads to DC_IN_1 (5V input). This is the correct configuration for a P-channel high-side switch. | | 4 | G | DC_GATE_ENB | ✅ | Gate pin correctly connected to DC_GATE_ENB, which is controlled by the overvoltage protection circuit consisting of Q106, D13, R855, C75, and R309. | | 5 | D1 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB output. This is the correct configuration for a P-channel high-side switch, where the drain connects to the load/output. | | 6 | D2 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB output. This is the correct configuration for a P-channel high-side switch, where the drain connects to the load/output. | | 7 | D3 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB output. This is the correct configuration for a P-channel high-side switch, where the drain connects to the load/output. | | 8 | D4 | +PS_5VSB | ✅ | Drain pins correctly connected to +PS_5VSB output. This is the correct configuration for a P-channel high-side switch, where the drain connects to the load/output. | </details> <details> <summary>Q13 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +5VSB | ✅ | Drain is connected to +5VSB input rail. This is correct for a high-side switch configuration. | | G | GATE | SYS_EN | ✅ | Gate is connected to SYS_EN control signal. The control circuit provides +10V when enabled and GND when disabled, giving sufficient VGS for proper operation. | | S | SOURCE | +VCC | ✅ | Source is connected to +VCC output rail. This is correct for a high-side switch, with current flowing from drain to source when enabled. | </details> <details> <summary>Q6 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/RXR035N03) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB | ✅ | Drain is connected to +3VSB input rail. This is correct for a high-side switch configuration. | | G | GATE | SYS_EN | ✅ | Gate is connected to SYS_EN control signal. The control circuit provides +10V when enabled and GND when disabled, giving sufficient VGS for proper operation. | | S | SOURCE | +VCC3 | ✅ | Source is connected to +VCC3 output rail. This is correct for a high-side switch, with current flowing from drain to source when enabled. | </details> <details> <summary>Q11 - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +3VSB_EN | ✅ | Drain pin correctly connected to +3VSB_EN, which drives the gate of Q104 (P-channel power MOSFET). Drain current is limited to approximately 100µA steady-state through R322 (100K to +10V), well within the 300mA rating. | | G | GATE | +3VSB_EN_L | ✅ | Gate pin correctly connected to +3VSB_EN_L, which is driven by Q4 collector and pulled up through R321 (1K to +PS_5VSB). Gate voltage swings between ~0V (Q4 on) and ~5V (Q4 off), providing adequate drive for the MOSFET. | | S | SOURCE | GND | ✅ | Source pin correctly connected to GND, providing proper reference for N-channel MOSFET operation in low-side switch configuration. | </details> <details> <summary>Q4 - XSTR_NPN_40V_200mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.dropbox.com/scl/fi/429d9yd6zt2n9eblnwt96/MMBT3904S2S1AM.pdf?rlkey=tnw47yrl6i6taycl1avowx97n&st=g80omaqf&dl=1) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/MMBT3904) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | B | BASE | S5_ENBL | ✅ | Base pin correctly connected to S5_ENBL signal, which is pulled up to +V1P8A through R133 (10K) and can be pulled low by Q10. Provides adequate base current for switching operation. | | C | COLLECTOR | +3VSB_EN_L | ✅ | Collector pin correctly connected to +3VSB_EN_L, which drives the gate of Q11 through R321 (1K pull-up to +PS_5VSB). Collector current is limited to approximately 5mA, well within the 200mA maximum rating. | | E | EMITTER | GND | ✅ | Emitter pin correctly connected to GND, providing proper reference for NPN transistor operation in common-emitter configuration. | </details> <details> <summary>Q10 - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | S5_ENBL | ✅ | Drain connected to S5_ENBL, which drives the base of NPN transistor Q4. This pin acts as a low-side switch to control Q4's base voltage. | | G | GATE | 5VSB_CTRL | ✅ | Gate connected to 5VSB_CTRL, which is the EuP control signal from U35. This provides direct gate drive control for the MOSFET. | | S | SOURCE | GND | ✅ | Source correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch. | </details> <details> <summary>Q14 - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | 5VSB_LSENB | ✅ | Drain connected to 5VSB_LSENB, which drives the gate of power MOSFET Q103. This pin acts as a low-side switch to control Q103's gate voltage. | | G | GATE | 5VSB_GATE | ✅ | Gate connected to 5VSB_GATE, which is driven from 5VSB_CTRL through R323 (10K). This provides adequate gate drive voltage to control the MOSFET. | | S | SOURCE | GND | ✅ | Source correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch. | </details> <details> <summary>Q7 - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN_GATE | ✅ | Drain connected to SYS_EN_GATE, which drives the gate of Q12. This pin acts as a low-side switch to control Q12's gate voltage. | | G | GATE | SLP_S3_L | ✅ | Gate connected to SLP_S3_L, which is an active-low control signal. This provides gate drive control for the MOSFET. | | S | SOURCE | GND | ✅ | Source correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch. | </details> <details> <summary>Q12 - FET_NCH_60V_300mA_SOT23 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/download/data-sheet/pdf/2n7002k-fsc-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2N7002K) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | SYS_EN | ✅ | Drain connected to SYS_EN, which drives the gates of power MOSFETs Q13 and Q6. This pin acts as a low-side switch to control the power MOSFETs. | | G | GATE | SYS_EN_GATE | ✅ | Gate connected to SYS_EN_GATE, which is controlled by Q7 and pulled up through R142. This provides gate drive control for the MOSFET. | | S | SOURCE | GND | ✅ | Source correctly connected to GND, which is the proper configuration for an N-channel MOSFET used as a low-side switch. | </details> <details> <summary>Q2 - DIODE_ARRAY_75V_0.3A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | +PS_5VSB | ✅ | Anode 1 connected to +PS_5VSB (5V standby rail). This diode provides negative clamping for the CLK signal through C72, limiting negative excursions to approximately 4.3V. | | 2 | A2 | $22N1417 | ✅ | Anode 2 connected to floating node $22N1417, which is also connected to Q9 pin 1 and filtered to GND through C71. This diode appears to be reverse-biased in normal operation and its specific function is unclear. | | 3 | C | $22N1419 | ✅ | Common cathode connected to $22N1419, which is AC-coupled to the CLK pin of U13 through C72. This is the clamped node for negative voltage excursions. | </details> <details> <summary>Q9 - DIODE_ARRAY_75V_0.3A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAV99-7-F-S-X) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | A1 | $22N1417 | ✅ | Anode 1 connected to floating node $22N1417, which is also connected to Q2 pin 2 and filtered to GND through C71. This diode appears to be reverse-biased in normal operation and its specific function is unclear. | | 2 | A2 | +10V | ✅ | Anode 2 connected to +10V rail. This diode provides a secondary negative clamp at approximately 9.3V, which is higher than the Q2 clamp and may serve as backup protection. | | 3 | C | $22N1467 | ✅ | Common cathode connected to $22N1467, which is AC-coupled to the CLK pin of U13 through C283. This provides a secondary clamped path for negative voltage excursions. | </details> <details> <summary>D6 - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB_PG | ✅ | Pin 1 connects to +PS_3VSB_PG, the power good output from the 3.3VSB regulator U13. The exact diode function cannot be verified without the datasheet. | | 2 | 2 | +3VSB_EN | ✅ | Pin 2 connects to +3VSB_EN, which drives the gate of P-channel MOSFET Q104 and is pulled up to +10V through R322. The exact diode function cannot be verified without the datasheet. | | 3 | 3 | PMC_RSMRST | ✅ | Pin 3 connects to PMC_RSMRST, likely a reset signal to the platform management controller. The exact diode function cannot be verified without the datasheet. | </details> <details> <summary>FB11 - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_5VSB | ✅ | Pin 1 connects to +PS_5VSB, paralleled with FB1 pin 1 for increased current capacity. | | 2 | 2 | PS5VSB_VIN | ✅ | Pin 2 connects to PS5VSB_VIN, paralleled with FB1 pin 2 for increased current capacity. | </details> <details> <summary>L13 - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $22N1502 | ✅ | Pin 1 connects to $22N1502, paralleled with L12 pin 1 for increased current capacity. | | 2 | 2 | DC_IN_1 | ✅ | Pin 2 connects to DC_IN_1, paralleled with L12 pin 2 for increased current capacity. | </details> <details> <summary>L12 - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $22N1502 | ✅ | Pin 1 connects to $22N1502, the source pins of P-channel MOSFET U36 and the filtered DC input node. | | 2 | 2 | DC_IN_1 | ✅ | Pin 2 connects to DC_IN_1, the 5V DC input from power jack J9. | </details> <details> <summary>FB1 - FERRITE_120OHM_3A_0603 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_5VSB | ✅ | Pin 1 connects to +PS_5VSB, the filtered 5V standby rail output from power switching MOSFETs Q103 and U36. | | 2 | 2 | PS5VSB_VIN | ✅ | Pin 2 connects to PS5VSB_VIN, the input to the 3.3V buck regulator U13 and associated input capacitors. | </details> <details> <summary>J9 - JACK_PWR_2.1MM_RAPC712 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/414/RAPC712_cd.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/RAPC712) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DC_IN_1 | ✅ | Center pin connected to DC_IN_1 net, serving as the positive 5V DC power input. The connection includes appropriate filtering capacitors, ferrite beads, and inrush current limiting, feeding into an overvoltage protection circuit. | | 2 | 2 | GND | ✅ | Sleeve/barrel contact correctly connected to the GND net, serving as the ground return for the DC power input. | | 3 | 3 | GND | ✅ | Switch contact connected to GND net. The switch functionality is not utilized in this design, which is acceptable when plug detection is not required. | </details> <details> <summary>U25 - NCP81109GMNTXG ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT pin connected to VR_HOT_L net for thermal alert output. | | 2 | SDIO | $23N2429 | ✅ | SDIO pin connected to SVID data interface through 16.9Ω series resistor R80. | | 3 | ALERT | $23N2431 | ✅ | ALERT pin connected to SVID alert interface through 0Ω resistor R62. | | 4 | SCLK | $23N2430 | ✅ | SCLK pin connected to SVID clock interface through 20.0Ω series resistor R81. | | 5 | GND | AGND-VCORE | ✅ | GND pin connected to AGND-VCORE analog ground net, which connects to main GND through 0Ω resistor R37. | | 6 | VR_RDY | $23N3753 | ✅ | VR_RDY pin connected to power good output VCORE_PG through 0Ω resistor R79. | | 7 | VIN1 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors. | | 11 | VIN2 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors. | | 12 | VIN3 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors. | | 13 | VIN4 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors. | | 14 | VIN5 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors. | | 15 | VIN6 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors. | | 16 | VIN7 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors. | | 17 | VIN8 | +5VSB_SW | ✅ | VIN1-VIN8 pins all connected to +5VSB_SW input supply with proper decoupling capacitors. | | 8 | BST | $23N3711 | ✅ | BST pin connected to bootstrap circuit with R154 (2.20Ω) and C50 (0.22µF) to SW1 node. | | 9 | GH | | ✅ | GH pin has no net connection shown. Without datasheet, cannot verify if this is correct for an integrated power stage or if this is an error. | | 10 | SW1 | $23N3731 | ✅ | SW1 pin connected to bootstrap circuit return path through C50. | | 18 | SW2 | VCORE-SW | ✅ | SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE. | | 25 | SW3 | VCORE-SW | ✅ | SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE. | | 26 | SW4 | VCORE-SW | ✅ | SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE. | | 27 | SW5 | VCORE-SW | ✅ | SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE. | | 28 | SW6 | VCORE-SW | ✅ | SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE. | | 29 | SW7 | VCORE-SW | ✅ | SW2-SW7 pins all connected to VCORE-SW switch node output, which feeds through L18 inductor to +VCORE. | | 19 | PGND1 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 20 | PGND2 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 21 | PGND3 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 22 | PGND4 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 23 | PGND5 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 24 | PGND6 | GND | ✅ | PGND1-PGND6 pins all connected to main GND for power ground return. | | 30 | GL | | ✅ | GL pin has no net connection shown. Without datasheet, cannot verify if this is correct for an integrated power stage or if this is an error. | | 31 | VBOOT | $23N3477 | ✅ | VBOOT pin connected through 88.7kΩ resistor to ground for bootstrap voltage monitoring. Text note indicates VBOOT = 1.1V. | | 32 | GND1 | AGND-VCORE | ✅ | GND1 pin connected to AGND-VCORE analog ground net. | | 33 | VCCP | $23N3625 | ✅ | VCCP pin connected to charge pump supply through 1.00Ω resistor from +5VSB with 4.7µF decoupling. | | 34 | TSENSE | $23N3665 | ✅ | TSENSE pin connected to temperature sensing network with 100kΩ thermistor TH2 and 14.0kΩ resistor forming voltage divider. | | 35 | IMAX | $23N3681 | ✅ | IMAX pin connected through 44.2kΩ resistor to ground to set maximum current limit. Text note indicates IMAX = 14A. | | 36 | IOUT | $23N3683 | ✅ | IOUT pin connected through 16.5kΩ resistor and 470pF capacitor to ground for output current reporting. | | 37 | ILIM | VCORE-ILIM | ✅ | ILIM pin connected to current sense compensation network through 15.0kΩ resistor. | | 38 | CSCOMP | VCORE-CSCOMP | ✅ | CSCOMP pin connected to current sense compensation network with capacitors, resistors, and thermistor TH1 for temperature compensation. | | 39 | CSSUM | VCORE-CSSUM | ✅ | CSSUM pin connected to current sense sum network with DCR sensing through shorts SP3 and SP4 measuring inductor voltage drop. | | 40 | CSREF | VCORE-CSREF | ✅ | CSREF pin connected to current sense reference through 10.0Ω resistor with DCR sensing from output through short SP4. | | 41 | FREQ | $23N2930 | ✅ | FREQ pin connected through 18.7kΩ resistor to ground to set switching frequency. Text note indicates FSW = 650kHz. | | 42 | COMP | VCORE-COMP | ✅ | COMP pin connected to voltage loop compensation network with capacitors C35 and C37. | | 43 | FB | VCORE-FB | ✅ | FB pin connected to feedback network with resistor divider and compensation components. | | 44 | DIFFOUT | VCORE-DIFFOUT | ✅ | DIFFOUT pin connected to differential amplifier output network with resistors R89 and R90. | | 45 | VSN | VR-VCORE-VSN | ✅ | VSN pin connected to negative remote sense input through 10.0Ω resistor for differential voltage sensing at the load. | | 46 | VSP | VR-VCORE-VSP | ✅ | VSP pin connected to positive remote sense input through 100Ω resistor for differential voltage sensing at the load. | | 47 | VCC | $23N3860 | ✅ | VCC pin connected to internal supply through 2.20Ω resistor from +5VSB with 1.0µF decoupling. | | 48 | EN | $23N5607 | ✅ | EN pin connected to enable control with pull-up through 0Ω resistor from +VCC and 10kΩ pull-down. | | 49 | GND_PAD | AGND-VCORE | ✅ | GND_PAD connected to AGND-VCORE analog ground net for thermal and electrical grounding. | | 50 | VIN_PAD | +5VSB_SW | ✅ | VIN_PAD connected to +5VSB_SW input supply, paralleling the VIN1-VIN8 pins. | | 51 | SW_PAD | VCORE-SW | ✅ | SW_PAD connected to VCORE-SW switch node output, paralleling the SW2-SW7 pins. | </details> <details> <summary>L8 - 3120-0183 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3120-0183) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 connects to the +5VSB input supply rail. This is the correct connection for the input side of the input filter inductor. | | 2 | 2 | +5VSB_SW | ✅ | Pin 2 connects to the +5VSB_SW filtered supply rail that powers the U25 controller VIN pins. This is the correct connection for the output side of the input filter inductor. | </details> <details> <summary>L18 - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-SW | ✅ | Pin 1 connects to the VCORE-SW switching node from the U25 multiphase buck controller. This is the correct connection for the input side of the output filter inductor. | | 2 | 2 | +VCORE | ✅ | Pin 2 connects to the +VCORE output rail with multiple output capacitors and load connections. This is the correct connection for the output side of the filter inductor. | </details> <details> <summary>TH2 - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | Connected to net $23N3662, which receives the TSENSE signal from U25 through R78. This thermistor provides temperature sensing for the voltage regulator. | | 2 | 2 | GND | ✅ | Connected to GND, providing the ground reference for the temperature sensing voltage divider. | </details> <details> <summary>R78 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3665 | ✅ | Connected to net $23N3665, which connects to U25 pin 34 (TSENSE). This 0-ohm jumper allows the TSENSE signal to reach the thermistor network. | | 2 | 2 | $23N3662 | ✅ | Connected to net $23N3662, which is the junction of TH2 and R131. This completes the connection from TSENSE to the temperature sensing network. | </details> <details> <summary>R131 - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3662 | ✅ | Connected to net $23N3662, forming a parallel combination with TH2 for temperature sensing. The 14K value sets the temperature sensing characteristics. | | 2 | 2 | GND | ✅ | Connected to GND, completing the temperature sensing voltage divider to ground. | </details> <details> <summary>TH1 - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP net, which is the current sense compensation pin of U25. This thermistor provides temperature compensation for the current sensing loop. | | 2 | 2 | $23N3115 | ✅ | Connected to net $23N3115, which is the junction between R96 and R106 in the current sensing compensation network. | </details> <details> <summary>D4 - BAT54A-S ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAT54A-S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Cathode 1 of dual Schottky diode, connected to VCORE_PG net. This pin receives the VCORE power good signal and forms part of a wired-AND power good monitoring circuit. | | 2 | 2 | VGFX_PG | ✅ | Cathode 2 of dual Schottky diode, connected to VGFX_PG net. This pin receives the graphics voltage regulator power good signal and forms the other input of the wired-AND power good monitoring circuit. | | 3 | 3 | VCORE_GFX_PG | ✅ | Common anode of dual Schottky diode, connected to VCORE_GFX_PG net. This pin outputs the combined power good signal that is high only when both VCORE_PG and VGFX_PG are high. | </details> <details> <summary>R94 - 110-0001923 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_GFX_PG | ✅ | Connected to VCORE_GFX_PG combined power good signal. Functions as part of pull-up network. | | 2 | 2 | +VCC3 | ✅ | Connected to +VCC3 supply rail. Provides pull-up voltage for the combined power good signal. | </details> <details> <summary>R79 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE_PG | ✅ | Connected to VCORE_PG power good signal. Functions as 0-ohm jumper to route VR_RDY signal. | | 2 | 2 | $23N3753 | ✅ | Connected to U25 pin 6 (VR_RDY) through internal net $23N3753. Routes voltage regulator ready signal to VCORE_PG. | </details> <details> <summary>R167 - 1120-0052 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Connected to +VCC3 supply rail. Provides pull-up voltage for VCORE_PG signal. | | 2 | 2 | VCORE_PG | ✅ | Connected to VCORE_PG power good signal. Provides pull-up for the VR_RDY output from U25. | </details> <details> <summary>R62 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U25 ALERT pin. | | 2 | 2 | $23N2431 | ✅ | Zero-ohm jumper on SVID alert line providing direct connection between external SVID_ALERT-R signal and U25 ALERT pin. | </details> <details> <summary>R80 - 1120-0329 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA-R | ✅ | Series resistor on SVID data line between external SVID_DATA-R signal and U25 SDIO pin. Provides signal integrity and protection for the serial data line. | | 2 | 2 | $23N2429 | ✅ | Series resistor on SVID data line between external SVID_DATA-R signal and U25 SDIO pin. Provides signal integrity and protection for the serial data line. | </details> <details> <summary>R87 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_CLK-R. Not installed, indicating pull-ups are provided elsewhere in the system. | | 2 | 2 | SVID_CLK-R | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_CLK-R. Not installed, indicating pull-ups are provided elsewhere in the system. | </details> <details> <summary>R86 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_ALERT-R. Not installed, indicating pull-ups are provided elsewhere in the system. | | 2 | 2 | SVID_ALERT-R | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_ALERT-R. Not installed, indicating pull-ups are provided elsewhere in the system. | </details> <details> <summary>R85 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_DATA-R. Not installed, indicating pull-ups are provided elsewhere in the system. | | 2 | 2 | SVID_DATA-R | ✅ | DNI pull-up resistor that would connect +V1P0S to SVID_DATA-R. Not installed, indicating pull-ups are provided elsewhere in the system. | </details> <details> <summary>R81 - 1120-0099 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_CLK-R | ✅ | Series resistor on SVID clock line between external SVID_CLK-R signal and U25 SCLK pin. Provides signal integrity and protection for the serial clock line. | | 2 | 2 | $23N2430 | ✅ | Series resistor on SVID clock line between external SVID_CLK-R signal and U25 SCLK pin. Provides signal integrity and protection for the serial clock line. | </details> <details> <summary>C87 - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VCORE | ✅ | Positive terminal of the 330µF tantalum capacitor connected to the +VCORE output rail. This provides bulk energy storage and filtering for the VCORE regulator output. | | 2 | N | GND | ✅ | Negative terminal of the tantalum capacitor connected to ground reference. This completes the output filtering capacitor connection with correct polarity. | </details> <details> <summary>C35 - 2220-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | Connected to VCORE-COMP net which connects to the COMP pin (pin 42) of U25. This is the error amplifier output. | | 2 | 2 | VCORE-FB | ✅ | Connected to VCORE-FB net. Forms direct high-frequency path between COMP and FB for stability. | </details> <details> <summary>C37 - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-COMP | ✅ | Connected to VCORE-COMP net which connects to the COMP pin (pin 42) of U25. | | 2 | 2 | $23N2824 | ✅ | Connected to intermediate node $23N2824 which connects to R88. Forms RC network with R88 to create compensation zero. | </details> <details> <summary>R90 - 1121-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2818 | ✅ | Connected to intermediate node $23N2818 which connects to C36. Forms an RC network for additional phase boost. | | 2 | 2 | VCORE-DIFFOUT | ✅ | Connected to VCORE-DIFFOUT net which connects to the DIFFOUT pin (pin 44) of U25. | </details> <details> <summary>R88 - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2824 | ✅ | Connected to intermediate node $23N2824 which connects to C37. Forms part of the Type III compensation network creating a zero with C37. | | 2 | 2 | VCORE-FB | ✅ | Connected to VCORE-FB net which connects to the FB pin (pin 43) of U25. This is the feedback node of the compensation network. | </details> <details> <summary>R89 - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | Connected to VCORE-FB net, the feedback node. Provides DC feedback path from FB to DIFFOUT. | | 2 | 2 | VCORE-DIFFOUT | ✅ | Connected to VCORE-DIFFOUT net which connects to the DIFFOUT pin (pin 44) of U25. Completes the feedback path. | </details> <details> <summary>C36 - 2220-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-FB | ✅ | Connected to VCORE-FB net which connects to the FB pin (pin 43) of U25. | | 2 | 2 | $23N2818 | ✅ | Connected to intermediate node $23N2818 which connects to R90. Forms RC network with R90 for additional phase boost. | </details> <details> <summary>R146 - 1120-0338 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3683 | ✅ | Connected to U25 pin 36 (IOUT) to set the output current monitoring scale. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE to provide the pulldown reference for IOUT. | </details> <details> <summary>R106 - 1120-0037 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3115 | ✅ | Connected to intermediate node $23N3115, continuing the divider from R96. | | 2 | 2 | VCORE-CSSUM | ✅ | Connected to VCORE-CSSUM to complete the resistor divider network. | </details> <details> <summary>R96 - 1120-0282 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP as part of a resistor divider network with R106. | | 2 | 2 | $23N3115 | ✅ | Connected to intermediate node $23N3115, which continues to R106 and has TH1 in parallel for temperature compensation. | </details> <details> <summary>C45 - 2220-0035 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSREF | ✅ | Connected to VCORE-CSREF to filter the current sense reference voltage. | | 2 | 2 | GND | ✅ | Connected to GND to complete the filtering capacitor. | </details> <details> <summary>R95 - 1120-0029 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-ILIM | ✅ | Connected to VCORE-ILIM (U25 pin 37) to set the current limit threshold. | | 2 | 2 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP to complete the current limit setting network. | </details> <details> <summary>R107 - 1130-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSSUM | ✅ | Connected to VCORE-CSSUM to provide the current sense signal from the switching node. | | 2 | 2 | $23N3209 | ✅ | Connected to VCORE-SW through PCB bridge short SP3, implementing DCR current sensing from the switching node. | </details> <details> <summary>R108 - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSREF | ✅ | Connected to VCORE-CSREF (U25 pin 40) to provide a reference voltage for current sensing. | | 2 | 2 | $23N3208 | ✅ | Connected to +VCORE through PCB bridge short SP4, providing a reference voltage proportional to the output for adaptive voltage positioning. | </details> <details> <summary>R105 - 1120-0115 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3681 | ✅ | Connected to U25 pin 35 (IMAX) to set the maximum current limit. A nearby text note indicates IMAX should be 14A. | | 2 | 2 | AGND-VCORE | ✅ | Connected to AGND-VCORE to provide the pulldown reference for IMAX. | </details> <details> <summary>C40 - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP, in parallel with C39 to provide additional compensation capacitance. | | 2 | 2 | VCORE-CSSUM | ✅ | Connected to VCORE-CSSUM, in parallel with C39 to complete the compensation network. | </details> <details> <summary>C39 - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCORE-CSCOMP | ✅ | Connected to VCORE-CSCOMP for current loop compensation. This capacitor, along with C40, provides compensation between CSCOMP and CSSUM pins of the PWM controller. | | 2 | 2 | VCORE-CSSUM | ✅ | Connected to VCORE-CSSUM to complete the compensation network between CSCOMP and CSSUM. | </details> <details> <summary>R849 - 1121-0001 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ❌ | <details><summary>R849 is a 0 ohm jumper connecting +VCC to the EN pin of U25. With R851 (10K to GND) also populated, this creates a continuous current path from +VCC to GND through R851, drawing approximately 0.33-0.5mA depending on +VCC voltage. This is wasteful and unusual; typically only one of R849 or R851 would be populated.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="33.07,36.25,40.57,43.75" aspect-ratio="1.29" } <ul><li>Pin 1 of R849 is connected to net +VCC (from schematic)</li><li>Pin 2 of R849 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic)</li><li>R849 is a 0 ohm jumper (part number 1121-0001) (from schematic)</li><li>R851 is a 10K resistor connecting the same net $23N5607 to GND (from schematic)</li><li>With R849 as 0 ohm and R851 as 10K both populated, a current path exists from +VCC through R849 to GND through R851 (reasoning)</li><li>The current through this path would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning)</li><li>This continuous current draw is wasteful and serves no functional purpose (reasoning)</li><li>Typical enable circuit design would have either a pull-up (R849) or pull-down (R851) populated, not both (reasoning)</li><li>The 0 ohm jumper R849 would pull the EN pin high to +VCC, enabling the regulator (reasoning)</li><li>If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning)</li><li>If the intent is to disable the regulator by default or allow external control, R849 should be DNI and R851 should be populated (reasoning)</li><li>One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)</li></ul></details> | | 2 | 2 | $23N5607 | ❌ | <details><summary>R849 is a 0 ohm jumper connecting +VCC to the EN pin of U25. With R851 (10K to GND) also populated, this creates a continuous current path from +VCC to GND through R851, drawing approximately 0.33-0.5mA depending on +VCC voltage. This is wasteful and unusual; typically only one of R849 or R851 would be populated.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="33.07,38.02,40.57,45.52" aspect-ratio="1.29" } <ul><li>Pin 1 of R849 is connected to net +VCC (from schematic)</li><li>Pin 2 of R849 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic)</li><li>R849 is a 0 ohm jumper (part number 1121-0001) (from schematic)</li><li>R851 is a 10K resistor connecting the same net $23N5607 to GND (from schematic)</li><li>With R849 as 0 ohm and R851 as 10K both populated, a current path exists from +VCC through R849 to GND through R851 (reasoning)</li><li>The current through this path would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning)</li><li>This continuous current draw is wasteful and serves no functional purpose (reasoning)</li><li>Typical enable circuit design would have either a pull-up (R849) or pull-down (R851) populated, not both (reasoning)</li><li>The 0 ohm jumper R849 would pull the EN pin high to +VCC, enabling the regulator (reasoning)</li><li>If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning)</li><li>If the intent is to disable the regulator by default or allow external control, R849 should be DNI and R851 should be populated (reasoning)</li><li>One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)</li></ul></details> | </details> <details> <summary>R851 - 1120-0011 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N5607 | ❌ | <details><summary>R851 is a 10K pull-down resistor connecting the EN pin of U25 to GND. With R849 (0 ohm to +VCC) also populated, this creates a continuous current path from +VCC to GND, drawing approximately 0.33-0.5mA. This is wasteful and unusual; typically only one of R849 or R851 would be populated.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="33.07,39.78,40.57,47.28" aspect-ratio="1.29" } <ul><li>Pin 1 of R851 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic)</li><li>Pin 2 of R851 is connected to net GND (from schematic)</li><li>R851 is a 10K resistor (part number 1120-0011) (from schematic)</li><li>R849 is a 0 ohm jumper connecting +VCC to the same net $23N5607 (from schematic)</li><li>With both R849 (0 ohm) and R851 (10K) populated, a current path exists from +VCC to GND (reasoning)</li><li>The current through R851 would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning)</li><li>This continuous current draw is wasteful and serves no functional purpose (reasoning)</li><li>A pull-down resistor on an enable pin is typically used when the regulator should be disabled by default or when external control is desired (reasoning)</li><li>With R849 (0 ohm) populated, the EN pin is strongly pulled high to +VCC, making R851 redundant except for creating unwanted current draw (reasoning)</li><li>If the intent is to disable the regulator by default, R851 should be populated and R849 should be DNI (reasoning)</li><li>If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning)</li><li>One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)</li></ul></details> | | 2 | 2 | GND | ❌ | <details><summary>R851 is a 10K pull-down resistor connecting the EN pin of U25 to GND. With R849 (0 ohm to +VCC) also populated, this creates a continuous current path from +VCC to GND, drawing approximately 0.33-0.5mA. This is wasteful and unusual; typically only one of R849 or R851 would be populated.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="33.07,41.55,40.57,49.05" aspect-ratio="1.29" } <ul><li>Pin 1 of R851 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic)</li><li>Pin 2 of R851 is connected to net GND (from schematic)</li><li>R851 is a 10K resistor (part number 1120-0011) (from schematic)</li><li>R849 is a 0 ohm jumper connecting +VCC to the same net $23N5607 (from schematic)</li><li>With both R849 (0 ohm) and R851 (10K) populated, a current path exists from +VCC to GND (reasoning)</li><li>The current through R851 would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning)</li><li>This continuous current draw is wasteful and serves no functional purpose (reasoning)</li><li>A pull-down resistor on an enable pin is typically used when the regulator should be disabled by default or when external control is desired (reasoning)</li><li>With R849 (0 ohm) populated, the EN pin is strongly pulled high to +VCC, making R851 redundant except for creating unwanted current draw (reasoning)</li><li>If the intent is to disable the regulator by default, R851 should be populated and R849 should be DNI (reasoning)</li><li>If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning)</li><li>One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)</li></ul></details> | </details> <details> <summary>R154 - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3711 | ✅ | Connected to BST pin of U25 (NCP81109GMNTXG controller). This is the bootstrap pin connection for the high-side gate driver. | | 2 | 2 | $23N3733 | ✅ | Connected to bootstrap capacitor C50. This forms the series R-C bootstrap network between BST and SW1 pins. | </details> <details> <summary>C50 - 2222-0008 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N3733 | ✅ | Connected to R154 pin 2, forming the bootstrap capacitor connection between the damping resistor and the switch node. | | 2 | 2 | $23N3731 | ✅ | Connected to SW1 pin of U25. This completes the bootstrap circuit by connecting the capacitor to the switch node. | </details> <details> <summary>R93 - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $23N2930 | ✅ | Pin 1 connects to the FREQ pin (pin 41) of U25 (NCP81109GMNTXG) to set the switching frequency. A nearby text note indicates the target frequency is 650 kHz. | | 2 | 2 | AGND-VCORE | ✅ | Pin 2 connects to AGND-VCORE, the analog ground net for the VCORE regulator section. This is the correct reference for the frequency-setting resistor. | </details> <details> <summary>U26 - NCP81109GMNTXG ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NCP81109GMNTXG) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VRHOT | VR_HOT_L | ✅ | VRHOT pin is connected to VR_HOT_L net, which is a thermal alert output signal. | | 2 | SDIO | $24N3490 | ✅ | SDIO pin is connected to SVID data line through R193 (16.9Ω) series resistor with pull-up to +V1P0S through R195 (69.8Ω). | | 3 | ALERT | $24N3492 | ✅ | ALERT pin is connected to SVID alert line through R67 (0Ω) jumper with pull-up to +V1P0S through R196 (69.8Ω, DNI). | | 4 | SCLK | $24N3491 | ✅ | SCLK pin is connected to SVID clock line through R194 (20.0Ω) series resistor with pull-up to +V1P0S through R197 (69.8Ω). | | 5 | GND | AGND-VGFX | ✅ | GND pin is connected to AGND-VGFX analog ground net, which connects to main GND through R66 (0Ω) jumper. | | 6 | VR_RDY | $24N3598 | ✅ | VR_RDY pin is connected to power good output VGFX_PG through R184 (0Ω) jumper, with pull-up R230 (1.91kΩ) to +VCC3 and decoupling C60 (0.1µF). | | 7 | VIN1 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 11 | VIN2 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 12 | VIN3 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 13 | VIN4 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 14 | VIN5 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 15 | VIN6 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 16 | VIN7 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 17 | VIN8 | +5VSB_SW | ✅ | VIN1-VIN8 pins are all connected to +5VSB_SW input supply with multiple decoupling capacitors (C54-C59). | | 8 | BST | $24N3593 | ✅ | BST pin is connected to bootstrap circuit with R228 (2.20Ω) and C186 (0.22µF) to SW1 for high-side gate driver supply. | | 9 | GH | | ✅ | GH pin has no net connection shown in the schematic, which is expected for an integrated solution where MOSFETs are internal. | | 10 | SW1 | $24N3595 | ✅ | SW1 is connected to the bootstrap capacitor return path ($24N3595) but is isolated from the main switch node VGFX-SW. This configuration appears intentional as phase 1 gate drives (GH pin 9, GL pin 30) are not connected, suggesting phase 1 is not used as an active switching phase. | | 18 | SW2 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 25 | SW3 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 26 | SW4 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 27 | SW5 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 28 | SW6 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 29 | SW7 | VGFX-SW | ✅ | SW2-SW7 pins are all connected to VGFX-SW switch node, which feeds output inductor L4 (470nH) to generate +VGFX output. | | 19 | PGND1 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 20 | PGND2 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 21 | PGND3 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 22 | PGND4 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 23 | PGND5 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 24 | PGND6 | GND | ✅ | PGND1-PGND6 pins are all connected to GND, providing power ground return paths for the integrated MOSFETs. | | 30 | GL | | ✅ | GL pin has no net connection shown in the schematic, which is expected for an integrated solution where MOSFETs are internal. | | 31 | VBOOT | $24N3564 | ✅ | VBOOT pin is connected to bootstrap voltage sense with R170 (100kΩ) pull-down to AGND-VGFX. | | 32 | GND1 | AGND-VGFX | ✅ | GND1 pin is connected to AGND-VGFX analog ground net. | | 33 | VCCP | $24N3578 | ✅ | VCCP pin is connected to internal LDO/charge pump supply with R846 (1Ω) from +5VSB and C185 (4.7µF) decoupling. | | 34 | TSENSE | $24N3584 | ✅ | TSENSE pin is connected to temperature sense network with TH4 (100kΩ@25C thermistor) and R226 (14.0kΩ) forming a divider to GND, with C168 (0.1µF) filtering. | | 35 | IMAX | $24N3588 | ✅ | IMAX pin is connected to R207 (44.2kΩ) to AGND-VGFX, setting the maximum current limit. A text note indicates IMAX = 14A. | | 36 | IOUT | $24N3589 | ✅ | IOUT pin is connected to output current reporting network with R227 (16.5kΩ) and C184 (470pF) to AGND-VGFX. | | 37 | ILIM | VGFX-ILIM | ✅ | ILIM pin is connected to current limit threshold network with R204 (15.0kΩ) to VGFX-CSCOMP. | | 38 | CSCOMP | VGFX-CSCOMP | ✅ | CSCOMP pin is connected to current sense compensation network with R204, R205, TH3, C113, and C166 for current loop stability and thermal compensation. | | 39 | CSSUM | VGFX-CSSUM | ✅ | CSSUM pin is connected to current sense sum network with R224, R223, C113, and C166 for multiphase current sensing. | | 40 | CSREF | VGFX-CSREF | ✅ | CSREF pin is connected to current sense reference with R225 (10.0Ω) to output voltage through SP1, and C167 (1000pF) to GND. | | 41 | FREQ | $24N3542 | ✅ | FREQ pin is connected to R203 (18.7kΩ) to AGND-VGFX, setting the switching frequency. A text note indicates FSW = 650kHz. | | 42 | COMP | VGFX-COMP | ✅ | COMP pin is connected to voltage loop compensation network with C62 (47pF) to FB and C64 (2200pF) to feedback divider. | | 43 | FB | VGFX-FB | ✅ | FB pin is connected to feedback network with R198 (3.01kΩ) divider, R199 (1.00kΩ) to DIFFOUT, and compensation capacitors C62 and C63. | | 44 | DIFFOUT | VGFX-DIFFOUT | ✅ | DIFFOUT pin is connected to differential amplifier output network with R199 (1.00kΩ) to FB and R200 (47Ω) to compensation. | | 45 | VSN | VR-VGFX-VSN | ✅ | VSN pin is connected to negative remote sense input with R169 (10.0Ω) from ground reference point. | | 46 | VSP | VR-VGFX-VSP | ✅ | VSP pin is connected to positive remote sense input with R202 (100Ω) from +VGFX and R68 (0Ω) from VCCGT_SENSE. | | 47 | VCC | $24N3610 | ✅ | VCC pin is connected to supply input with R229 (2.20Ω) from +5VSB and C53 (1.0µF) decoupling to AGND-VGFX. | | 48 | EN | $24N6011 | ✅ | EN pin is connected to enable input with R850 (0Ω) pull-up to +VCC, R852 (10.0kΩ) pull-down to GND, and C434 (0.1µF) decoupling. | | 49 | GND_PAD | AGND-VGFX | ✅ | GND_PAD is connected to AGND-VGFX analog ground net for thermal and electrical grounding. | | 50 | VIN_PAD | +5VSB_SW | ✅ | VIN_PAD is connected to +5VSB_SW input supply for additional current handling capability. | | 51 | SW_PAD | VGFX-SW | ✅ | SW_PAD is connected to VGFX-SW switch node for additional current handling capability. | </details> <details> <summary>SP1 - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Pin 1 connects to +VGFX, the regulated output voltage of the buck converter. This connection is part of the DCR (DC Resistance) current sensing network. | | 2 | 2 | $24N3559 | ✅ | Pin 2 connects to $24N3559, which connects through R225 (10Ω) to VGFX-CSREF (pin 40 of U26). This forms the reference path for DCR current sensing. | </details> <details> <summary>SP2 - 999-0000005 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/999-0000005) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Pin 1 connects to VGFX-SW, the switching node of the buck converter. This connection is part of the DCR current sensing network. | | 2 | 2 | $24N3558 | ✅ | Pin 2 connects to $24N3558, which connects through R224 (100kΩ) to VGFX-CSSUM (pin 39 of U26). This forms the sum path for DCR current sensing. | </details> <details> <summary>L4 - 3120-0266 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3120-0266) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to VGFX-SW switching node. This is the correct connection for a buck converter output inductor. | | 2 | 2 | +VGFX | ✅ | Connected to +VGFX output rail. This is the correct connection for a buck converter output inductor. However, there is a potential concern regarding current rating. | </details> <details> <summary>R198 - 1120-0032 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3524 | ✅ | Connected to internal compensation network node $24N3524, which connects to C64 pin 2. Forms part of the voltage loop compensation network. | | 2 | 2 | VGFX-FB | ✅ | Connected to VGFX-FB net, which is the feedback pin (pin 43) of voltage regulator controller U26. | </details> <details> <summary>R199 - 1120-0010 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-FB | ✅ | Connected to VGFX-FB net, the feedback pin of U26. Forms part of the differential amplifier network. | | 2 | 2 | VGFX-DIFFOUT | ✅ | Connected to VGFX-DIFFOUT net, the differential output pin (pin 44) of U26. | </details> <details> <summary>R200 - 1121-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3522 | ✅ | Connected to internal compensation network node $24N3522, which connects to C63 pin 2. | | 2 | 2 | VGFX-DIFFOUT | ✅ | Connected to VGFX-DIFFOUT net, the differential output pin of U26. | </details> <details> <summary>C62 - 2220-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-COMP | ✅ | Connected to VGFX-COMP net, the compensation pin (pin 42) of U26. | | 2 | 2 | VGFX-FB | ✅ | Connected to VGFX-FB net, the feedback pin of U26. Provides direct AC coupling between COMP and FB. | </details> <details> <summary>C63 - 2220-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-FB | ✅ | Connected to VGFX-FB net, the feedback pin of U26. | | 2 | 2 | $24N3522 | ✅ | Connected to internal compensation network node $24N3522, which connects to R200 pin 1. | </details> <details> <summary>C64 - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-COMP | ✅ | Connected to VGFX-COMP net, the compensation pin of U26. | | 2 | 2 | $24N3524 | ✅ | Connected to internal compensation network node $24N3524, which connects to R198 pin 1. | </details> <details> <summary>R224 - 1130-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM pin of the controller U26 for current sensing. | | 2 | 2 | $24N3558 | ✅ | Connected through net $24N3558 and short SP2 to the switching node VGFX-SW for DCR current sensing. | </details> <details> <summary>C167 - 2220-0035 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSREF | ✅ | Connected to VGFX-CSREF for filtering the current sense reference. | | 2 | 2 | GND | ✅ | Connected to GND to provide AC filtering for the CSREF pin. | </details> <details> <summary>R205 - 1120-0282 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP for current sense compensation. | | 2 | 2 | $24N3557 | ✅ | Connected to intermediate node $24N3557, forming a parallel path with thermistor TH3 for temperature compensation. | </details> <details> <summary>R223 - 1120-0037 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3557 | ✅ | Connected to the intermediate node $24N3557 which links to the CSCOMP compensation network. | | 2 | 2 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM to provide feedback from the current sense sum to the compensation network. | </details> <details> <summary>TH3 - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP for current sensing temperature compensation. This thermistor provides temperature-dependent resistance to compensate the current sensing circuit of the voltage regulator. | | 2 | 2 | $24N3557 | ✅ | Connected to internal node $24N3557 which forms part of the resistor divider network with R205 and R223. This creates a temperature-dependent voltage for current sensing compensation. | </details> <details> <summary>R225 - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSREF | ✅ | Connected to VGFX-CSREF pin of the controller for current sense reference. | | 2 | 2 | $24N3559 | ✅ | Connected through net $24N3559 and short SP1 to the output voltage +VGFX, providing a reference for DCR current sensing. | </details> <details> <summary>R204 - 1120-0029 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-ILIM | ✅ | Connected to VGFX-ILIM pin of the controller for current limit setting. | | 2 | 2 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP to link the current limit setting to the compensation network. | </details> <details> <summary>C166 - 2221-0002 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP for current loop compensation. | | 2 | 2 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM, forming part of the current loop compensation network in parallel with C113. | </details> <details> <summary>C113 - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-CSCOMP | ✅ | Connected to VGFX-CSCOMP for current loop compensation. | | 2 | 2 | VGFX-CSSUM | ✅ | Connected to VGFX-CSSUM, forming part of the current loop compensation network in parallel with C166. | </details> <details> <summary>TH4 - 3880-0004 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3880-0004) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | Connected to internal node $24N3583 which forms a voltage divider with R226 (14K) to ground. This provides temperature-dependent voltage to the TSENSE pin of U26 through R178. | | 2 | 2 | GND | ✅ | Connected to GND to complete the voltage divider circuit with R226. This is the standard configuration for a thermistor-based temperature sensing circuit. | </details> <details> <summary>R226 - 1120-0055 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3583 | ✅ | Connected to $24N3583 which connects to TH4 pin 1, forming the upper part of the voltage divider. This creates a temperature-dependent voltage with the thermistor. | | 2 | 2 | GND | ✅ | Connected to GND to complete the voltage divider with TH4. This is the standard lower resistor in a thermistor voltage divider configuration. | </details> <details> <summary>C168 - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3584 | ✅ | Connected to $24N3584 which connects to U26 pin 34 (TSENSE). This capacitor provides filtering for the temperature sensing input to reduce noise. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX (analog ground) to provide a clean ground reference for filtering. This ensures the filter capacitor has a low-noise ground connection. | </details> <details> <summary>R178 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3584 | ✅ | Connected to $24N3584 which connects to U26 pin 34 (TSENSE) and C168 for filtering. This side of the jumper connects the temperature sensing network to the controller. | | 2 | 2 | $24N3583 | ✅ | Connected to $24N3583 which connects to the TH4/R226 voltage divider. This side of the jumper connects to the thermistor temperature sensing network. | </details> <details> <summary>R67 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_ALERT-R | ✅ | Connected to SVID_ALERT-R net. R196 (69.8Ω pull-up to +V1P0S) is DNI, so no pull-up is present on this board. | | 2 | 2 | $24N3492 | ✅ | Connected to U26 pin 3 (ALERT) through net $24N3492. This 0Ω jumper provides a direct connection to the ALERT pin. | </details> <details> <summary>R195 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Connected to +V1P0S supply. This provides the pull-up voltage for the SVID data line. | | 2 | 2 | SVID_DATA-R | ✅ | Connected to SVID_DATA-R net, providing pull-up for the SVID data line. The 69.8Ω value provides a strong pull-up for fast signal transitions. | </details> <details> <summary>R196 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | This component is marked DNI (Do Not Install). If installed, it would provide a 69.8Ω pull-up from +V1P0S to SVID_ALERT-R. | | 2 | 2 | SVID_ALERT-R | ✅ | This component is marked DNI (Do Not Install). If installed, it would provide a 69.8Ω pull-up from +V1P0S to SVID_ALERT-R. | </details> <details> <summary>C432 - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Connected to +V1P0S supply. This capacitor provides decoupling for the 1.0V supply used for SVID pull-ups. | | 2 | 2 | GND | ✅ | Connected to GND. This completes the decoupling capacitor for the +V1P0S supply. | </details> <details> <summary>R197 - 1120-0330 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0S | ✅ | Connected to +V1P0S supply. This provides the pull-up voltage for the SVID clock line. | | 2 | 2 | SVID_CLK-R | ✅ | Connected to SVID_CLK-R net, providing pull-up for the SVID clock line. The 69.8Ω value provides a strong pull-up for fast signal transitions. | </details> <details> <summary>R194 - 1120-0099 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_CLK-R | ✅ | Connected to SVID_CLK-R net, which is pulled up to +V1P0S through R197. This pin forms one end of the series resistor for the SVID clock line. | | 2 | 2 | $24N3491 | ✅ | Connected to U26 pin 4 (SCLK) through net $24N3491. This pin forms the controller side of the series resistor for the SVID clock line. | </details> <details> <summary>R193 - 1120-0329 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | SVID_DATA-R | ✅ | Connected to SVID_DATA-R net, which is pulled up to +V1P0S through R195. This pin forms one end of the series resistor for the SVID data line. | | 2 | 2 | $24N3490 | ✅ | Connected to U26 pin 2 (SDIO) through net $24N3490. This pin forms the controller side of the series resistor for the SVID data line. | </details> <details> <summary>R202 - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VGFX | ✅ | Connects to +VGFX output rail for local voltage sensing. This provides a 100Ω series resistance path from the output to the VSP sense input. | | 2 | 2 | VR-VGFX-VSP | ✅ | Connects to VR-VGFX-VSP net, which is the positive sense input (VSP, pin 46) of U26. This forms part of the differential remote sense circuit. | </details> <details> <summary>R68 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCCGT_SENSE | ✅ | Connects to VCCGT_SENSE net for remote voltage sensing. This 0Ω jumper enables remote sensing when the VCCGT_SENSE signal is connected. | | 2 | 2 | VR-VGFX-VSP | ✅ | Connects to VR-VGFX-VSP net, which is the positive sense input (VSP, pin 46) of U26. This provides the remote sensing path. | </details> <details> <summary>R201 - 1120-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connects to GND. This resistor is in parallel with R69 (0Ω), which effectively bypasses R201's 100Ω resistance. | | 2 | 2 | $24N3528 | ✅ | Connects to $24N3528, an internal node in the VSN sensing network. This node connects to VSN through R169 and to GND through parallel R201 and R69. | </details> <details> <summary>R69 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Connects to GND. This 0Ω jumper is in parallel with R201 (100Ω), providing a low-impedance ground path. | | 2 | 2 | $24N3528 | ✅ | Connects to $24N3528, an internal node in the VSN sensing network. This provides the low-impedance ground connection for the VSN path. | </details> <details> <summary>R169 - 1120-0022 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3528 | ✅ | Connects to $24N3528, an internal node that connects to GND through parallel R201 and R69. This forms the ground reference side of the differential sense circuit. | | 2 | 2 | VR-VGFX-VSN | ✅ | Connects to VR-VGFX-VSN, which is the negative sense input (VSN, pin 45) of U26. This completes the differential sense circuit. | </details> <details> <summary>C61 - 2221-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VR-VGFX-VSP | ✅ | DNI capacitor that would provide differential filtering between VSP and VSN sense inputs. Not installed, likely to avoid phase shift in the feedback loop. | | 2 | 2 | VR-VGFX-VSN | ✅ | DNI capacitor that would provide differential filtering between VSP and VSN sense inputs. Not installed, likely to avoid phase shift in the feedback loop. | </details> <details> <summary>C104 - 2221-0004 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3528 | ✅ | DNI capacitor that would provide filtering on the VSN sense path. Not installed, likely to avoid phase shift in the feedback loop. | | 2 | 2 | VR-VGFX-VSN | ✅ | DNI capacitor that would provide filtering on the VSN sense path. Not installed, likely to avoid phase shift in the feedback loop. | </details> <details> <summary>C434 - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N6011 | ✅ | Connected to enable control net $24N6011 for filtering. | | 2 | 2 | GND | ✅ | Connected to GND to complete the bypass capacitor function. | </details> <details> <summary>R850 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC | ✅ | Connected to +VCC power rail to provide enable control signal. | | 2 | 2 | $24N6011 | ✅ | Connected to enable control net $24N6011 which drives U26 pin 48 (EN). | </details> <details> <summary>R852 - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N6011 | ✅ | Connected to enable control net $24N6011 to provide pull-down function. | | 2 | 2 | GND | ✅ | Connected to GND to complete the pull-down function. | </details> <details> <summary>R230 - 1120-0052 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VCC3 | ✅ | Connected to +VCC3 power rail to provide pull-up voltage source for the power good signal. | | 2 | 2 | VGFX_PG | ✅ | Connected to VGFX_PG net, providing pull-up function for the power good signal. | </details> <details> <summary>C60 - 2222-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX_PG | ✅ | Connected to VGFX_PG net to provide signal filtering and noise suppression. | | 2 | 2 | GND | ✅ | Connected to GND to complete the filtering path for the power good signal. | </details> <details> <summary>R184 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX_PG | ✅ | Connected to VGFX_PG net, which is the conditioned power good signal with pull-up and filtering. | | 2 | 2 | $24N3598 | ✅ | Connected to U26 pin 6 (VR_RDY), the voltage regulator power ready output signal. | </details> <details> <summary>R228 - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3593 | ✅ | Connected to the BST (bootstrap) pin of U26 (NCP81109GMNTXG) via net $24N3593. This resistor provides series damping and current limiting for the bootstrap circuit. | | 2 | 2 | $24N3596 | ✅ | Connected to bootstrap capacitor C186 pin 1 via net $24N3596. This forms the series R-C bootstrap network. However, C186 pin 2 has a connection issue that affects the overall bootstrap circuit functionality. | </details> <details> <summary>C186 - 2222-0008 ❌</summary> DRCY flagged 1 potential issues in this component. ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 2 | 2 | $24N3595 | ❌ | <details><summary>Connected to U26 pin 10 (SW1) via net $24N3595, but should connect to the main switching node VGFX-SW. The bootstrap capacitor must reference the actual switching node where the inductor connects to provide proper gate drive voltage for the high-side MOSFET.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="32.39,42.43,39.89,49.93" aspect-ratio="1.29" } <ul><li>Pin 2 is connected to net $24N3595 (from schematic)</li><li>Net $24N3595 connects only to U26 pin 10 (SW1) (from schematic)</li><li>The main switching node is VGFX-SW, which connects to U26 pins 18, 25, 26, 27, 28, 29 (SW2-SW7) and pin 51 (SW_PAD) (from schematic)</li><li>The output inductor L4 pin 1 connects to VGFX-SW, confirming this is the main switching node (from schematic)</li><li>SW1 is isolated and not connected to VGFX-SW or to any other part of the power stage except the bootstrap capacitor (from schematic)</li><li>This is a multiphase buck converter with only one inductor (L4), and all active switch nodes (SW2-SW7) are paralleled to VGFX-SW (from schematic)</li><li>In a synchronous buck converter, the bootstrap capacitor must be connected between the BST pin and the switching node to provide proper gate drive voltage for the high-side MOSFET (reasoning)</li><li>The switching node is defined as the connection point between the high-side and low-side MOSFETs, which is where the inductor connects in a buck converter (reasoning)</li><li>Since the inductor connects to VGFX-SW and all active switch outputs (SW2-SW7) connect to VGFX-SW, the bootstrap capacitor should be connected between BST and VGFX-SW (reasoning)</li><li>The current configuration with the bootstrap capacitor connected to the isolated SW1 pin will not provide proper bootstrap voltage referenced to the actual switching node (reasoning)</li><li>Pin 2 should be connected to net VGFX-SW instead of net $24N3595 to form a functional bootstrap circuit (reasoning)</li><li>While there is a small possibility that SW1 is intentionally designed as a separate bootstrap reference node in the NCP81109GMNTXG, this would be highly unusual and inconsistent with standard synchronous buck converter design practice (reasoning)</li><li>The 0.22µF capacitance and 16V voltage rating are appropriate for a bootstrap capacitor in a 5V input system (reasoning)</li></ul></details> | | 1 | 1 | $24N3596 | ✅ | Connected to bootstrap resistor R228. This is the charging side of the bootstrap capacitor. | </details> <details> <summary>R229 - 1130-0234 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail. This pin sources power for the VCC bias supply of U26 through the 2.2 ohm current-limiting resistor. | | 2 | 2 | $24N3610 | ✅ | Connected to net $24N3610, which supplies U26 pin 47 (VCC) and is bypassed by C53. This provides the bias supply voltage for the controller IC. | </details> <details> <summary>R846 - 1130-0193 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Connected to +5VSB supply rail. This pin sources power for the VCCP charge pump supply of U26 through the 1 ohm current-limiting resistor. | | 2 | 2 | $24N3578 | ✅ | Connected to net $24N3578, which supplies U26 pin 33 (VCCP) and is bypassed by C185. This provides the charge pump supply voltage for the gate driver. | </details> <details> <summary>C53 - 2222-0014 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3610 | ✅ | Connected to net $24N3610, which is the VCC supply for U26 after current limiting by R229. This pin provides bypass capacitance for the controller bias supply. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX analog ground. This provides the return path for the VCC bypass capacitor, correctly referenced to the analog ground plane. | </details> <details> <summary>C185 - 2232-0016 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3578 | ✅ | Connected to net $24N3578, which is the VCCP charge pump supply for U26 after current limiting by R846. This pin provides bypass capacitance for the charge pump supply. | | 2 | 2 | GND | ✅ | Connected to GND power ground. This provides the return path for the VCCP bypass capacitor, referenced to power ground to keep charge pump switching currents separate from the analog ground. | </details> <details> <summary>R203 - 1120-0351 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3542 | ✅ | Connected to U26 FREQ pin to set switching frequency. Text note indicates target frequency of 650 kHz. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX (analog ground), which is appropriate for a frequency-setting resistor. | </details> <details> <summary>R207 - 1120-0115 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3588 | ✅ | Connected to U26 IMAX pin (pin 35) to set the maximum current limit. A text note near this component indicates IMAX = 14A. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX (analog ground). This provides the ground reference for the IMAX current limit setting. | </details> <details> <summary>C184 - 2220-0025 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3589 | ✅ | Connected to U26 IOUT pin (pin 36) for current monitoring. Forms an RC filter with R227 to filter the current sense output signal. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX (analog ground). This completes the RC filter with R227 for current monitoring. | </details> <details> <summary>R227 - 1120-0338 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3589 | ✅ | Connected to U26 IOUT pin (pin 36) for current monitoring. Forms an RC filter with C184 to filter the current sense output signal. | | 2 | 2 | AGND-VGFX | ✅ | Connected to AGND-VGFX (analog ground). This provides the ground reference for the current monitoring filter. | </details> <details> <summary>R231 - 1141-0026 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VGFX-SW | ✅ | Connected to the switching node VGFX-SW of the DC/DC converter. This is the input of the RC snubber circuit. | | 2 | 2 | $24N3623 | ✅ | Connected to the intermediate node of the RC snubber, which connects to capacitor C187. | </details> <details> <summary>C187 - 2240-0005 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $24N3623 | ✅ | Connected to the intermediate node of the RC snubber, receiving the filtered signal from R231. | | 2 | 2 | GND | ✅ | Connected to ground, completing the RC snubber circuit path. | </details> <details> <summary>R66 - 1121-0001 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | R66 is a 0-ohm jumper connecting the power ground (GND) to the analog ground (AGND-VGFX), implementing a star ground topology for the DC-DC controller U26. | | 2 | 2 | AGND-VGFX | ✅ | R66 is a 0-ohm jumper connecting the power ground (GND) to the analog ground (AGND-VGFX), implementing a star ground topology for the DC-DC controller U26. | </details> <details> <summary>U41 - RT8207 ❌</summary> DRCY flagged 1 potential issues in this component. 📄 [DRCY referred to this Datasheet for this component.](https://www.richtek.com/SaveDownload.aspx?specid=RT8207P) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/RT8207) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 22 | BOOT | $25N771 | ❌ | <details><summary>BOOT pin connected to bootstrap network, but bootstrap capacitor C309 is significantly undersized (0.1uF instead of recommended 1uF) and includes non-standard series resistor R298 (4.7Ω), which may cause insufficient gate drive voltage and slower switching transitions.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="45.80,38.02,53.30,45.52" aspect-ratio="1.29" } <ul><li>Pin 22 (BOOT) is connected to net $25N771 (from schematic)</li><li>Net $25N771 connects through R298 (4.7Ω resistor) to DDR_BST net (from schematic)</li><li>DDR_BST connects to C309 pin 2 (0.1uF capacitor) (from schematic)</li><li>C309 pin 1 connects to DDR_PHASE net (PHASE pin) (from schematic)</li><li>BOOT is the boost flying capacitor connection for VDDQ that supplies high side gate driver instantaneous current (from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=2">RT8207</a>, page 2)</li><li>Datasheet recommends 1uF flying bootstrap capacitor between BOOT and PHASE pins (from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=16">RT8207</a>, page 16)</li><li>Typical application circuits show direct connection of bootstrap capacitor without series resistance (from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=3">RT8207</a>, page 3)</li><li>Actual bootstrap capacitor C309 is 0.1uF, which is 10x smaller than the recommended 1uF (reasoning)</li><li>Undersized bootstrap capacitor may cause insufficient gate drive voltage for high-side MOSFET, especially at high switching frequencies (reasoning)</li><li>Series resistor R298 (4.7Ω) is not shown in datasheet reference designs and will cause voltage drop during gate charging (reasoning)</li><li>The series resistor will slow bootstrap capacitor charging and may affect gate drive performance (reasoning)</li><li>Bootstrap capacitor should be increased to 1uF and series resistor should be removed to match datasheet recommendations (reasoning)</li></ul></details> | | 1 | VTTGND | GND | ✅ | VTTGND pin correctly connected to GND for VTT LDO power ground. | | 2 | VTTSNS | +VDIMM_VTT | ✅ | VTTSNS pin correctly connected to +VDIMM_VTT for remote voltage sensing of VTT output. | | 3 | GND | GND | ✅ | GND pin correctly connected to system ground for analog ground reference. | | 4 | MODE | GND | ✅ | MODE pin connected to GND. Function not documented in available datasheet for 20-pin variant, but connection appears to be a valid mode selection. | | 5 | VTTREF | $25N769 | ✅ | VTTREF pin correctly connected to bypass capacitor C342 (0.22uF) for buffered reference output. | | 6 | DEM | $25N1291 | ✅ | DEM pin connected to pull-up resistor R810 (10K to +5VSB). Function not documented in available 20-pin datasheet, likely controls diode emulation mode. | | 8 | VDDQ | +VDIMM | ✅ | VDDQ pin correctly connected to +VDIMM output rail for reference input and discharge control. | | 9 | FB | $25N987 | ✅ | FB pin correctly connected to resistor divider (R814=8.06K, R815=10K) and compensation capacitor C382 (22pF) to set output voltage to 1.35V for DDR3L. | | 10 | S3 | EN_VTT | ✅ | S3 pin correctly connected to EN_VTT signal through R302 (0 ohm) for VTT output control. | | 11 | S5 | EN_VDDQ | ✅ | S5 pin correctly connected to EN_VDDQ signal through R300 (0 ohm) for overall power state control. | | 12 | TON | $25N1081 | ✅ | TON pin correctly connected to +5VSB through R816, but R816 has incorrect value (464K instead of specified 806K), resulting in switching frequency of approximately 504kHz instead of the intended 285kHz. | | 13 | PGOOD | DRAM_PWROK | ✅ | PGOOD pin correctly connected to DRAM_PWROK signal for power good indication. | | 14 | VDD | $25N1195 | ✅ | VDD pin correctly connected through RC filter (R813=2.2Ω, C380=1uF) from +5VSB for analog supply. | | 15 | VDDP | +5VSB | ✅ | VDDP pin correctly connected directly to +5VSB for gate driver supply. | | 16 | CS | $25N1238 | ✅ | CS pin correctly connected through R817 (3.83K) to VDD for current limit threshold setting. | | 18 | PGND | GND | ✅ | PGND pin correctly connected to GND for power ground of low-side MOSFET. | | 19 | LGATE | $25N901 | ✅ | LGATE pin correctly connected to Q102 pin 8 (Q2G) for low-side MOSFET gate drive. | | 20 | PHASE | DDR_PHASE | ✅ | PHASE pin correctly connected to switching node between MOSFETs and output inductor L11. | | 21 | UGATE | $25N897 | ✅ | UGATE pin correctly connected to Q102 pin 1 (Q1G) for high-side MOSFET gate drive. | | 23 | VLDOIN | +VDIMM | ✅ | VLDOIN pin correctly connected to +VDIMM for VTT LDO power supply and tracking discharge mode. | | 24 | VTT | +VDIMM_VTT | ✅ | VTT pin correctly connected to +VDIMM_VTT output rail for VTT LDO power output. | | 25 | GND_PAD | GND | ✅ | GND_PAD (exposed pad) correctly connected to GND for thermal dissipation and ground reference. | </details> <details> <summary>R816 - 1120-0149 ❌</summary> DRCY flagged 1 potential issues in this component. ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0149) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ❌ | <details><summary>TON timing resistor has incorrect value of 464K; should be 806K per design specification to achieve the intended 285kHz switching frequency. Current value results in approximately 504kHz operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="27.62,35.08,35.12,42.58" aspect-ratio="1.29" } <ul><li>R816 pin 1 is connected to +5VSB net (from schematic)</li><li>R816 pin 2 is connected to net $25N1081 (TON pin of U41) (from schematic)</li><li>R816 value is 464K per component attributes (from schematic)</li><li>Schematic design note specifies 'Rton=806K, F=285KHz' (from schematic)</li><li>On-time formula is tON = 3.85p × RTON × VVDDQ / (VIN - 0.5) (from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=15">RT8207</a>, page 15)</li><li>Switching frequency formula: f = (VIN - 0.5) / (3.85p × VIN × RTON) (from schematic)</li><li>With RTON=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 504kHz (reasoning)</li><li>With RTON=806K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 290kHz, matching the design note (reasoning)</li><li>The resistor value does not match the design specification, indicating an error in component selection (reasoning)</li><li>Higher switching frequency affects inductor selection, core losses, switching losses, and EMI performance (reasoning)</li><li>R816 should be changed from 464K to 806K to achieve the intended 285kHz switching frequency (reasoning)</li></ul></details> | | 2 | 2 | $25N1081 | ❌ | <details><summary>TON timing resistor has incorrect value of 464K; should be 806K per design specification to achieve the intended 285kHz switching frequency. Current value results in approximately 504kHz operation.</summary>!thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="27.62,36.84,35.12,44.34" aspect-ratio="1.29" } <ul><li>R816 pin 1 is connected to +5VSB net (from schematic)</li><li>R816 pin 2 is connected to net $25N1081 (TON pin of U41) (from schematic)</li><li>R816 value is 464K per component attributes (from schematic)</li><li>Schematic design note specifies 'Rton=806K, F=285KHz' (from schematic)</li><li>On-time formula is tON = 3.85p × RTON × VVDDQ / (VIN - 0.5) (from datasheet <a href="https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=15">RT8207</a>, page 15)</li><li>Switching frequency formula: f = (VIN - 0.5) / (3.85p × VIN × RTON) (from schematic)</li><li>With RTON=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 504kHz (reasoning)</li><li>With RTON=806K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 290kHz, matching the design note (reasoning)</li><li>The resistor value does not match the design specification, indicating an error in component selection (reasoning)</li><li>Higher switching frequency affects inductor selection, core losses, switching losses, and EMI performance (reasoning)</li><li>R816 should be changed from 464K to 806K to achieve the intended 285kHz switching frequency (reasoning)</li></ul></details> | </details> <details> <summary>R814 - 1120-0187 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0187) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Upper feedback resistor correctly connected between +VDIMM output and FB pin to set output voltage to 1.35V for DDR3L operation. | | 2 | 2 | $25N987 | ✅ | Upper feedback resistor correctly connected between +VDIMM output and FB pin to set output voltage to 1.35V for DDR3L operation. | </details> <details> <summary>R815 - 1120-0011 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0011) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N987 | ✅ | Lower feedback resistor correctly connected between FB pin and ground to set output voltage to 1.35V for DDR3L operation. | | 2 | 2 | GND | ✅ | Lower feedback resistor correctly connected between FB pin and ground to set output voltage to 1.35V for DDR3L operation. | </details> <details> <summary>R817 - 1120-0267 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0267) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1195 | ✅ | Current limit setting resistor correctly connected between VDD and CS pin to set overcurrent protection threshold to approximately 11A. | | 2 | 2 | $25N1238 | ✅ | Current limit setting resistor correctly connected between VDD and CS pin to set overcurrent protection threshold to approximately 11A. | </details> <details> <summary>R813 - 110-0004466 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004466) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1195 | ✅ | RC filter resistor correctly connected between VDDP supply and VDD analog supply for noise filtering. Value is 2.2Ω, which is lower than the typical 5.1Ω recommendation but provides adequate filtering with reduced voltage drop. | | 2 | 2 | +5VSB | ✅ | RC filter resistor correctly connected between VDDP supply and VDD analog supply for noise filtering. Value is 2.2Ω, which is lower than the typical 5.1Ω recommendation but provides adequate filtering with reduced voltage drop. | </details> <details> <summary>R810 - 110-0001875 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N1291 | ✅ | Pull-up resistor for DEM pin, likely configuring diode emulation mode operation. The schematic uses a 24-pin package variant while available datasheet shows 20-pin variant, so DEM pin function cannot be fully verified from datasheet. | | 2 | 2 | +5VSB | ✅ | Pull-up resistor for DEM pin, likely configuring diode emulation mode operation. The schematic uses a 24-pin package variant while available datasheet shows 20-pin variant, so DEM pin function cannot be fully verified from datasheet. | </details> <details> <summary>C382 - 2220-0047 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2220-0047) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Compensation capacitor (22pF) in feedback network, providing stability for feedback divider. | | 2 | 2 | $25N987 | ✅ | Compensation capacitor (22pF) in feedback network, providing stability for feedback divider. | </details> <details> <summary>Q102 - FDMS3604S ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pub/Collateral/FDMS3604S-D.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/FDMS3604S) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | Q1G | $25N897 | ✅ | High-side gate (Q1G) correctly connected to UGATE output from controller U41 pin 21 via net $25N897. | | 2 | VIN_A | DDR3L_VIN | ✅ | Drain pins (VIN_A, VIN_B, VIN_C) correctly connected to input voltage rail DDR3L_VIN, which is derived from +5VSB through ferrite beads. | | 3 | VIN_B | DDR3L_VIN | ✅ | Drain pins (VIN_A, VIN_B, VIN_C) correctly connected to input voltage rail DDR3L_VIN, which is derived from +5VSB through ferrite beads. | | 4 | VIN_C | DDR3L_VIN | ✅ | Drain pins (VIN_A, VIN_B, VIN_C) correctly connected to input voltage rail DDR3L_VIN, which is derived from +5VSB through ferrite beads. | | 5 | PGND_A | GND | ✅ | Source pins (PGND_A, PGND_B, PGND_C) correctly connected to ground, providing the return path for the low-side synchronous FET. | | 6 | PGND_B | GND | ✅ | Source pins (PGND_A, PGND_B, PGND_C) correctly connected to ground, providing the return path for the low-side synchronous FET. | | 7 | PGND_C | GND | ✅ | Source pins (PGND_A, PGND_B, PGND_C) correctly connected to ground, providing the return path for the low-side synchronous FET. | | 8 | Q2G | $25N901 | ✅ | Low-side gate (Q2G) correctly connected to LGATE output from controller U41 pin 19 via net $25N901. | | 9 | PHASE | DDR_PHASE | ✅ | PHASE pin correctly connected to output inductor L11 and bootstrap capacitor C309, forming the switching node of the buck converter. | </details> <details> <summary>R298 - 110-0004467 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004467) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | $25N771 | ✅ | Bootstrap resistor input correctly connected to U41 BOOT pin via net $25N771, forming part of the bootstrap charging circuit. | | 2 | 2 | DDR_BST | ✅ | Bootstrap resistor output correctly connected to intermediate bootstrap node DDR_BST, which connects to bootstrap capacitor C309. | </details> <details> <summary>L11 - 125-0004454 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/125-0004454) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | DDR_PHASE | ✅ | Inductor input correctly connected to switching node DDR_PHASE from Q102 pin 9. | | 2 | 2 | +VDIMM | ✅ | Inductor output correctly connected to output voltage rail +VDIMM, which supplies 1.35V to the DIMM with maximum current of 7.1A. | </details> <details> <summary>L5 - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is correctly connected to the +5VSB standby power rail, serving as the input to the ferrite bead filter. | | 2 | 2 | DDR3L_VIN | ✅ | Pin 2 is correctly connected to the DDR3L_VIN net, providing filtered power to the DDR3L voltage regulator input stage. | </details> <details> <summary>L6 - 126-0004457 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0004457) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | Pin 1 is correctly connected to the +5VSB standby power rail in parallel with L5, serving as the input to the ferrite bead filter. | | 2 | 2 | DDR3L_VIN | ✅ | Pin 2 is correctly connected to the DDR3L_VIN net in parallel with L5, providing filtered power to the DDR3L voltage regulator input stage. | </details> <details> <summary>C129 - 123-0005035 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0005035) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | P | +VDIMM | ✅ | Positive terminal correctly connected to +VDIMM output rail. This is the bulk output capacitor for the DDR memory power supply. However, the 2V voltage rating provides marginal derating for the 1.35V rail. | | 2 | N | GND | ✅ | Negative terminal correctly connected to ground reference. | </details> <details> <summary>C361 - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM_VTT | ✅ | Connected to +VDIMM_VTT rail. This pin provides bulk decoupling for the VTT termination voltage output from the RT8207 DDR power controller. | | 2 | 2 | GND | ✅ | Connected to GND. This provides the return path for the VTT rail decoupling capacitor. | </details> <details> <summary>C362 - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM_VTT | ✅ | Connected to +VDIMM_VTT rail in parallel with C361. This provides additional bulk decoupling capacitance and reduces ESR/ESL for the VTT termination voltage. | | 2 | 2 | GND | ✅ | Connected to GND. This provides the return path for the VTT rail decoupling capacitor. | </details> <details> <summary>C359 - 2232-0012 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2232-0012) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +VDIMM | ✅ | Output decoupling capacitor for +VDIMM rail. Pin 1 connects to +VDIMM, Pin 2 connects to GND. | | 2 | 2 | GND | ✅ | Output decoupling capacitor for +VDIMM rail. Pin 1 connects to +VDIMM, Pin 2 connects to GND. | </details> <details> <summary>C140 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V). | | 2 | 2 | +VDIMM | ✅ | Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V). | </details> <details> <summary>C137 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V). | | 2 | 2 | +VDIMM | ✅ | Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V). | </details> <details> <summary>C141 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V). | | 2 | 2 | +VDIMM | ✅ | Output decoupling capacitor for +VDIMM rail. Pin 1 connects to GND, Pin 2 connects to +VDIMM (1.35V). | </details> <details> <summary>C126 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, providing the ground reference for this input decoupling capacitor. | | 2 | 2 | DDR3L_VIN | ✅ | Pin 2 is connected to DDR3L_VIN, the input power rail for the DDR buck converter. | </details> <details> <summary>C127 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, providing the ground reference for this input decoupling capacitor. | | 2 | 2 | DDR3L_VIN | ✅ | Pin 2 is connected to DDR3L_VIN, the input power rail for the DDR buck converter. | </details> <details> <summary>C128 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, providing the ground reference for this input decoupling capacitor. | | 2 | 2 | DDR3L_VIN | ✅ | Pin 2 is connected to DDR3L_VIN, the input power rail for the DDR buck converter. | </details> <details> <summary>C328 - 123-0001176 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001176) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | Pin 1 is connected to GND, providing the ground reference for this input decoupling capacitor. | | 2 | 2 | DDR3L_VIN | ✅ | Pin 2 is connected to DDR3L_VIN, the input power rail for the DDR buck converter. | </details> <details> <summary>R24 - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | R24 (12.1K) is correctly configured as the upper resistor (R1) in the feedback divider for U21, connecting from +V1P8S to +V1P8S_FB. | | 2 | 2 | +V1P8S_FB | ✅ | R24 (12.1K) is correctly configured as the upper resistor (R1) in the feedback divider for U21, connecting from +V1P8S to +V1P8S_FB. | </details> <details> <summary>R25 - 110-0004490 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004490) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | GND | ✅ | R25 (9.53K) is correctly configured as the lower resistor (R2) in the feedback divider for U21, connecting from +V1P8S_FB to GND. | | 2 | 2 | +V1P8S_FB | ✅ | R25 (9.53K) is correctly configured as the lower resistor (R2) in the feedback divider for U21, connecting from +V1P8S_FB to GND. | </details> <details> <summary>R23 - 110-0002058 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8S | ✅ | R23 (4.7K) is correctly configured as a pull-up resistor for the power good signal, connecting from +V1P8S to +V1P8S_PGD. | | 2 | 2 | +V1P8S_PGD | ✅ | R23 (4.7K) is correctly configured as a pull-up resistor for the power good signal, connecting from +V1P8S to +V1P8S_PGD. | </details> <details> <summary>R22 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | 1P8V_EN | ✅ | R22 (0 ohm) is correctly configured as a jumper connecting the enable signal 1P8V_EN to +V1P8S_EN. | | 2 | 2 | +V1P8S_EN | ✅ | R22 (0 ohm) is correctly configured as a jumper connecting the enable signal 1P8V_EN to +V1P8S_EN. | </details> <details> <summary>U21 - LDO_ULD_3A_SO8 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004526) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P8S_PGD | ✅ | PGOOD pin is correctly connected to +V1P8S_PGD net, which is pulled up to the output voltage through R23 (4.7K). This is a typical configuration for an open-drain power good output. | | 2 | EN | +V1P8S_EN | ✅ | EN pin is correctly connected to +V1P8S_EN net, which is driven from 1P8V_EN through R22 (0 ohm jumper). The enable signal is pulled up to +VCC through R125 (4.7K), which will exceed the 1.1V enable threshold. | | 3 | VIN | +PS_3VSB | ✅ | VIN pin is correctly connected to +PS_3VSB, the input power supply rail. Multiple input capacitors (C3, C6, C19, C156, C18) are present for filtering and stability. | | 4 | VDD | +PS_3VSB | ✅ | VDD pin is correctly connected to +PS_3VSB, the same as VIN. This is typical for LDOs where VDD supplies the control circuitry. | | 5 | NC | | ✅ | NC pin has no connection, which is correct as this pin is designated as no connect. | | 6 | VOUT | +V1P8S | ✅ | VOUT pin is correctly connected to +V1P8S output rail. Multiple output capacitors (C8, C4, C7) provide filtering and stability. The output voltage is approximately 1.816V based on the feedback divider. | | 7 | ADJ | +V1P8S_FB | ✅ | ADJ pin is correctly connected to +V1P8S_FB feedback node. The feedback divider consists of R24 (12.1K) to VOUT and R25 (9.53K) to GND, which sets the output voltage to approximately 1.816V using the formula Vout = 0.8(1 + R1/R2). | | 8 | GND1 | GND | ✅ | GND1 pin is correctly connected to the GND net, providing the ground reference for the regulator. | | 9 | GND2 | GND | ✅ | GND2 pin is correctly connected to the GND net. Having two ground pins improves thermal and electrical performance. | </details> <details> <summary>R320 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0022) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | VCNTL_V1P0S | ✅ | 10 ohm resistor connects VCNTL pin of U38 LDO to +VCC supply rail, with 1uF capacitor to ground forming RC filter. Connection purpose cannot be definitively verified without U38 datasheet. | | 2 | 2 | +VCC | ✅ | 10 ohm resistor connects VCNTL pin of U38 LDO to +VCC supply rail, with 1uF capacitor to ground forming RC filter. Connection purpose cannot be definitively verified without U38 datasheet. | </details> <details> <summary>U38 - LDO_ULD_5A_SO8 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004525) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | GND | GND | ✅ | Ground pin correctly connected to GND net. | | 2 | FB | FB_V1P0S | ✅ | Feedback pin correctly connected to resistive divider network formed by R136 (40.2K to output) and R135 (143K to ground). | | 3 | VOUT-2 | +V1P0S | ✅ | Output pins correctly connected together to +V1P0S rail with appropriate decoupling capacitors. However, the total load current of 4.9A (1.3A + 3.6A per text notes) leaves only 2% margin below the 5A maximum rating, which is insufficient for robust design. | | 4 | VOUT-1 | +V1P0S | ✅ | Output pins correctly connected together to +V1P0S rail with appropriate decoupling capacitors. However, the total load current of 4.9A (1.3A + 3.6A per text notes) leaves only 2% margin below the 5A maximum rating, which is insufficient for robust design. | | 5 | VIN-2 | +VDIMM | ✅ | Input pins correctly connected together to +VDIMM supply rail with appropriate input capacitors. | | 9 | VIN-1 | +VDIMM | ✅ | Input pins correctly connected together to +VDIMM supply rail with appropriate input capacitors. | | 6 | VCNTL | VCNTL_V1P0S | ✅ | VCNTL pin connected to +VCC through R320 (10 ohm) with C117 (1uF) to ground. Without datasheet, cannot verify if this configuration is correct for the VCNTL function. | | 7 | POK | V1P0S_PG | ✅ | Power good output pin correctly connected to V1P0S_PG net with pullup resistor R319 (10K to +VCC) and driving enable signal for downstream regulator through R134. | | 8 | EN | 1P0V_EN | ✅ | Enable input pin correctly connected to 1P0V_EN net, which is controlled by VCORE_GFX_PG through R306 (0 ohm jumper). | </details> <details> <summary>R150 - 110-0002560 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002560) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | Upper feedback resistor correctly connected between the SENSE/ADJ pin and VOUT to set the output voltage. | | 2 | 2 | +V1P8A | ✅ | Upper feedback resistor correctly connected between the SENSE/ADJ pin and VOUT to set the output voltage. | </details> <details> <summary>U20 - NCP606 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.onsemi.com/pdf/datasheet/ncp605-d.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004677) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | VIN1 | +PS_3VSB | ✅ | VIN1 is correctly connected to the +PS_3VSB input power rail with appropriate decoupling capacitors nearby. | | 2 | GND | GND | ✅ | GND pin is correctly connected to the ground plane. | | 3 | EN | +V1P8A_EN | ✅ | EN pin is correctly connected to the power sequencing enable signal from U24 through R151, with appropriate filtering capacitor C158. | | 4 | VOUT | +V1P8A | ✅ | VOUT pin is correctly connected to the +V1P8A output rail with adequate decoupling capacitor C151. | | 5 | SENSE/ADJ | +V1P8A_FB | ✅ | SENSE/ADJ pin is correctly connected to a resistor divider network (R150 and R153) that sets the output voltage to approximately 1.8V. | | 6 | VIN2 | +PS_3VSB | ✅ | VIN2 is correctly connected to +PS_3VSB, matching VIN1 as required by the datasheet. | | 7 | GND_PAD | GND | ✅ | GND_PAD (exposed pad) is correctly connected to ground for thermal management. | </details> <details> <summary>R153 - 110-0002726 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002726) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P8A_FB | ✅ | Lower feedback resistor correctly connected between the SENSE/ADJ pin and ground to set the output voltage. | | 2 | 2 | GND | ✅ | Lower feedback resistor correctly connected between the SENSE/ADJ pin and ground to set the output voltage. | </details> <details> <summary>R151 - 110-0001853 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | Zero-ohm resistor correctly passes the power good signal from U24 to enable U20, creating proper power sequencing. | | 2 | 2 | +V1P8A_EN | ✅ | Zero-ohm resistor correctly passes the power good signal from U24 to enable U20, creating proper power sequencing. | </details> <details> <summary>U24 - LDO_ULD_3A_SO8 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004526) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | PGOOD | +V1P0A_PWRGD | ✅ | PGOOD pin is correctly connected to +V1P0A_PWRGD net with pull-up resistor R33 to +PS_3VSB. This provides an open-drain power good output signal for sequencing. | | 2 | EN | +V1P0A_ENABLE | ✅ | EN pin is correctly connected to +V1P0A_ENABLE net with pull-up resistor R32 from +5VSB. The enable threshold requirement of >1.1V is satisfied by the +5VSB pull-up. | | 3 | VIN | +PS_3VSB | ✅ | VIN pin is correctly connected to +PS_3VSB, which is the 3.3V standby input supply for the LDO. | | 4 | VDD | +PS_3VSB | ✅ | VDD pin is correctly connected to +PS_3VSB, providing power to the internal control circuitry of the LDO. | | 5 | NC | | ✅ | NC pin is correctly left unconnected as specified by the component definition. | | 6 | VOUT | +V1P0A | ✅ | VOUT pin is correctly connected to +V1P0A net with appropriate decoupling capacitors. The output provides 1.0V analog supply. | | 7 | ADJ | +V1P0A_FB | ✅ | ADJ pin is correctly connected to the feedback network consisting of R34 (6.04K) and R35 (23.7K), which sets the output voltage to approximately 1.0V. | | 8 | GND1 | GND | ✅ | GND1 and GND2 pins are correctly connected to the GND net. Dual ground pins are typical for LDOs to improve thermal and electrical performance. | | 9 | GND2 | GND | ✅ | GND1 and GND2 pins are correctly connected to the GND net. Dual ground pins are typical for LDOs to improve thermal and electrical performance. | </details> <details> <summary>R32 - 4.7K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +5VSB | ✅ | R32 is a pull-up resistor correctly connected between +5VSB and the enable pin of U24, ensuring the enable signal is above the 1.1V threshold when active. | | 2 | 2 | +V1P0A_ENABLE | ✅ | R32 is a pull-up resistor correctly connected between +5VSB and the enable pin of U24, ensuring the enable signal is above the 1.1V threshold when active. | </details> <details> <summary>R35 - 23.7K ohm 1% 1/4W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004494) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | R35 is the bottom resistor (R2) in the feedback divider network for U24, correctly connected between the ADJ pin and GND to set the output voltage to 1.0V. | | 2 | 2 | GND | ✅ | R35 is the bottom resistor (R2) in the feedback divider network for U24, correctly connected between the ADJ pin and GND to set the output voltage to 1.0V. | </details> <details> <summary>R33 - 4.7K ohm 1% 1/10W 0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +PS_3VSB | ✅ | R33 is a pull-up resistor correctly connected between +PS_3VSB and the power good output of U24, providing proper open-drain operation. | | 2 | 2 | +V1P0A_PWRGD | ✅ | R33 is a pull-up resistor correctly connected between +PS_3VSB and the power good output of U24, providing proper open-drain operation. | </details> <details> <summary>R34 - 6.04K ohm 1% 1/16W 0402 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0003781) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_FB | ✅ | R34 is the top resistor (R1) in the feedback divider network for U24, correctly connected between the ADJ pin and VOUT to set the output voltage to 1.0V. | | 2 | 2 | +V1P0A | ✅ | R34 is the top resistor (R1) in the feedback divider network for U24, correctly connected between the ADJ pin and VOUT to set the output voltage to 1.0V. | </details> <details> <summary>R120 - 10K0 resistor ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P35S | ✅ | Connected to +V1P35S output voltage from Q5 source for power good sensing. | | 2 | 2 | 1P35V_PWG | ✅ | Connected to 1P35V_PWG which drives the base of Q3 to generate power good signaling for downstream sequencing. | </details> <details> <summary>Q5 - MOSFET_N_CH_30V_3.5A_TSMT3 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://mm.digikey.com/Volume0/opasdata/d220001/medias/docus/7466/RXR035N03.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/132-0004421) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | D | DRAIN | +VDIMM | ✅ | Drain is correctly connected to +VDIMM input voltage with appropriate decoupling capacitors for a high-side switch configuration. | | G | GATE | 1P35V_EN | ✅ | Gate is driven from V1P0S_PG through R134 (1kΩ) to enable the MOSFET when V1P0S power is good. The gate voltage depends on the +VCC rail voltage, which must provide sufficient VGS to fully enhance the MOSFET. | | S | SOURCE | +V1P35S | ✅ | Source is correctly connected to +V1P35S output with decoupling capacitors and power good sensing through R120. The configuration is appropriate for a high-side switch. | </details> <details> <summary>R134 - RES_1Kohm_1%_1/10W_0402 ✅</summary> DRCY found no issues in this component 🎉 ℹ️ DRCY didn't use a Datasheet for this component. | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | V1P0S_PG | ✅ | Connected to V1P0S_PG power good signal from U38 LDO, which controls the enable signal for Q5 gate drive. | | 2 | 2 | 1P35V_EN | ✅ | Connected to 1P35V_EN which drives the gate of Q5 through appropriate current limiting. | </details> <details> <summary>Q1 - XSTR_NPN_DUAL_40V_SOT-363 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/132-0004425) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter 1 of first NPN transistor, correctly connected to ground. | | 2 | B1 | PSGOOD | ✅ | Base 1 of first NPN transistor, correctly connected to PSGOOD signal which controls the transistor switching. | | 3 | C2 | SYS_PWRGD | ✅ | Collector 2 of second NPN transistor, correctly connected to SYS_PWRGD output signal. | | 4 | E2 | GND | ✅ | Emitter 2 of second NPN transistor, correctly connected to ground. | | 5 | B2 | PSPUP | ✅ | Base 2 and Collector 1 are both connected to PSPUP, creating a feedback path where Q1A controls Q1B. This is correct for the power sequencing logic. | | 6 | C1 | PSPUP | ✅ | Base 2 and Collector 1 are both connected to PSPUP, creating a feedback path where Q1A controls Q1B. This is correct for the power sequencing logic. | </details> <details> <summary>Q3 - XSTR_NPN_DUAL_40V_SOT-363 ✅</summary> DRCY found no issues in this component 🎉 📄 [DRCY referred to this Datasheet for this component.](https://www.mccsemi.com/pdf/Products/MMBT3904%28SOT-23%29.pdf) [📤 Replace a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/132-0004425) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | E1 | GND | ✅ | Emitter 1 of first NPN transistor, correctly connected to ground. | | 2 | B1 | 1P35V_PWG | ✅ | Base 1 of first NPN transistor, correctly connected to 1P35V_PWG signal which indicates the 1.35V rail is good. | | 3 | C2 | 1P8V_EN | ✅ | Collector 2 of second NPN transistor, correctly connected to 1P8V_EN signal which enables the 1.8V regulator. | | 4 | E2 | GND | ✅ | Emitter 2 of second NPN transistor, correctly connected to ground. | | 5 | B2 | 1P5V_EN_B | ✅ | Base 2 and Collector 1 are both connected to 1P5V_EN_B, creating a feedback path where Q3A controls Q3B. This is correct for the power sequencing logic. | | 6 | C1 | 1P5V_EN_B | ✅ | Base 2 and Collector 1 are both connected to 1P5V_EN_B, creating a feedback path where Q3A controls Q3B. This is correct for the power sequencing logic. | </details> <details> <summary>D11 - DIODE_SCHOTTKY_30V_0.2A_SOT23 ✅</summary> DRCY found no issues in this component 🎉 ⚠️ DRCY couldn't retrieve a Datasheet for this component. [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/130-0004403) | Pin Designator | Pin Name | Net | Correct? | Analysis | |---------------:|----------|-----|:--------:|----------| | 1 | 1 | +V1P0A_PWRGD | ✅ | Dual Schottky diode configured to combine power good signals. Pin assignment needs verification as datasheet is not available. | | 2 | 2 | SLP_S3_L | ✅ | Dual Schottky diode configured to combine power good signals. Pin assignment needs verification as datasheet is not available. | | 3 | 3 | PSGOOD | ✅ | Dual Schottky diode configured to combine power good signals. Pin assignment needs verification as datasheet is not available. | </details> </details> <details> <summary>📤 Upload Missing Datasheets</summary> DRCY was unable to find datasheets for the following components. You can upload datasheets to your repository to use them in future reviews. - **R127, R128, R129, R130, R192, R216, R243, R261, R293, R300, R302, R354, R41, R42, R43, R46, R48, R51, R72, R73, R74, R809** (110-0001853): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853) - **R147, R50** (110-0001859): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001859) - **R102, R116, R124, R183, R190, R191, R2, R209, R210, R211, R220, R221, R260, R268, R28, R29, R30, R400, R71, R810** (110-0001875): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001875) - **R186, R187, R208, R233, R234, R259, R401** (110-0001923): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001923) - **R206, R812** (110-0001951): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001951) - **R60, R61** (110-0001957): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001957) - **R179** (110-0001960): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001960) - **R11, R12, R269, R270** (110-0001967): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001967) - **R171, R172, R257, R52** (110-0001984): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001984) - **R819** (110-0002000): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002000) - **R136** (110-0002029): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002029) - **R152, R222, R265, R275** (110-0002124): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002124) - **R150, R24** (110-0002560): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002560) - **R213, R38, R39** (110-0002631): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002631) - **R153** (110-0002726): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002726) - **R240, R241, R242, R258** (110-0003059): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0003059) - **R34** (110-0003781): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0003781) - **R813** (110-0004466): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004466) - **R298** (110-0004467): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004467) - **R185, R77** (110-0004472): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004472) - **R255** (110-0004474): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004474) - **R217, R218, R239** (110-0004476): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004476) - **R212** (110-0004478): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004478) - **R25** (110-0004490): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004490) - **R35** (110-0004494): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004494) - **R135** (110-0004498): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004498) - **R40** (110-0004695): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0004695) - **R832, R833, R834, R835** (1120-0003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0003) - **R837, R838, R839** (1120-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0010) - **R815, R820, R821, R822, R823, R824, R825, R826, R827, R828, R829, R830, R831** (1120-0011): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0011) - **R836** (1120-0018): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0018) - **R320** (1120-0022): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0022) - **R847** (1120-0032): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0032) - **R801, R802, R803, R804, R805, R806, R807, R808** (1120-0119): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0119) - **R816** (1120-0149): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0149) - **R814** (1120-0187): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0187) - **R843, R844** (1120-0203): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0203) - **R817** (1120-0267): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0267) - **R848** (1120-0359): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0359) - **R840, R841, R842** (1121-0001): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1121-0001) - **C10, C11, C12, C13, C177, C178, C179, C180** (123-0001038): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001038) - **C191, C192, C205, C206, C207, C208** (123-0001056): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001056) - **C252, C253** (123-0001107): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001107) - **C103, C126, C127, C128, C137, C140, C141, C328, C91** (123-0001176): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0001176) - **C148** (123-0004408): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0004408) - **C129, C76, C77, C87** (123-0005035): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/123-0005035) - **L11** (125-0004454): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/125-0004454) - **L3** (125-0004501): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/125-0004501) - **FB3** (126-0001423): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0001423) - **FB1, FB11, FB4, FB5, L12, L13, L5, L6** (126-0004457): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/126-0004457) - **D11** (130-0004403): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/130-0004403) - **U38** (140-0004525): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004525) - **U21, U24** (140-0004526): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004526) - **Y1** (145-0004789): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/145-0004789) - **X1, Y2** (145-0004792): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/145-0004792) - **P1** (158-0004513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/158-0004513) - **J10** (158-0004534): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/158-0004534) - **C429, C430, C431** (2220-0039): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2220-0039) - **C382** (2220-0047): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2220-0047) - **C425** (2221-0017): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2221-0017) - **C428** (2222-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2222-0014) - **C426, C427** (2222-0016): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2222-0016) - **C359, C361, C362, C419, C420, C421, C422, C423, C424** (2232-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2232-0012) - **C66, C67, C68, C78, C79, C80, C81** (2242-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/2242-0014) - **J5, J6, J7** (258-0002513): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0002513) - **USB1** (258-0004503): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0004503) - **J2** (258-0004524): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0004524) - **J1** (258-0004612): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0004612) - **J4** (258-0004869): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0004869) - **JP1** (258-0005019): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/258-0005019) - **FB12** (3044-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3044-0010) - **FB13** (3044-0012): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3044-0012) - **L8** (3120-0183): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3120-0183) - **L18, L4** (3120-0266): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3120-0266) - **CHOKE1, CHOKE2, CHOKE3, CHOKE4, L14, L15, L16, L17** (3142-0014): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3142-0014) - **J11** (3362-0042): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3362-0042) - **J8** (3430-0212): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3430-0212) - **BH1** (353-0003073): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/353-0003073) - **FL1** (3750-0010): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3750-0010) - **SW1** (3770-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3770-0026) - **TH1, TH2, TH3, TH4** (3880-0004): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/3880-0004) - **U42** (4300-0071): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4300-0071) - **U5, U6** (4327-0009): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4327-0009) - **D1, D2** (4560-0045): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4560-0045) - **D13** (4620-0026): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/4620-0026) - **TP11, TP12** (999-0000002): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/999-0000002) - **TP1, TP17, TP18, TP2** (999-0000003): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/999-0000003) - **SP1, SP2** (999-0000005): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/999-0000005) - **D3, D4, D6** (BAT54A-S): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAT54A-S) - **D10, D5, D8** (BAT754C): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAT754C) - **Q2, Q9** (BAV99-7-F-S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BAV99-7-F-S-X) - **L1, L2** (BKP2125HS221-T): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/BKP2125HS221-T) - **U33** (M24C02-WMN6TP-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/M24C02-WMN6TP-X) - **U25, U26** (NCP81109GMNTXG): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NCP81109GMNTXG) - **U35** (NCT3012S-X): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NCT3012S-X) - **U18** (NTB0104GU12): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTB0104GU12) - **U4, U7** (NTS0102GT): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTS0102GT) - **U10, U14, U15, U16, U17, U19** (NTS0104GU12): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/NTS0104GU12) - **P2** (SCHA5B0200): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/SCHA5B0200) - **U29** (TPD4USB30): [📤 Upload a datasheet](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/TPD4USB30) </details> Note: DRCY uses AI. Please verify the outputs.

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:08 +00:00

[🚨 Error] Component R38, pins 1, 2: Pull-down resistor on VGA DDC data line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation.

Pin 1 is connected to net CRT_DAT (from schematic)
Pin 2 is connected to GND (from schematic)
Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) (from schematic)
This resistor acts as a pull-down on the VGA DDC data line (reasoning)
DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning)
I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning)
Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning)
If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning)
If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning)
The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)

All affected pins

Component CPU1, pins `BC1, BC2`: VGA_DDCCLK and VGA_DDCDATA pins incorrectly connected through 150-ohm resistors to GND. DDC uses I2C protocol which requires pull-up resistors, not pull-downs.

Pin BC1 is named VGA_DDCCLK and connects to net CRT_CLK (from schematic)
Pin BC2 is named VGA_DDCDATA and connects to net CRT_DAT (from schematic)
R39 (150 ohm) connects CRT_CLK pin 1 to GND pin 2 (from schematic)
R38 (150 ohm) connects CRT_DAT pin 1 to GND pin 2 (from schematic)
DDC (Display Data Channel) is an I2C-based protocol used for monitor communication and identification (reasoning)
I2C protocol requires pull-up resistors on both SDA and SCL lines because they are open-drain signals (reasoning)
Typical I2C pull-up resistor values range from 2.2K to 10K ohms connected to a positive voltage rail (typically 3.3V or 5V) (reasoning)
Pull-down resistors on I2C lines prevent proper communication by holding the lines low, making it impossible for devices to drive the lines high (reasoning)
The 150-ohm value is too low for I2C pull-ups and would draw excessive current even if connected to the correct rail (reasoning)
These resistors should be changed to pull-up resistors connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) with values in the 2.2K-10K range (reasoning)

Component R38, pins `1, 2`: Pull-down resistor on VGA DDC data line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation.

Pin 1 is connected to net CRT_DAT (from schematic)
Pin 2 is connected to GND (from schematic)
Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) (from schematic)
This resistor acts as a pull-down on the VGA DDC data line (reasoning)
DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning)
I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning)
Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning)
If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning)
If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning)
The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)

Component R39, pins `1, 2`: Pull-down resistor on VGA DDC clock line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation.

Pin 1 is connected to net CRT_CLK (from schematic)
Pin 2 is connected to GND (from schematic)
Net CRT_CLK connects to CPU1 pin BC1 (VGA_DDCCLK) (from schematic)
This resistor acts as a pull-down on the VGA DDC clock line (reasoning)
DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading (reasoning)
I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation (reasoning)
Pull-down resistors on I2C lines would hold the signals low and prevent proper communication (reasoning)
If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) (reasoning)
If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional (reasoning)
The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented (from schematic)

Datasheets: 📄 CPU1

_{Upload/replace a datasheet: 📤 CPU1 📤 R38 📤 R39}

[🚨 Error] **Component `R38`, pins `1, 2`: Pull-down resistor on VGA DDC data line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="68.52,40.96,76.93,48.46" aspect-ratio="1.29" } - Pin 1 is connected to net CRT_DAT *(from schematic)* - Pin 2 is connected to GND *(from schematic)* - Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) *(from schematic)* - This resistor acts as a pull-down on the VGA DDC data line *(reasoning)* - DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading *(reasoning)* - I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation *(reasoning)* - Pull-down resistors on I2C lines would hold the signals low and prevent proper communication *(reasoning)* - If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) *(reasoning)* - If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional *(reasoning)* - The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented *(from schematic)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>CPU1</code>, pins `BC1, BC2`: VGA_DDCCLK and VGA_DDCDATA pins incorrectly connected through 150-ohm resistors to GND. DDC uses I2C protocol which requires pull-up resistors, not pull-downs.</summary> - Pin BC1 is named VGA_DDCCLK and connects to net CRT_CLK *(from schematic)* - Pin BC2 is named VGA_DDCDATA and connects to net CRT_DAT *(from schematic)* - R39 (150 ohm) connects CRT_CLK pin 1 to GND pin 2 *(from schematic)* - R38 (150 ohm) connects CRT_DAT pin 1 to GND pin 2 *(from schematic)* - DDC (Display Data Channel) is an I2C-based protocol used for monitor communication and identification *(reasoning)* - I2C protocol requires pull-up resistors on both SDA and SCL lines because they are open-drain signals *(reasoning)* - Typical I2C pull-up resistor values range from 2.2K to 10K ohms connected to a positive voltage rail (typically 3.3V or 5V) *(reasoning)* - Pull-down resistors on I2C lines prevent proper communication by holding the lines low, making it impossible for devices to drive the lines high *(reasoning)* - The 150-ohm value is too low for I2C pull-ups and would draw excessive current even if connected to the correct rail *(reasoning)* - These resistors should be changed to pull-up resistors connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) with values in the 2.2K-10K range *(reasoning)* </details> <details> <summary>Component <code>R38</code>, pins `1, 2`: Pull-down resistor on VGA DDC data line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation.</summary> - Pin 1 is connected to net CRT_DAT *(from schematic)* - Pin 2 is connected to GND *(from schematic)* - Net CRT_DAT connects to CPU1 pin BC2 (VGA_DDCDATA) *(from schematic)* - This resistor acts as a pull-down on the VGA DDC data line *(reasoning)* - DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading *(reasoning)* - I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation *(reasoning)* - Pull-down resistors on I2C lines would hold the signals low and prevent proper communication *(reasoning)* - If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) *(reasoning)* - If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional *(reasoning)* - The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented *(from schematic)* </details> <details> <summary>Component <code>R39</code>, pins `1, 2`: Pull-down resistor on VGA DDC clock line. Standard DDC/I2C interfaces require pull-up resistors to enable open-drain communication, not pull-down resistors which would prevent proper DDC operation.</summary> - Pin 1 is connected to net CRT_CLK *(from schematic)* - Pin 2 is connected to GND *(from schematic)* - Net CRT_CLK connects to CPU1 pin BC1 (VGA_DDCCLK) *(from schematic)* - This resistor acts as a pull-down on the VGA DDC clock line *(reasoning)* - DDC (Display Data Channel) is an I2C-based protocol used for monitor detection and EDID reading *(reasoning)* - I2C interfaces use open-drain outputs and require pull-up resistors to the supply voltage for proper operation *(reasoning)* - Pull-down resistors on I2C lines would hold the signals low and prevent proper communication *(reasoning)* - If the VGA port is intended to be functional, this resistor should be changed to a pull-up resistor connected to an appropriate voltage rail (typically 3.3V or 5V for VGA DDC) *(reasoning)* - If the VGA port is intentionally disabled, this pull-down configuration would keep the line in a known low state, which may be intentional *(reasoning)* - The VGA video output signals (RED, GREEN, BLUE, HSYNC, VSYNC) are not shown connected in the schematic, suggesting the VGA port may not be fully implemented *(from schematic)* </details> </details> Datasheets: [📄 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf) Upload/replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004628) [📤 R38](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002631) [📤 R39](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0002631)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:08 +00:00

[🚨 Error] Component CPU1, pins AK12, AK13: DDI RCOMP pins appear to be swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative) connects to DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P) connects to DDI_RCOMP_N. The pin naming convention suggests these connections are reversed.

Pin AK13 is named D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating active-low or negative signal (from datasheet 140-0004628)
Pin AK12 is named DDI0_RCOMP_P with _P suffix indicating positive signal (from datasheet 140-0004628)
In the schematic, pin AK13 connects to net DDI_RCOMP_P (from schematic)
In the schematic, pin AK12 connects to net DDI_RCOMP_N (from schematic)
The overline notation in pin names typically indicates the complement or negative signal in differential pairs (reasoning)
The _P suffix typically indicates the positive signal in differential pairs (reasoning)
Based on naming convention, AK13 should connect to the negative net and AK12 to the positive net (reasoning)
R217 (402 ohm) is connected between DDI_RCOMP_N and DDI_RCOMP_P as a compensation resistor (from schematic)
The connections should be corrected: AK13 to DDI_RCOMP_N and AK12 to DDI_RCOMP_P (reasoning)

_{Replace a datasheet: 📤 CPU1}

[🚨 Error] **Component `CPU1`, pins `AK12, AK13`: DDI RCOMP pins appear to be swapped. Pin AK13 (D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline indicating negative) connects to DDI_RCOMP_P, while pin AK12 (DDI0_RCOMP_P) connects to DDI_RCOMP_N. The pin naming convention suggests these connections are reversed.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="38.07,30.96,45.57,39.05" aspect-ratio="1.29" } - Pin AK13 is named D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ with overline notation indicating active-low or negative signal *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf>))* - Pin AK12 is named DDI0_RCOMP_P with _P suffix indicating positive signal *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf>))* - In the schematic, pin AK13 connects to net DDI_RCOMP_P *(from schematic)* - In the schematic, pin AK12 connects to net DDI_RCOMP_N *(from schematic)* - The overline notation in pin names typically indicates the complement or negative signal in differential pairs *(reasoning)* - The _P suffix typically indicates the positive signal in differential pairs *(reasoning)* - Based on naming convention, AK13 should connect to the negative net and AK12 to the positive net *(reasoning)* - R217 (402 ohm) is connected between DDI_RCOMP_N and DDI_RCOMP_P as a compensation resistor *(from schematic)* - The connections should be corrected: AK13 to DDI_RCOMP_N and AK12 to DDI_RCOMP_P *(reasoning)* Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004628)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:08 +00:00

[🚨 Error] Component R257, pin 1: Connected to DDI1_DDCDATA (CPU1 pin P30) with pull-down to ground. This implements an incorrect method for disabling the DDI1 interface - I2C data lines should not have pull-down resistors.

Pin 1 is connected to net DDI1_DDCDAT (from schematic)
Net DDI1_DDCDAT connects to CPU1 pin P30 (DDI1_DDCDATA) (from schematic)
R257 pin 2 connects to GND, making this a pull-down resistor (from schematic)
DDI1_DDCDATA is the Display Data Channel data line for Display Port 1, which uses I2C protocol (from datasheet 140-0004628)
Other DDI1 pins are grounded: G30 (DDI1_DDCCLK) and K30 (DDI1_HPD) connect directly to GND (from schematic)
Schematic note 'Bay Trail-M Remove eDP Port' indicates DDI1 is intentionally disabled (from schematic)
I2C interfaces require pull-up resistors on clock and data lines for proper operation, not pull-down resistors (reasoning)
A pull-down resistor on an I2C data line prevents proper I2C communication (reasoning)
The datasheet recommends that unused I/O signals should be tri-stated (output driver disabled) and input receiver disabled through software configuration (from datasheet 140-0004628)
Using external pull-down resistors is not the recommended method for disabling unused display ports per the datasheet (reasoning)
If the port is properly disabled in software with tri-stated pins, external resistors are unnecessary (reasoning)
The correct approach is to configure the pins as tri-stated in software and leave them unconnected or with appropriate termination per datasheet recommendations (reasoning)

_{Upload a datasheet: 📤 R257}

[🚨 Error] **Component `R257`, pin `1`: Connected to DDI1_DDCDATA (CPU1 pin P30) with pull-down to ground. This implements an incorrect method for disabling the DDI1 interface - I2C data lines should not have pull-down resistors.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="c6d51d1759888fc83971" diff-visibility="full" variant="default" view-coords="64.43,26.26,71.93,33.76" aspect-ratio="1.29" } - Pin 1 is connected to net DDI1_DDCDAT *(from schematic)* - Net DDI1_DDCDAT connects to CPU1 pin P30 (DDI1_DDCDATA) *(from schematic)* - R257 pin 2 connects to GND, making this a pull-down resistor *(from schematic)* - DDI1_DDCDATA is the Display Data Channel data line for Display Port 1, which uses I2C protocol *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf>))* - Other DDI1 pins are grounded: G30 (DDI1_DDCCLK) and K30 (DDI1_HPD) connect directly to GND *(from schematic)* - Schematic note 'Bay Trail-M Remove eDP Port' indicates DDI1 is intentionally disabled *(from schematic)* - I2C interfaces require pull-up resistors on clock and data lines for proper operation, not pull-down resistors *(reasoning)* - A pull-down resistor on an I2C data line prevents proper I2C communication *(reasoning)* - The datasheet recommends that unused I/O signals should be tri-stated (output driver disabled) and input receiver disabled through software configuration *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf>))* - Using external pull-down resistors is not the recommended method for disabling unused display ports per the datasheet *(reasoning)* - If the port is properly disabled in software with tri-stated pins, external resistors are unnecessary *(reasoning)* - The correct approach is to configure the pins as tri-stated in software and leave them unconnected or with appropriate termination per datasheet recommendations *(reasoning)* Upload a datasheet: [📤 R257](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001984)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:08 +00:00

[🚨 Error] Component R354, pins 1, 2: This 0-ohm resistor ties SD3_WP (write protect) to SD3_CD# (card detect), which is unusual and likely incorrect. These signals should typically be independent to allow separate detection of card presence and write protection status.

Pin 1 is connected to net SD3_WP (from schematic)
Pin 2 is connected to net SD3_CD# (from schematic)
SD3_WP connects to CPU1 pin BD5 labeled SD3_WP_BD5 (from schematic)
SD3_CD# connects to CPU1 pin BC24 labeled SD3_CD# (from schematic)
R354 is a 0-ohm resistor that directly connects these two signals together (from schematic)
SD3_WP is typically an input to detect if an SD card's write protect switch is enabled, with active-low polarity where low indicates write-protected (reasoning)
SD3_CD# is typically an active-low input to detect if an SD card is physically present in the slot, where low indicates card present (reasoning)
Tying these signals together forces them to always have the same logic level, preventing independent detection of card presence and write protection status (reasoning)
With both signals tied together, when a card is present CD# goes low, which also forces WP low, indicating the card is write-protected regardless of the actual WP switch state (reasoning)
In typical SD card interface designs, card detect and write protect are separate signals with independent functionality (reasoning)
If write protect detection is not needed, the WP pin should typically be pulled to a fixed state such as high for write-enabled, rather than tied to card detect (reasoning)
This connection could cause all inserted cards to appear write-protected, preventing write operations even when the card's WP switch is off (reasoning)
Recommendation: Separate these signals and either connect WP to its own detection circuit or pull it to an appropriate fixed state if write protect detection is not required (reasoning)

_{Upload a datasheet: 📤 R354}

[🚨 Error] **Component `R354`, pins `1, 2`: This 0-ohm resistor ties SD3_WP (write protect) to SD3_CD# (card detect), which is unusual and likely incorrect. These signals should typically be independent to allow separate detection of card presence and write protection status.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="be0367a8ed73ec923161" diff-visibility="full" variant="default" view-coords="38.52,43.90,46.93,51.40" aspect-ratio="1.29" } - Pin 1 is connected to net SD3_WP *(from schematic)* - Pin 2 is connected to net SD3_CD# *(from schematic)* - SD3_WP connects to CPU1 pin BD5 labeled SD3_WP_BD5 *(from schematic)* - SD3_CD# connects to CPU1 pin BC24 labeled SD3_CD# *(from schematic)* - R354 is a 0-ohm resistor that directly connects these two signals together *(from schematic)* - SD3_WP is typically an input to detect if an SD card's write protect switch is enabled, with active-low polarity where low indicates write-protected *(reasoning)* - SD3_CD# is typically an active-low input to detect if an SD card is physically present in the slot, where low indicates card present *(reasoning)* - Tying these signals together forces them to always have the same logic level, preventing independent detection of card presence and write protection status *(reasoning)* - With both signals tied together, when a card is present CD# goes low, which also forces WP low, indicating the card is write-protected regardless of the actual WP switch state *(reasoning)* - In typical SD card interface designs, card detect and write protect are separate signals with independent functionality *(reasoning)* - If write protect detection is not needed, the WP pin should typically be pulled to a fixed state such as high for write-enabled, rather than tied to card detect *(reasoning)* - This connection could cause all inserted cards to appear write-protected, preventing write operations even when the card's WP switch is off *(reasoning)* - Recommendation: Separate these signals and either connect WP to its own detection circuit or pull it to an appropriate fixed state if write protect detection is not required *(reasoning)* Upload a datasheet: [📤 R354](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/110-0001853)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:08 +00:00

[🚨 Error] Component CPU1, pins AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33: CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.

These pins are named CORE_V1P05_S3 indicating they require 1.05V (from schematic)
All pins are connected to the +V1P0S net (from schematic)
The +V1P0S net name suggests 1.0V nominal voltage (from schematic)
Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S (from schematic)
V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet (from datasheet 140-0004628, page 120)
V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet (from datasheet 140-0004628, page 119)
CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A (from datasheet 140-0004628, page 120)
Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist (from schematic)
Text note '+V1P05S' at position near top of page references a separate 1.05V rail (from schematic)
Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage (reasoning)
The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin (reasoning)
Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction (reasoning)
The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings (from datasheet 140-0004628, page 119-120)
These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S (reasoning)

_{Replace a datasheet: 📤 CPU1}

[🚨 Error] **Component `CPU1`, pins `AC32, Y32, AA33, AF33, AG33, AG35, U33, U35, V33`: CORE_V1P05_S3 pins are connected to +V1P0S (1.0V) but should be connected to a separate 1.05V rail. This is a 50mV undervoltage condition that violates datasheet specifications.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="863828d80a4e9158f8a5" diff-visibility="full" variant="default" view-coords="36.71,28.61,61.48,49.63" aspect-ratio="1.29" } - These pins are named CORE_V1P05_S3 indicating they require 1.05V *(from schematic)* - All pins are connected to the +V1P0S net *(from schematic)* - The +V1P0S net name suggests 1.0V nominal voltage *(from schematic)* - Other pins clearly requiring 1.0V (DDI_V1P0_S0IX, DRAM_V1P0_S0IX, UNCORE_V1P0_S3) are also connected to +V1P0S *(from schematic)* - V1P05S supply should be 1.05V nominal with 1.03V minimum and 1.08V maximum per datasheet *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120>), page 120)* - V1P0S supply should be 1.0V nominal with 0.98V minimum and 1.03V maximum per datasheet *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119>), page 119)* - CORE_V1P05_S3 pins should be powered by V1P05S at 1.05V with maximum current of 1.3A *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=120>), page 120)* - Text note 'VCC_CORE_V1P05' near these pins suggests a 1.05V rail should exist *(from schematic)* - Text note '+V1P05S' at position near top of page references a separate 1.05V rail *(from schematic)* - Connecting 1.05V pins to 1.0V rail results in 50mV undervoltage *(reasoning)* - The 1.0V supply maximum of 1.03V equals the 1.05V supply minimum, leaving no design margin *(reasoning)* - Operating CORE_V1P05_S3 pins at 1.0V instead of 1.05V may cause performance degradation or malfunction *(reasoning)* - The datasheet specifies separate V1P05S and V1P0S rails with different nominal voltages and current ratings *(from datasheet [140-0004628](<https://staging.allspice.dev/AI-Evals/E2E-Turbot/raw/commit/d7be525b45f8281be2cd167e80b8125f2d34a3a0/.allspice/datasheets/140-0004628/atom_e3800_family_datasheet-1522396.pdf#page=119-120>), page 119-120)* - These pins should be connected to a separate 1.05V rail (V1P05S or +V1P05S) instead of +V1P0S *(reasoning)* Replace a datasheet: [📤 CPU1](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004628)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:08 +00:00

[🚨 Error] Component U2, pins 15, 16, 17, 18, 20, 21, 22, 23: All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure.

Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) (from schematic)
Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) (from schematic)
Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) (from schematic)
Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) (from schematic)
Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) (from schematic)
Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) (from schematic)
Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) (from schematic)
Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) (from schematic)
According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) (from datasheet 140-0004333, page 4)
The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout (from schematic)
The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) (reasoning)
Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) (reasoning)
All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet (reasoning)
Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals (reasoning)
The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN (reasoning)

_{Replace a datasheet: 📤 U2}

[🚨 Error] **Component `U2`, pins `15, 16, 17, 18, 20, 21, 22, 23`: All TMDS differential pairs (CLK, D0, D1, D2) have inverted polarity. The schematic symbol pin labels do not match the datasheet pinout for the PW package, causing all positive and negative signals to be swapped at the TPD12S016. This will cause complete HDMI link failure.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="02ce33795e3c4f20b5a8" diff-visibility="full" variant="default" view-coords="45.57,58.30,53.07,69.92" aspect-ratio="1.29" } - Pin 15 is connected to net HDMI_OUT_CLK_DN (negative signal) *(from schematic)* - Pin 16 is connected to net HDMI_OUT_CLK_DP (positive signal) *(from schematic)* - Pin 17 is connected to net HDMI_OUT_TX0_DN (negative signal) *(from schematic)* - Pin 18 is connected to net HDMI_OUT_TX0_DP (positive signal) *(from schematic)* - Pin 20 is connected to net HDMI_OUT_TX1_DN (negative signal) *(from schematic)* - Pin 21 is connected to net HDMI_OUT_TX1_DP (positive signal) *(from schematic)* - Pin 22 is connected to net HDMI_OUT_TX2_DN (negative signal) *(from schematic)* - Pin 23 is connected to net HDMI_OUT_TX2_DP (positive signal) *(from schematic)* - According to the datasheet for PW package: pin 15 is CLK+ (positive), pin 16 is CLK- (negative), pin 17 is D0+ (positive), pin 18 is D0- (negative), pin 20 is D1+ (positive), pin 21 is D1- (negative), pin 22 is D2+ (positive), pin 23 is D2- (negative) *(from datasheet [140-0004333](<https://www.ti.com/general/docs/suppproductinfo.tsp?distId=10&gotoUrl=https%3A%2F%2Fwww.ti.com%2Flit%2Fgpn%2Ftpd12s016#page=4>), page 4)* - The schematic symbol labels show: pin 15 as CLK-, pin 16 as CLK+, pin 17 as D0-, pin 18 as D0+, pin 20 as D1-, pin 21 as D1+, pin 22 as D2-, pin 23 as D2+, which is opposite to the datasheet pinout *(from schematic)* - The signal path shows negative signals (DN) from the HDMI controller flow through AC coupling capacitors and common mode chokes to nets ending in _DN, which connect to pins that the datasheet specifies as positive (+) *(reasoning)* - Similarly, positive signals (DP) from the HDMI controller flow to nets ending in _DP, which connect to pins that the datasheet specifies as negative (-) *(reasoning)* - All four TMDS differential pairs have their polarity inverted at the TPD12S016 due to the schematic symbol having incorrect pin labels that don't match the datasheet *(reasoning)* - Inverting the polarity of differential pairs will cause signal integrity issues and complete HDMI link failure, as the receiver will not be able to properly decode the TMDS signals *(reasoning)* - The correct connections should be: pin 15 to HDMI_OUT_CLK_DP, pin 16 to HDMI_OUT_CLK_DN, pin 17 to HDMI_OUT_TX0_DP, pin 18 to HDMI_OUT_TX0_DN, pin 20 to HDMI_OUT_TX1_DP, pin 21 to HDMI_OUT_TX1_DN, pin 22 to HDMI_OUT_TX2_DP, pin 23 to HDMI_OUT_TX2_DN *(reasoning)* Replace a datasheet: [📤 U2](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/140-0004333)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:09 +00:00

[⚠️ Warning] Component U32, pins 5, 8: Open-drain overcurrent flag outputs (FLG2/OC2# on pin 5, FLG1/OC1# on pin 8) connected directly to SoC without external pull-up resistors, deviating from datasheet recommendations.

Pin 5 (OC2#) is connected to SOC_USB_HOST_OC1 net and pin 8 (OC1#) is connected to SOC_USB_HOST_OC0 net (from schematic)
No external pull-up resistors are present on SOC_USB_HOST_OC0 or SOC_USB_HOST_OC1 nets on this schematic page (from schematic)
R115 (2.2K) connected to SOC_USB_HOST_EN0 is marked DNI and would be a pull-down, not a pull-up (from schematic)
The signals connect directly to the SoC which operates at 1.8V logic levels per the level translator U4 configuration (from schematic)
Pin 5 is FLG2 (Switch 2 over-current and over-temperature fault report) and pin 8 is FLG1 (Switch 1 over-current and over-temperature fault report) per the datasheet (from datasheet AP2172MPG, page 2)
FLG outputs are open-drain and active low when triggered (from datasheet AP2172MPG, page 2)
The datasheet typical application circuit shows 10k pull-up resistors from FLG outputs to IN (from datasheet AP2172MPG, page 1)
Open-drain outputs require pull-up resistors to provide a valid logic high level when not actively pulling low (reasoning)
Without external pull-ups, the signals would float when there is no fault condition, which is not a valid logic level (reasoning)
The design may rely on internal pull-ups in the SoC, which is common for GPIO pins and would allow the open-drain outputs to function correctly across the voltage domain (5V USB to 1.8V SoC) (reasoning)
However, relying on internal pull-ups creates a dependency on SoC configuration and is not guaranteed to work if the internal pull-ups are not enabled or are insufficient (reasoning)
Best practice per the datasheet is to include external pull-up resistors (typically 10k to an appropriate voltage rail) to ensure proper operation regardless of SoC configuration (reasoning)
External 10k pull-up resistors should be added to SOC_USB_HOST_OC0 and SOC_USB_HOST_OC1 nets to match datasheet recommendations and ensure reliable operation (reasoning)

_{Replace a datasheet: 📤 U32}

[⚠️ Warning] **Component `U32`, pins `5, 8`: Open-drain overcurrent flag outputs (FLG2/OC2# on pin 5, FLG1/OC1# on pin 8) connected directly to SoC without external pull-up resistors, deviating from datasheet recommendations.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="ff0b834cacfad7f44e11" diff-visibility="full" variant="default" view-coords="35.34,47.72,42.84,58.16" aspect-ratio="1.29" } - Pin 5 (OC2#) is connected to SOC_USB_HOST_OC1 net and pin 8 (OC1#) is connected to SOC_USB_HOST_OC0 net *(from schematic)* - No external pull-up resistors are present on SOC_USB_HOST_OC0 or SOC_USB_HOST_OC1 nets on this schematic page *(from schematic)* - R115 (2.2K) connected to SOC_USB_HOST_EN0 is marked DNI and would be a pull-down, not a pull-up *(from schematic)* - The signals connect directly to the SoC which operates at 1.8V logic levels per the level translator U4 configuration *(from schematic)* - Pin 5 is FLG2 (Switch 2 over-current and over-temperature fault report) and pin 8 is FLG1 (Switch 1 over-current and over-temperature fault report) per the datasheet *(from datasheet [AP2172MPG](<https://www.diodes.com/assets/Datasheets/AP2162_72.pdf#page=2>), page 2)* - FLG outputs are open-drain and active low when triggered *(from datasheet [AP2172MPG](<https://www.diodes.com/assets/Datasheets/AP2162_72.pdf#page=2>), page 2)* - The datasheet typical application circuit shows 10k pull-up resistors from FLG outputs to IN *(from datasheet [AP2172MPG](<https://www.diodes.com/assets/Datasheets/AP2162_72.pdf#page=1>), page 1)* - Open-drain outputs require pull-up resistors to provide a valid logic high level when not actively pulling low *(reasoning)* - Without external pull-ups, the signals would float when there is no fault condition, which is not a valid logic level *(reasoning)* - The design may rely on internal pull-ups in the SoC, which is common for GPIO pins and would allow the open-drain outputs to function correctly across the voltage domain (5V USB to 1.8V SoC) *(reasoning)* - However, relying on internal pull-ups creates a dependency on SoC configuration and is not guaranteed to work if the internal pull-ups are not enabled or are insufficient *(reasoning)* - Best practice per the datasheet is to include external pull-up resistors (typically 10k to an appropriate voltage rail) to ensure proper operation regardless of SoC configuration *(reasoning)* - External 10k pull-up resistors should be added to SOC_USB_HOST_OC0 and SOC_USB_HOST_OC1 nets to match datasheet recommendations and ensure reliable operation *(reasoning)* Replace a datasheet: [📤 U32](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/AP2172MPG)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:09 +00:00

[⚠️ Warning] Component Q105, pin D: Drain is connected to GPIO_LED_CONTROL net along with LED D2 anode and resistor R746, creating a parallel (shunt switch) configuration. The standard series topology should be used instead, with the drain connecting to D2 cathode.

Pin D is connected to net GPIO_LED_CONTROL (from schematic)
GPIO_LED_CONTROL net connects to R746 pin 2 (470Ω from +VCC), D2 anode, and C149 pin 1 (2.2µF to GND) (from schematic)
Pin D is the Drain terminal according to the FDN327N datasheet (from datasheet FDN327N, page 1)
The current configuration places D2 and Q105 in parallel between GPIO_LED_CONTROL and GND, creating a shunt switch topology where the MOSFET bypasses the LED (reasoning)
In the shunt switch topology, when Q105 is ON (gate high), current flows from +VCC through R746 and Q105 to GND, pulling GPIO_LED_CONTROL low and turning off D2, but wasting approximately VCC/470Ω (7-11mA depending on VCC voltage) of continuous current (reasoning)
When Q105 is OFF (gate low), GPIO_LED_CONTROL is pulled high through R746, forward-biasing D2 and turning the LED on, creating inverted control logic (GPIO high = LED off) (reasoning)
The standard low-side N-channel MOSFET LED driver topology requires the LED in series with the MOSFET: VCC → R746 → D2 anode → D2 cathode → Q105 drain → Q105 source → GND (reasoning)
The series topology provides non-inverted logic (GPIO high = LED on), eliminates power waste when the LED is off, and is the standard approach used in 99% of GPIO-controlled LED circuits (reasoning)
While the shunt switch topology is functional, it wastes significant power (7-11mA continuously when LED is off) and has no apparent advantage over the standard series topology for a system status indicator (reasoning)
The text note 'SYSTEM POWER LED - GPIO CONTROLLED' confirms this is intended as a GPIO-controlled system status indicator, which would typically use the standard series topology (from schematic)
The drain should connect to D2 cathode (not to GPIO_LED_CONTROL with R746 and D2 anode) to implement the standard, efficient series topology (reasoning)

_{Replace a datasheet: 📤 Q105}

[⚠️ Warning] **Component `Q105`, pin `D`: Drain is connected to GPIO_LED_CONTROL net along with LED D2 anode and resistor R746, creating a parallel (shunt switch) configuration. The standard series topology should be used instead, with the drain connecting to D2 cathode.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="29d21348d4ba0ba3eaf5" diff-visibility="full" variant="default" view-coords="50.34,36.84,57.84,44.34" aspect-ratio="1.29" } - Pin D is connected to net GPIO_LED_CONTROL *(from schematic)* - GPIO_LED_CONTROL net connects to R746 pin 2 (470Ω from +VCC), D2 anode, and C149 pin 1 (2.2µF to GND) *(from schematic)* - Pin D is the Drain terminal according to the FDN327N datasheet *(from datasheet [FDN327N](<https://www.onsemi.com/pdf/datasheet/fdn327n-d.pdf#page=1>), page 1)* - The current configuration places D2 and Q105 in parallel between GPIO_LED_CONTROL and GND, creating a shunt switch topology where the MOSFET bypasses the LED *(reasoning)* - In the shunt switch topology, when Q105 is ON (gate high), current flows from +VCC through R746 and Q105 to GND, pulling GPIO_LED_CONTROL low and turning off D2, but wasting approximately VCC/470Ω (7-11mA depending on VCC voltage) of continuous current *(reasoning)* - When Q105 is OFF (gate low), GPIO_LED_CONTROL is pulled high through R746, forward-biasing D2 and turning the LED on, creating inverted control logic (GPIO high = LED off) *(reasoning)* - The standard low-side N-channel MOSFET LED driver topology requires the LED in series with the MOSFET: VCC → R746 → D2 anode → D2 cathode → Q105 drain → Q105 source → GND *(reasoning)* - The series topology provides non-inverted logic (GPIO high = LED on), eliminates power waste when the LED is off, and is the standard approach used in 99% of GPIO-controlled LED circuits *(reasoning)* - While the shunt switch topology is functional, it wastes significant power (7-11mA continuously when LED is off) and has no apparent advantage over the standard series topology for a system status indicator *(reasoning)* - The text note 'SYSTEM POWER LED - GPIO CONTROLLED' confirms this is intended as a GPIO-controlled system status indicator, which would typically use the standard series topology *(from schematic)* - The drain should connect to D2 cathode (not to GPIO_LED_CONTROL with R746 and D2 anode) to implement the standard, efficient series topology *(reasoning)* Replace a datasheet: [📤 Q105](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/FDN327N)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:09 +00:00

[⚠️ Warning] Component R849, pins 1, 2: R849 is a 0 ohm jumper connecting +VCC to the EN pin of U25. With R851 (10K to GND) also populated, this creates a continuous current path from +VCC to GND through R851, drawing approximately 0.33-0.5mA depending on +VCC voltage. This is wasteful and unusual; typically only one of R849 or R851 would be populated.

Pin 1 of R849 is connected to net +VCC (from schematic)
Pin 2 of R849 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic)
R849 is a 0 ohm jumper (part number 1121-0001) (from schematic)
R851 is a 10K resistor connecting the same net $23N5607 to GND (from schematic)
With R849 as 0 ohm and R851 as 10K both populated, a current path exists from +VCC through R849 to GND through R851 (reasoning)
The current through this path would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning)
This continuous current draw is wasteful and serves no functional purpose (reasoning)
Typical enable circuit design would have either a pull-up (R849) or pull-down (R851) populated, not both (reasoning)
The 0 ohm jumper R849 would pull the EN pin high to +VCC, enabling the regulator (reasoning)
If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning)
If the intent is to disable the regulator by default or allow external control, R849 should be DNI and R851 should be populated (reasoning)
One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)

All affected pins

Component R849, pins `1, 2`: R849 is a 0 ohm jumper connecting +VCC to the EN pin of U25. With R851 (10K to GND) also populated, this creates a continuous current path from +VCC to GND through R851, drawing approximately 0.33-0.5mA depending on +VCC voltage. This is wasteful and unusual; typically only one of R849 or R851 would be populated.

Pin 1 of R849 is connected to net +VCC (from schematic)
Pin 2 of R849 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic)
R849 is a 0 ohm jumper (part number 1121-0001) (from schematic)
R851 is a 10K resistor connecting the same net $23N5607 to GND (from schematic)
With R849 as 0 ohm and R851 as 10K both populated, a current path exists from +VCC through R849 to GND through R851 (reasoning)
The current through this path would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning)
This continuous current draw is wasteful and serves no functional purpose (reasoning)
Typical enable circuit design would have either a pull-up (R849) or pull-down (R851) populated, not both (reasoning)
The 0 ohm jumper R849 would pull the EN pin high to +VCC, enabling the regulator (reasoning)
If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning)
If the intent is to disable the regulator by default or allow external control, R849 should be DNI and R851 should be populated (reasoning)
One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)

Component R851, pins `1, 2`: R851 is a 10K pull-down resistor connecting the EN pin of U25 to GND. With R849 (0 ohm to +VCC) also populated, this creates a continuous current path from +VCC to GND, drawing approximately 0.33-0.5mA. This is wasteful and unusual; typically only one of R849 or R851 would be populated.

Pin 1 of R851 is connected to net $23N5607, which connects to U25 pin 48 (EN) (from schematic)
Pin 2 of R851 is connected to net GND (from schematic)
R851 is a 10K resistor (part number 1120-0011) (from schematic)
R849 is a 0 ohm jumper connecting +VCC to the same net $23N5607 (from schematic)
With both R849 (0 ohm) and R851 (10K) populated, a current path exists from +VCC to GND (reasoning)
The current through R851 would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V (reasoning)
This continuous current draw is wasteful and serves no functional purpose (reasoning)
A pull-down resistor on an enable pin is typically used when the regulator should be disabled by default or when external control is desired (reasoning)
With R849 (0 ohm) populated, the EN pin is strongly pulled high to +VCC, making R851 redundant except for creating unwanted current draw (reasoning)
If the intent is to disable the regulator by default, R851 should be populated and R849 should be DNI (reasoning)
If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI (reasoning)
One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path (reasoning)

[⚠️ Warning] **Component `R849`, pins `1, 2`: R849 is a 0 ohm jumper connecting +VCC to the EN pin of U25. With R851 (10K to GND) also populated, this creates a continuous current path from +VCC to GND through R851, drawing approximately 0.33-0.5mA depending on +VCC voltage. This is wasteful and unusual; typically only one of R849 or R851 would be populated.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="b412abe41fc6123431ae" diff-visibility="full" variant="default" view-coords="33.07,36.25,40.57,45.52" aspect-ratio="1.29" } - Pin 1 of R849 is connected to net +VCC *(from schematic)* - Pin 2 of R849 is connected to net $23N5607, which connects to U25 pin 48 (EN) *(from schematic)* - R849 is a 0 ohm jumper (part number 1121-0001) *(from schematic)* - R851 is a 10K resistor connecting the same net $23N5607 to GND *(from schematic)* - With R849 as 0 ohm and R851 as 10K both populated, a current path exists from +VCC through R849 to GND through R851 *(reasoning)* - The current through this path would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V *(reasoning)* - This continuous current draw is wasteful and serves no functional purpose *(reasoning)* - Typical enable circuit design would have either a pull-up (R849) or pull-down (R851) populated, not both *(reasoning)* - The 0 ohm jumper R849 would pull the EN pin high to +VCC, enabling the regulator *(reasoning)* - If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI *(reasoning)* - If the intent is to disable the regulator by default or allow external control, R849 should be DNI and R851 should be populated *(reasoning)* - One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path *(reasoning)* <details> <summary>All affected pins</summary> <details> <summary>Component <code>R849</code>, pins `1, 2`: R849 is a 0 ohm jumper connecting +VCC to the EN pin of U25. With R851 (10K to GND) also populated, this creates a continuous current path from +VCC to GND through R851, drawing approximately 0.33-0.5mA depending on +VCC voltage. This is wasteful and unusual; typically only one of R849 or R851 would be populated.</summary> - Pin 1 of R849 is connected to net +VCC *(from schematic)* - Pin 2 of R849 is connected to net $23N5607, which connects to U25 pin 48 (EN) *(from schematic)* - R849 is a 0 ohm jumper (part number 1121-0001) *(from schematic)* - R851 is a 10K resistor connecting the same net $23N5607 to GND *(from schematic)* - With R849 as 0 ohm and R851 as 10K both populated, a current path exists from +VCC through R849 to GND through R851 *(reasoning)* - The current through this path would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V *(reasoning)* - This continuous current draw is wasteful and serves no functional purpose *(reasoning)* - Typical enable circuit design would have either a pull-up (R849) or pull-down (R851) populated, not both *(reasoning)* - The 0 ohm jumper R849 would pull the EN pin high to +VCC, enabling the regulator *(reasoning)* - If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI *(reasoning)* - If the intent is to disable the regulator by default or allow external control, R849 should be DNI and R851 should be populated *(reasoning)* - One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path *(reasoning)* </details> <details> <summary>Component <code>R851</code>, pins `1, 2`: R851 is a 10K pull-down resistor connecting the EN pin of U25 to GND. With R849 (0 ohm to +VCC) also populated, this creates a continuous current path from +VCC to GND, drawing approximately 0.33-0.5mA. This is wasteful and unusual; typically only one of R849 or R851 would be populated.</summary> - Pin 1 of R851 is connected to net $23N5607, which connects to U25 pin 48 (EN) *(from schematic)* - Pin 2 of R851 is connected to net GND *(from schematic)* - R851 is a 10K resistor (part number 1120-0011) *(from schematic)* - R849 is a 0 ohm jumper connecting +VCC to the same net $23N5607 *(from schematic)* - With both R849 (0 ohm) and R851 (10K) populated, a current path exists from +VCC to GND *(reasoning)* - The current through R851 would be I = +VCC / 10K, approximately 0.33mA if +VCC is 3.3V or 0.5mA if +VCC is 5V *(reasoning)* - This continuous current draw is wasteful and serves no functional purpose *(reasoning)* - A pull-down resistor on an enable pin is typically used when the regulator should be disabled by default or when external control is desired *(reasoning)* - With R849 (0 ohm) populated, the EN pin is strongly pulled high to +VCC, making R851 redundant except for creating unwanted current draw *(reasoning)* - If the intent is to disable the regulator by default, R851 should be populated and R849 should be DNI *(reasoning)* - If the intent is to always enable the regulator, R849 should be populated and R851 should be DNI *(reasoning)* - One of R849 or R851 should be marked as DNI to eliminate the unnecessary current path *(reasoning)* </details> </details>

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:09 +00:00

[🚨 Error] Component C186, pin 2: Connected to U26 pin 10 (SW1) via net $24N3595, but should connect to the main switching node VGFX-SW. The bootstrap capacitor must reference the actual switching node where the inductor connects to provide proper gate drive voltage for the high-side MOSFET.

Pin 2 is connected to net $24N3595 (from schematic)
Net $24N3595 connects only to U26 pin 10 (SW1) (from schematic)
The main switching node is VGFX-SW, which connects to U26 pins 18, 25, 26, 27, 28, 29 (SW2-SW7) and pin 51 (SW_PAD) (from schematic)
The output inductor L4 pin 1 connects to VGFX-SW, confirming this is the main switching node (from schematic)
SW1 is isolated and not connected to VGFX-SW or to any other part of the power stage except the bootstrap capacitor (from schematic)
This is a multiphase buck converter with only one inductor (L4), and all active switch nodes (SW2-SW7) are paralleled to VGFX-SW (from schematic)
In a synchronous buck converter, the bootstrap capacitor must be connected between the BST pin and the switching node to provide proper gate drive voltage for the high-side MOSFET (reasoning)
The switching node is defined as the connection point between the high-side and low-side MOSFETs, which is where the inductor connects in a buck converter (reasoning)
Since the inductor connects to VGFX-SW and all active switch outputs (SW2-SW7) connect to VGFX-SW, the bootstrap capacitor should be connected between BST and VGFX-SW (reasoning)
The current configuration with the bootstrap capacitor connected to the isolated SW1 pin will not provide proper bootstrap voltage referenced to the actual switching node (reasoning)
Pin 2 should be connected to net VGFX-SW instead of net $24N3595 to form a functional bootstrap circuit (reasoning)
While there is a small possibility that SW1 is intentionally designed as a separate bootstrap reference node in the NCP81109GMNTXG, this would be highly unusual and inconsistent with standard synchronous buck converter design practice (reasoning)
The 0.22µF capacitance and 16V voltage rating are appropriate for a bootstrap capacitor in a 5V input system (reasoning)

[🚨 Error] **Component `C186`, pin `2`: Connected to U26 pin 10 (SW1) via net $24N3595, but should connect to the main switching node VGFX-SW. The bootstrap capacitor must reference the actual switching node where the inductor connects to provide proper gate drive voltage for the high-side MOSFET.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="428456b4ca051e4f277a" diff-visibility="full" variant="default" view-coords="32.39,42.43,39.89,49.93" aspect-ratio="1.29" } - Pin 2 is connected to net $24N3595 *(from schematic)* - Net $24N3595 connects only to U26 pin 10 (SW1) *(from schematic)* - The main switching node is VGFX-SW, which connects to U26 pins 18, 25, 26, 27, 28, 29 (SW2-SW7) and pin 51 (SW_PAD) *(from schematic)* - The output inductor L4 pin 1 connects to VGFX-SW, confirming this is the main switching node *(from schematic)* - SW1 is isolated and not connected to VGFX-SW or to any other part of the power stage except the bootstrap capacitor *(from schematic)* - This is a multiphase buck converter with only one inductor (L4), and all active switch nodes (SW2-SW7) are paralleled to VGFX-SW *(from schematic)* - In a synchronous buck converter, the bootstrap capacitor must be connected between the BST pin and the switching node to provide proper gate drive voltage for the high-side MOSFET *(reasoning)* - The switching node is defined as the connection point between the high-side and low-side MOSFETs, which is where the inductor connects in a buck converter *(reasoning)* - Since the inductor connects to VGFX-SW and all active switch outputs (SW2-SW7) connect to VGFX-SW, the bootstrap capacitor should be connected between BST and VGFX-SW *(reasoning)* - The current configuration with the bootstrap capacitor connected to the isolated SW1 pin will not provide proper bootstrap voltage referenced to the actual switching node *(reasoning)* - Pin 2 should be connected to net VGFX-SW instead of net $24N3595 to form a functional bootstrap circuit *(reasoning)* - While there is a small possibility that SW1 is intentionally designed as a separate bootstrap reference node in the NCP81109GMNTXG, this would be highly unusual and inconsistent with standard synchronous buck converter design practice *(reasoning)* - The 0.22µF capacitance and 16V voltage rating are appropriate for a bootstrap capacitor in a 5V input system *(reasoning)*

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:09 +00:00

[🚨 Error] Component U41, pin 22: BOOT pin connected to bootstrap network, but bootstrap capacitor C309 is significantly undersized (0.1uF instead of recommended 1uF) and includes non-standard series resistor R298 (4.7Ω), which may cause insufficient gate drive voltage and slower switching transitions.

Pin 22 (BOOT) is connected to net $25N771 (from schematic)
Net $25N771 connects through R298 (4.7Ω resistor) to DDR_BST net (from schematic)
DDR_BST connects to C309 pin 2 (0.1uF capacitor) (from schematic)
C309 pin 1 connects to DDR_PHASE net (PHASE pin) (from schematic)
BOOT is the boost flying capacitor connection for VDDQ that supplies high side gate driver instantaneous current (from datasheet RT8207, page 2)
Datasheet recommends 1uF flying bootstrap capacitor between BOOT and PHASE pins (from datasheet RT8207, page 16)
Typical application circuits show direct connection of bootstrap capacitor without series resistance (from datasheet RT8207, page 3)
Actual bootstrap capacitor C309 is 0.1uF, which is 10x smaller than the recommended 1uF (reasoning)
Undersized bootstrap capacitor may cause insufficient gate drive voltage for high-side MOSFET, especially at high switching frequencies (reasoning)
Series resistor R298 (4.7Ω) is not shown in datasheet reference designs and will cause voltage drop during gate charging (reasoning)
The series resistor will slow bootstrap capacitor charging and may affect gate drive performance (reasoning)
Bootstrap capacitor should be increased to 1uF and series resistor should be removed to match datasheet recommendations (reasoning)

_{Replace a datasheet: 📤 U41}

[🚨 Error] **Component `U41`, pin `22`: BOOT pin connected to bootstrap network, but bootstrap capacitor C309 is significantly undersized (0.1uF instead of recommended 1uF) and includes non-standard series resistor R298 (4.7Ω), which may cause insufficient gate drive voltage and slower switching transitions.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="45.80,38.02,53.30,45.52" aspect-ratio="1.29" } - Pin 22 (BOOT) is connected to net $25N771 *(from schematic)* - Net $25N771 connects through R298 (4.7Ω resistor) to DDR_BST net *(from schematic)* - DDR_BST connects to C309 pin 2 (0.1uF capacitor) *(from schematic)* - C309 pin 1 connects to DDR_PHASE net (PHASE pin) *(from schematic)* - BOOT is the boost flying capacitor connection for VDDQ that supplies high side gate driver instantaneous current *(from datasheet [RT8207](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=2>), page 2)* - Datasheet recommends 1uF flying bootstrap capacitor between BOOT and PHASE pins *(from datasheet [RT8207](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=16>), page 16)* - Typical application circuits show direct connection of bootstrap capacitor without series resistance *(from datasheet [RT8207](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=3>), page 3)* - Actual bootstrap capacitor C309 is 0.1uF, which is 10x smaller than the recommended 1uF *(reasoning)* - Undersized bootstrap capacitor may cause insufficient gate drive voltage for high-side MOSFET, especially at high switching frequencies *(reasoning)* - Series resistor R298 (4.7Ω) is not shown in datasheet reference designs and will cause voltage drop during gate charging *(reasoning)* - The series resistor will slow bootstrap capacitor charging and may affect gate drive performance *(reasoning)* - Bootstrap capacitor should be increased to 1uF and series resistor should be removed to match datasheet recommendations *(reasoning)* Replace a datasheet: [📤 U41](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/RT8207)

Turbot.prj

AllSpiceAlice (Migrated from staging.allspice.dev) commented

2026-05-13 00:10:09 +00:00

[🚨 Error] Component R816, pins 1, 2: TON timing resistor has incorrect value of 464K; should be 806K per design specification to achieve the intended 285kHz switching frequency. Current value results in approximately 504kHz operation.

R816 pin 1 is connected to +5VSB net (from schematic)
R816 pin 2 is connected to net $25N1081 (TON pin of U41) (from schematic)
R816 value is 464K per component attributes (from schematic)
Schematic design note specifies 'Rton=806K, F=285KHz' (from schematic)
On-time formula is tON = 3.85p × RTON × VVDDQ / (VIN - 0.5) (from datasheet RT8207, page 15)
Switching frequency formula: f = (VIN - 0.5) / (3.85p × VIN × RTON) (from schematic)
With RTON=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 504kHz (reasoning)
With RTON=806K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 290kHz, matching the design note (reasoning)
The resistor value does not match the design specification, indicating an error in component selection (reasoning)
Higher switching frequency affects inductor selection, core losses, switching losses, and EMI performance (reasoning)
R816 should be changed from 464K to 806K to achieve the intended 285kHz switching frequency (reasoning)

_{Upload a datasheet: 📤 R816}

[🚨 Error] **Component `R816`, pins `1, 2`: TON timing resistor has incorrect value of 464K; should be 806K per design specification to achieve the intended 285kHz switching frequency. Current value results in approximately 504kHz operation.** !thumbnail[](Turbot.prj){ diff="AI-Evals/E2E-Turbot:05990542eebf7494ab9568ebcaeca5c0bea19065...d7be525b45f8281be2cd167e80b8125f2d34a3a0" pr="179" doc-id="1c71bf3d7946c343c7a6" diff-visibility="full" variant="default" view-coords="27.62,35.08,35.12,44.34" aspect-ratio="1.29" } - R816 pin 1 is connected to +5VSB net *(from schematic)* - R816 pin 2 is connected to net $25N1081 (TON pin of U41) *(from schematic)* - R816 value is 464K per component attributes *(from schematic)* - Schematic design note specifies 'Rton=806K, F=285KHz' *(from schematic)* - On-time formula is tON = 3.85p × RTON × VVDDQ / (VIN - 0.5) *(from datasheet [RT8207](<https://www.richtek.com/SaveDownload.aspx?specid=RT8207P#page=15>), page 15)* - Switching frequency formula: f = (VIN - 0.5) / (3.85p × VIN × RTON) *(from schematic)* - With RTON=464K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 504kHz *(reasoning)* - With RTON=806K, VVDDQ=1.35V, VIN=5V: calculated frequency is approximately 290kHz, matching the design note *(reasoning)* - The resistor value does not match the design specification, indicating an error in component selection *(reasoning)* - Higher switching frequency affects inductor selection, core losses, switching losses, and EMI performance *(reasoning)* - R816 should be changed from 464K to 806K to achieve the intended 285kHz switching frequency *(reasoning)* Upload a datasheet: [📤 R816](https://staging.allspice.dev/AI-Evals/E2E-Turbot/_upload/752c00bd/.allspice/datasheets/1120-0149)