E2E @ c6e30ffe - push to main #184

Closed

shrikanthup wants to merge 2 commits from refs/pull/184/head into main

shrikanthup commented

2026-05-15 16:19:43 +00:00

(Migrated from staging.allspice.dev)

Source: push to main
Ref: c6e30ffe3ac1966ed8063b8b6251d4bcc3fba134
Mode: e2e
Cache: enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache)
Cleanup: auto-closed after 7 days

Resolved config

{
  "dump_analysis_dir": "debug_dump",
  "libraries": [
    {
      "ipn_column": "IPN",
      "mpn_column": "MPN",
      "path": ".allspice/library.csv",
      "type": "csv"
    },
    {
      "digikey_client_id_env": "DIGIKEY_CLIENT_ID",
      "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET",
      "type": "digikey"
    }
  ]
}

Triggered at 2026-05-15T16:19:40.811269Z. Branch 9af1556e will be deleted on cleanup.

**Source:** push to main **Ref:** [`c6e30ffe3ac1966ed8063b8b6251d4bcc3fba134`](https://github.com/AllSpiceIO/connections-checker/tree/c6e30ffe3ac1966ed8063b8b6251d4bcc3fba134) **Mode:** e2e **Cache:** enabled (s3://allspice-storage-allspice-cloudstaging-staging/datasheet_cache) **Cleanup:** auto-closed after 7 days <details> <summary>Resolved config</summary> ```json { "dump_analysis_dir": "debug_dump", "libraries": [ { "ipn_column": "IPN", "mpn_column": "MPN", "path": ".allspice/library.csv", "type": "csv" }, { "digikey_client_id_env": "DIGIKEY_CLIENT_ID", "digikey_client_secret_env": "DIGIKEY_CLIENT_SECRET", "type": "digikey" } ] } ``` </details> Triggered at 2026-05-15T16:19:40.811269Z. Branch `9af1556e` will be deleted on cleanup.

AllSpiceAlice commented

2026-05-15 16:25:34 +00:00

(Migrated from staging.allspice.dev)

DRCY has reviewed this Design Review, and there should be a review posted below.

AllSpiceAlice (Migrated from staging.allspice.dev) reviewed 2026-05-15 17:06:49 +00:00

AllSpiceAlice (Migrated from staging.allspice.dev) left a comment

DRCY Connections Checker Review

DRCY reviewed the connections in the 25 page(s) that changed in this DR. From these pages, DRCY selected 10 component(s) to review, and found 7 potential issue(s) in 4 component(s). DRCY has posted comments on the schematic for each potential issue. For more details on the components reviewed and their connections, click on the dropdown below.

Component Details

DRCY selected and reviewed all connections from the following components of the schematic:

CPU1 - INTEL_ATOM_E3825_SOC ❌

DRCY flagged 2 potential issues in this component.

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
BC1	VGA_DDCCLK	CRT_CLK	❌	VGA_DDCCLK and VGA_DDCDATA pins are connected to 150-ohm pull-down resistors (R39 and R38 respectively) to ground. DDC signals use I2C protocol which requires pull-up resistors for proper operation, not pull-down resistors. If VGA is intentionally disabled, the 150-ohm value is too low for termination and should be 10K or higher to avoid excessive current draw. Pin BC1 (VGA_DDCCLK) connects to net CRT_CLK, which connects to R39 pin 1 (150-ohm resistor to ground) (from schematic) Pin BC2 (VGA_DDCDATA) connects to net CRT_DAT, which connects to R38 pin 1 (150-ohm resistor to ground) (from schematic) Pins BC1 and BC2 are designated as VGA_DDCCLK and VGA_DDCDATA respectively, implementing Display Data Channel using I2C protocol (from datasheet 140-0004628) I2C protocol requires pull-up resistors (typically 2.2K-10K ohms) on both SDA and SCL lines for proper operation (reasoning) Pull-down resistors prevent I2C bus from functioning correctly by holding the lines low (reasoning) If VGA is intentionally disabled, pull-down resistors could be used to terminate unused lines, but 150 ohms is too low (reasoning) At 3.3V, a 150-ohm pull-down would draw 22mA, which is excessive for termination (reasoning) Typical termination resistors for unused I2C lines are 10K or higher (reasoning) The schematic shows DDI1 interface is partially disabled (DDI1_DDCCLK and DDI1_HPD tied to ground), suggesting some display interfaces may be intentionally disabled (from schematic) VGA_IREF (pin AW1) is connected to a 357-ohm resistor to ground, suggesting VGA circuitry is at least partially implemented (from schematic) The 150-ohm pull-downs should be changed to pull-ups (2.2K-10K) if VGA is intended to be used, or to higher value pull-downs (10K+) if VGA is intentionally disabled (reasoning)
BC2	VGA_DDCDATA	CRT_DAT	❌	VGA_DDCCLK and VGA_DDCDATA pins are connected to 150-ohm pull-down resistors (R39 and R38 respectively) to ground. DDC signals use I2C protocol which requires pull-up resistors for proper operation, not pull-down resistors. If VGA is intentionally disabled, the 150-ohm value is too low for termination and should be 10K or higher to avoid excessive current draw. Pin BC1 (VGA_DDCCLK) connects to net CRT_CLK, which connects to R39 pin 1 (150-ohm resistor to ground) (from schematic) Pin BC2 (VGA_DDCDATA) connects to net CRT_DAT, which connects to R38 pin 1 (150-ohm resistor to ground) (from schematic) Pins BC1 and BC2 are designated as VGA_DDCCLK and VGA_DDCDATA respectively, implementing Display Data Channel using I2C protocol (from datasheet 140-0004628) I2C protocol requires pull-up resistors (typically 2.2K-10K ohms) on both SDA and SCL lines for proper operation (reasoning) Pull-down resistors prevent I2C bus from functioning correctly by holding the lines low (reasoning) If VGA is intentionally disabled, pull-down resistors could be used to terminate unused lines, but 150 ohms is too low (reasoning) At 3.3V, a 150-ohm pull-down would draw 22mA, which is excessive for termination (reasoning) Typical termination resistors for unused I2C lines are 10K or higher (reasoning) The schematic shows DDI1 interface is partially disabled (DDI1_DDCCLK and DDI1_HPD tied to ground), suggesting some display interfaces may be intentionally disabled (from schematic) VGA_IREF (pin AW1) is connected to a 357-ohm resistor to ground, suggesting VGA circuitry is at least partially implemented (from schematic) The 150-ohm pull-downs should be changed to pull-ups (2.2K-10K) if VGA is intended to be used, or to higher value pull-downs (10K+) if VGA is intentionally disabled (reasoning)
AK12	DDI0_RCOMP_P	DDI_RCOMP_N	❌	DDI compensation pins are swapped. Pin AK13 (DDI_RCOMP_N per datasheet) connects to DDI_RCOMP_P net, while pin AK12 (DDI0_RCOMP_P per datasheet) connects to DDI_RCOMP_N net. These connections should be reversed. Pin AK13 is connected to net DDI_RCOMP_P (from schematic) Pin AK12 is connected to net DDI_RCOMP_N (from schematic) Pin AK13 is designated as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (DDI_RCOMP_N with overline notation indicating negation) in the datasheet (from datasheet 140-0004628) Pin AK12 is designated as DDI0_RCOMP_P in the datasheet (from datasheet 140-0004628) Compensation resistor R217 (402 ohm) is connected between DDI_RCOMP_N and DDI_RCOMP_P nets (from schematic) The pin names in the datasheet clearly indicate AK13 should be the negative pin and AK12 should be the positive pin (reasoning) The net connections are reversed compared to the datasheet pin designations (reasoning) Pin AK13 should connect to DDI_RCOMP_N net and pin AK12 should connect to DDI_RCOMP_P net (reasoning)
AK13	~DDI0_RCOMP	DDI_RCOMP_P	❌	DDI compensation pins are swapped. Pin AK13 (DDI_RCOMP_N per datasheet) connects to DDI_RCOMP_P net, while pin AK12 (DDI0_RCOMP_P per datasheet) connects to DDI_RCOMP_N net. These connections should be reversed. Pin AK13 is connected to net DDI_RCOMP_P (from schematic) Pin AK12 is connected to net DDI_RCOMP_N (from schematic) Pin AK13 is designated as D̅D̅I̅0̅_̅R̅C̅O̅M̅P̅ (DDI_RCOMP_N with overline notation indicating negation) in the datasheet (from datasheet 140-0004628) Pin AK12 is designated as DDI0_RCOMP_P in the datasheet (from datasheet 140-0004628) Compensation resistor R217 (402 ohm) is connected between DDI_RCOMP_N and DDI_RCOMP_P nets (from schematic) The pin names in the datasheet clearly indicate AK13 should be the negative pin and AK12 should be the positive pin (reasoning) The net connections are reversed compared to the datasheet pin designations (reasoning) Pin AK13 should connect to DDI_RCOMP_N net and pin AK12 should connect to DDI_RCOMP_P net (reasoning)
A29	RESERVED_A29	GPIO_NC13	✅	RESERVED_A29 pin connected to GPIO_NC13 net with 10K pull-down resistor R102. This appears to be an intentional configuration for Bay Trail-I variant.
B30	GPIO_S0_NC12	$3N566	✅	GPIO_S0_NC12 pin connected to test point TP15 (DNI). This provides a test point for the GPIO signal.
C26	DDI0_DDCDATA	HDMI_DDCDAT	✅	DDI0_DDCDATA pin is correctly connected to HDMI_DDCDAT net for I2C-based Display Data Channel communication with HDMI display.
C28	DDI0_DDCCLK	HDMI_DDCCLK	✅	DDI0_DDCCLK pin is correctly connected to HDMI_DDCCLK net for I2C-based Display Data Channel communication with HDMI display.
D27	DDI0_HPD	HDMI_HPD_B	✅	DDI0_HPD pin correctly connected to HDMI_HPD_B net, which is the output of inverter U39 providing inverted hot plug detect signal.
G30	DDI1_DDCCLK	GND	✅	DDI1_DDCCLK pin tied to GND, intentionally disabling DDI1 interface as indicated by 'Bay Trail-M Remove eDP Port' note.
K30	DDI1_HPD	GND	✅	DDI1_HPD pin tied to GND, intentionally disabling DDI1 interface as indicated by 'Bay Trail-M Remove eDP Port' note.
P14	RESERVED_P14	MCSI_RCOMP	✅	RESERVED_P14 pin connected to MCSI_RCOMP net with 150-ohm resistor R213 to ground. This appears to be an intentional use for MCSI compensation as indicated by 'Bay Trail-I MCSI Port' note.
P30	DDI1_DDCDATA	DDI1_DDCDAT	✅	DDI1_DDCDATA pin connected to DDI1_DDCDAT net with 2.2K pull-down resistor R257. This is part of the DDI1 disable configuration.
AH2	RESERVED_VSS3	$3N554	✅	RESERVED_VSS3 pin connected through 0-ohm resistor R43 to GND, which is the correct configuration per datasheet recommendations.
AH3	RESERVED_VSS2	$3N552	✅	RESERVED_VSS2 pin connected through 0-ohm resistor R46 to GND, which is the correct configuration per datasheet recommendations.
AM2	RESERVED_VSS1	$3N589	✅	RESERVED_VSS1 pin connected through 0-ohm resistor R41 to GND, which is the correct configuration per datasheet recommendations.
AM3	RESERVED_VSS0	$3N579	✅	RESERVED_VSS0 pin connected through 0-ohm resistor R42 to GND, which is the correct configuration per datasheet recommendations.
AP2	DDI0_TXN_3	HDMI_CLK_DN	✅	DDI0 differential transmit pairs are correctly connected to HDMI signals with proper polarity. These high-speed differential pairs carry HDMI video data (three data lanes) and clock signals.
AP3	DDI0_TXP_3	HDMI_CLK_DP	✅	DDI0 differential transmit pairs are correctly connected to HDMI signals with proper polarity. These high-speed differential pairs carry HDMI video data (three data lanes) and clock signals.
AR1	DDI0_TXN_2	HDMI_TX0_DN	✅	DDI0 differential transmit pairs are correctly connected to HDMI signals with proper polarity. These high-speed differential pairs carry HDMI video data (three data lanes) and clock signals.
AR3	DDI0_TXP_2	HDMI_TX0_DP	✅	DDI0 differential transmit pairs are correctly connected to HDMI signals with proper polarity. These high-speed differential pairs carry HDMI video data (three data lanes) and clock signals.
AT2	DDI0_TXP_1	HDMI_TX1_DP	✅	DDI0 differential transmit pairs are correctly connected to HDMI signals with proper polarity. These high-speed differential pairs carry HDMI video data (three data lanes) and clock signals.
AT3	DDI0_TXN_1	HDMI_TX1_DN	✅	DDI0 differential transmit pairs are correctly connected to HDMI signals with proper polarity. These high-speed differential pairs carry HDMI video data (three data lanes) and clock signals.
AV2	DDI0_TXN_0	HDMI_TX2_DN	✅	DDI0 differential transmit pairs are correctly connected to HDMI signals with proper polarity. These high-speed differential pairs carry HDMI video data (three data lanes) and clock signals.
AV3	DDI0_TXP_0	HDMI_TX2_DP	✅	DDI0 differential transmit pairs are correctly connected to HDMI signals with proper polarity. These high-speed differential pairs carry HDMI video data (three data lanes) and clock signals.
AW1	VGA_IREF	$3N548	✅	VGA_IREF pin correctly connected to 357-ohm reference resistor R40 to ground, matching datasheet specifications for VGA DAC current reference.
AY3	VGA_IRTN	GND	✅	VGA_IRTN pin correctly connected to GND, serving as the current return path for the VGA DAC.

U39 - SN74LVC1G14DCKR ✅

DRCY found no issues in this component 🎉

📄 DRCY referred to this Datasheet for this component. 📤 Replace a datasheet

Pin Designator	Pin Name	Net	Correct?	Analysis
1	NC		✅	NC (No Connect) pin is correctly left unconnected.
2	A	HDMI_HPD	✅	Input pin A is correctly connected to HDMI_HPD signal for Schmitt-trigger inversion.
3	GND	GND	✅	Ground pin is correctly connected to GND.
4	Y	HDMI_HPD_B	✅	Output pin Y is correctly connected to HDMI_HPD_B, providing inverted HPD signal to CPU.
5	VCC	+V1P8S	✅	VCC pin is correctly connected to +V1P8S power rail with appropriate decoupling.

R39 - 150 ohm 1% 1/16W 0402 ❌

DRCY flagged 2 potential issues in this component.